Varun Wadekar | eea6dc1 | 2021-05-04 16:14:09 -0700 | [diff] [blame] | 1 | /* |
Varun Wadekar | f6e7c95 | 2022-01-25 03:39:28 -0800 | [diff] [blame^] | 2 | * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | eea6dc1 | 2021-05-04 16:14:09 -0700 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef GIC600AE_FMU_H |
| 8 | #define GIC600AE_FMU_H |
| 9 | |
| 10 | /******************************************************************************* |
| 11 | * GIC600-AE FMU register offsets and constants |
| 12 | ******************************************************************************/ |
| 13 | #define GICFMU_ERRFR_LO U(0x000) |
| 14 | #define GICFMU_ERRFR_HI U(0x004) |
| 15 | #define GICFMU_ERRCTLR_LO U(0x008) |
| 16 | #define GICFMU_ERRCTLR_HI U(0x00C) |
| 17 | #define GICFMU_ERRSTATUS_LO U(0x010) |
| 18 | #define GICFMU_ERRSTATUS_HI U(0x014) |
| 19 | #define GICFMU_ERRGSR_LO U(0xE00) |
| 20 | #define GICFMU_ERRGSR_HI U(0xE04) |
| 21 | #define GICFMU_KEY U(0xEA0) |
| 22 | #define GICFMU_PINGCTLR U(0xEA4) |
| 23 | #define GICFMU_PINGNOW U(0xEA8) |
| 24 | #define GICFMU_SMEN U(0xEB0) |
| 25 | #define GICFMU_SMINJERR U(0xEB4) |
| 26 | #define GICFMU_PINGMASK_LO U(0xEC0) |
| 27 | #define GICFMU_PINGMASK_HI U(0xEC4) |
| 28 | #define GICFMU_STATUS U(0xF00) |
| 29 | #define GICFMU_ERRIDR U(0xFC8) |
| 30 | |
| 31 | /* ERRCTLR bits */ |
| 32 | #define FMU_ERRCTLR_ED_BIT BIT(0) |
| 33 | #define FMU_ERRCTLR_CE_EN_BIT BIT(1) |
| 34 | #define FMU_ERRCTLR_UI_BIT BIT(2) |
| 35 | #define FMU_ERRCTLR_CI_BIT BIT(3) |
| 36 | |
| 37 | /* SMEN constants */ |
| 38 | #define FMU_SMEN_BLK_SHIFT U(8) |
| 39 | #define FMU_SMEN_SMID_SHIFT U(24) |
| 40 | |
| 41 | /* Error record IDs */ |
| 42 | #define FMU_BLK_GICD U(0) |
| 43 | #define FMU_BLK_SPICOL U(1) |
| 44 | #define FMU_BLK_WAKERQ U(2) |
| 45 | #define FMU_BLK_ITS0 U(4) |
| 46 | #define FMU_BLK_ITS1 U(5) |
| 47 | #define FMU_BLK_ITS2 U(6) |
| 48 | #define FMU_BLK_ITS3 U(7) |
| 49 | #define FMU_BLK_ITS4 U(8) |
| 50 | #define FMU_BLK_ITS5 U(9) |
| 51 | #define FMU_BLK_ITS6 U(10) |
| 52 | #define FMU_BLK_ITS7 U(11) |
| 53 | #define FMU_BLK_PPI0 U(12) |
| 54 | #define FMU_BLK_PPI1 U(13) |
| 55 | #define FMU_BLK_PPI2 U(14) |
| 56 | #define FMU_BLK_PPI3 U(15) |
| 57 | #define FMU_BLK_PPI4 U(16) |
| 58 | #define FMU_BLK_PPI5 U(17) |
| 59 | #define FMU_BLK_PPI6 U(18) |
| 60 | #define FMU_BLK_PPI7 U(19) |
| 61 | #define FMU_BLK_PPI8 U(20) |
| 62 | #define FMU_BLK_PPI9 U(21) |
| 63 | #define FMU_BLK_PPI10 U(22) |
| 64 | #define FMU_BLK_PPI11 U(23) |
| 65 | #define FMU_BLK_PPI12 U(24) |
| 66 | #define FMU_BLK_PPI13 U(25) |
| 67 | #define FMU_BLK_PPI14 U(26) |
| 68 | #define FMU_BLK_PPI15 U(27) |
| 69 | #define FMU_BLK_PPI16 U(28) |
| 70 | #define FMU_BLK_PPI17 U(29) |
| 71 | #define FMU_BLK_PPI18 U(30) |
| 72 | #define FMU_BLK_PPI19 U(31) |
| 73 | #define FMU_BLK_PPI20 U(32) |
| 74 | #define FMU_BLK_PPI21 U(33) |
| 75 | #define FMU_BLK_PPI22 U(34) |
| 76 | #define FMU_BLK_PPI23 U(35) |
| 77 | #define FMU_BLK_PPI24 U(36) |
| 78 | #define FMU_BLK_PPI25 U(37) |
| 79 | #define FMU_BLK_PPI26 U(38) |
| 80 | #define FMU_BLK_PPI27 U(39) |
| 81 | #define FMU_BLK_PPI28 U(40) |
| 82 | #define FMU_BLK_PPI29 U(41) |
| 83 | #define FMU_BLK_PPI30 U(42) |
| 84 | #define FMU_BLK_PPI31 U(43) |
| 85 | #define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF) |
| 86 | |
| 87 | /* Safety Mechamism limit */ |
| 88 | #define FMU_SMID_GICD_MAX U(33) |
Varun Wadekar | f6e7c95 | 2022-01-25 03:39:28 -0800 | [diff] [blame^] | 89 | #define FMU_SMID_PPI_MAX U(12) |
| 90 | #define FMU_SMID_ITS_MAX U(14) |
Varun Wadekar | eea6dc1 | 2021-05-04 16:14:09 -0700 | [diff] [blame] | 91 | #define FMU_SMID_SPICOL_MAX U(5) |
| 92 | #define FMU_SMID_WAKERQ_MAX U(2) |
Varun Wadekar | eea6dc1 | 2021-05-04 16:14:09 -0700 | [diff] [blame] | 93 | |
| 94 | /* MBIST Safety Mechanism ID */ |
| 95 | #define GICD_MBIST_REQ_ERROR U(23) |
| 96 | #define GICD_FMU_CLKGATE_ERROR U(33) |
| 97 | #define PPI_MBIST_REQ_ERROR U(10) |
| 98 | #define PPI_FMU_CLKGATE_ERROR U(12) |
| 99 | #define ITS_MBIST_REQ_ERROR U(13) |
| 100 | #define ITS_FMU_CLKGATE_ERROR U(14) |
| 101 | |
| 102 | /* ERRSTATUS bits */ |
Varun Wadekar | de19844 | 2022-01-24 05:45:15 -0800 | [diff] [blame] | 103 | #define FMU_ERRSTATUS_BLKID_SHIFT U(32) |
| 104 | #define FMU_ERRSTATUS_BLKID_MASK U(0xFF) |
| 105 | #define FMU_ERRSTATUS_V_BIT BIT(30) |
| 106 | #define FMU_ERRSTATUS_UE_BIT BIT(29) |
| 107 | #define FMU_ERRSTATUS_OV_BIT BIT(27) |
| 108 | #define FMU_ERRSTATUS_CE_BITS (BIT(25) | BIT(24)) |
| 109 | #define FMU_ERRSTATUS_CLEAR (FMU_ERRSTATUS_V_BIT | FMU_ERRSTATUS_UE_BIT | \ |
| 110 | FMU_ERRSTATUS_OV_BIT | FMU_ERRSTATUS_CE_BITS) |
| 111 | #define FMU_ERRSTATUS_IERR_MASK U(0xFF) |
| 112 | #define FMU_ERRSTATUS_IERR_SHIFT U(8) |
| 113 | #define FMU_ERRSTATUS_SERR_MASK U(0xFF) |
Varun Wadekar | eea6dc1 | 2021-05-04 16:14:09 -0700 | [diff] [blame] | 114 | |
| 115 | /* PINGCTLR constants */ |
| 116 | #define FMU_PINGCTLR_INTDIFF_SHIFT U(16) |
| 117 | #define FMU_PINGCTLR_TIMEOUTVAL_SHIFT U(4) |
| 118 | #define FMU_PINGCTLR_EN_BIT BIT(0) |
| 119 | |
| 120 | #ifndef __ASSEMBLER__ |
| 121 | |
| 122 | #include <stdint.h> |
| 123 | |
| 124 | #include <arch_helpers.h> |
| 125 | |
| 126 | /******************************************************************************* |
| 127 | * GIC600 FMU EL3 driver API |
| 128 | ******************************************************************************/ |
| 129 | uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n); |
| 130 | uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n); |
| 131 | uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n); |
| 132 | uint64_t gic_fmu_read_errgsr(uintptr_t base); |
| 133 | uint32_t gic_fmu_read_pingctlr(uintptr_t base); |
| 134 | uint32_t gic_fmu_read_pingnow(uintptr_t base); |
| 135 | uint64_t gic_fmu_read_pingmask(uintptr_t base); |
| 136 | uint32_t gic_fmu_read_status(uintptr_t base); |
| 137 | uint32_t gic_fmu_read_erridr(uintptr_t base); |
| 138 | void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val); |
| 139 | void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val); |
| 140 | void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val); |
| 141 | void gic_fmu_write_pingnow(uintptr_t base, uint32_t val); |
| 142 | void gic_fmu_write_smen(uintptr_t base, uint32_t val); |
| 143 | void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val); |
| 144 | void gic_fmu_write_pingmask(uintptr_t base, uint64_t val); |
Varun Wadekar | f6e7c95 | 2022-01-25 03:39:28 -0800 | [diff] [blame^] | 145 | void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid); |
Varun Wadekar | eea6dc1 | 2021-05-04 16:14:09 -0700 | [diff] [blame] | 146 | |
| 147 | void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en); |
| 148 | void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask, |
| 149 | unsigned int timeout_val, unsigned int interval_diff); |
| 150 | void gic600_fmu_print_sm_info(uint64_t base, unsigned int blk, unsigned int smid); |
Varun Wadekar | de19844 | 2022-01-24 05:45:15 -0800 | [diff] [blame] | 151 | int gic600_fmu_probe(uint64_t base, int *probe_data); |
| 152 | int gic600_fmu_ras_handler(uint64_t base, int probe_data); |
Varun Wadekar | eea6dc1 | 2021-05-04 16:14:09 -0700 | [diff] [blame] | 153 | |
| 154 | #endif /* __ASSEMBLER__ */ |
| 155 | |
| 156 | #endif /* GIC600AE_FMU_H */ |