Chungying Lu | a566cc9 | 2023-03-15 14:16:28 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <inttypes.h> |
| 8 | |
| 9 | /* TF-A system header */ |
| 10 | #include <common/debug.h> |
| 11 | #include <drivers/delay_timer.h> |
| 12 | #include <lib/mmio.h> |
| 13 | #include <lib/utils_def.h> |
| 14 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 15 | |
| 16 | /* Vendor header */ |
| 17 | #include "apusys.h" |
| 18 | #include "apusys_power.h" |
| 19 | #include <mtk_mmap_pool.h> |
| 20 | |
| 21 | static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeout_us) |
| 22 | { |
| 23 | uint32_t reg_val, count; |
| 24 | |
| 25 | count = timeout_us / APU_POLL_STEP_US; |
| 26 | if (count == 0) { |
| 27 | count = 1; |
| 28 | } |
| 29 | |
| 30 | do { |
| 31 | reg_val = mmio_read_32(reg); |
| 32 | if ((reg_val & mask) == value) { |
| 33 | return 0; |
| 34 | } |
| 35 | |
| 36 | udelay(APU_POLL_STEP_US); |
| 37 | } while (--count); |
| 38 | |
| 39 | ERROR(MODULE_TAG "Timeout polling APU register %#" PRIxPTR "\n", reg); |
| 40 | ERROR(MODULE_TAG "Read value 0x%x, expected 0x%x\n", reg_val, |
| 41 | (value == 0U) ? (reg_val & ~mask) : (reg_val | mask)); |
| 42 | |
| 43 | return -1; |
| 44 | } |
| 45 | |
| 46 | static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2) |
| 47 | { |
| 48 | unsigned int fvco = clk_rate; |
| 49 | unsigned int pcw_val; |
| 50 | unsigned int postdiv_val = 1; |
| 51 | unsigned int postdiv_reg = 0; |
| 52 | |
| 53 | while (fvco <= OUT_CLK_FREQ_MIN) { |
| 54 | postdiv_val = postdiv_val << 1; |
| 55 | postdiv_reg = postdiv_reg + 1; |
| 56 | fvco = fvco << 1; |
| 57 | } |
| 58 | |
| 59 | pcw_val = (fvco * (1 << DDS_SHIFT)) / BASIC_CLK_FREQ; |
| 60 | |
| 61 | if (postdiv_reg == 0) { |
| 62 | pcw_val = pcw_val * 2; |
| 63 | postdiv_val = postdiv_val << 1; |
| 64 | postdiv_reg = postdiv_reg + 1; |
| 65 | } |
| 66 | |
| 67 | *r1 = postdiv_reg; |
| 68 | *r2 = pcw_val; |
| 69 | } |
| 70 | |
| 71 | static void apu_pll_init(void) |
| 72 | { |
| 73 | const uint32_t pll_hfctl_cfg[PLL_NUM] = { |
| 74 | PLL4HPLL_FHCTL0_CFG, |
| 75 | PLL4HPLL_FHCTL1_CFG, |
| 76 | PLL4HPLL_FHCTL2_CFG, |
| 77 | PLL4HPLL_FHCTL3_CFG |
| 78 | }; |
| 79 | const uint32_t pll_con1[PLL_NUM] = { |
| 80 | PLL4H_PLL1_CON1, |
| 81 | PLL4H_PLL2_CON1, |
| 82 | PLL4H_PLL3_CON1, |
| 83 | PLL4H_PLL4_CON1 |
| 84 | }; |
| 85 | const uint32_t pll_fhctl_dds[PLL_NUM] = { |
| 86 | PLL4HPLL_FHCTL0_DDS, |
| 87 | PLL4HPLL_FHCTL1_DDS, |
| 88 | PLL4HPLL_FHCTL2_DDS, |
| 89 | PLL4HPLL_FHCTL3_DDS |
| 90 | }; |
| 91 | const uint32_t pll_freq_out[PLL_NUM] = { |
| 92 | APUPLL0_DEFAULT_FREQ, |
| 93 | APUPLL1_DEFAULT_FREQ, |
| 94 | APUPLL2_DEFAULT_FREQ, |
| 95 | APUPLL3_DEFAULT_FREQ |
| 96 | }; |
| 97 | uint32_t pcw_val, posdiv_val; |
| 98 | int pll_idx; |
| 99 | |
| 100 | mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_RST_CON, PLL4H_PLL_HP_SWRSTB); |
| 101 | mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_HP_EN, PLL4H_PLL_HP_EN); |
| 102 | mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_CLK_CON, PLL4H_PLL_HP_CLKEN); |
| 103 | |
| 104 | for (pll_idx = 0; pll_idx < PLL_NUM; pll_idx++) { |
| 105 | mmio_setbits_32(APU_PLL_BASE + pll_hfctl_cfg[pll_idx], (FHCTL0_EN | SFSTR0_EN)); |
| 106 | |
| 107 | posdiv_val = 0; |
| 108 | pcw_val = 0; |
| 109 | get_pll_pcw(pll_freq_out[pll_idx], &posdiv_val, &pcw_val); |
| 110 | |
| 111 | mmio_clrsetbits_32(APU_PLL_BASE + pll_con1[pll_idx], |
| 112 | (RG_PLL_POSDIV_MASK << RG_PLL_POSDIV_SFT), |
| 113 | (posdiv_val << RG_PLL_POSDIV_SFT)); |
| 114 | mmio_write_32(APU_PLL_BASE + pll_fhctl_dds[pll_idx], |
| 115 | (FHCTL_PLL_TGL_ORG | pcw_val)); |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | static void apu_acc_init(void) |
| 120 | { |
| 121 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR0, CGEN_SOC); |
| 122 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET0, HW_CTRL_EN); |
| 123 | |
| 124 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR1, CGEN_SOC); |
| 125 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET1, HW_CTRL_EN); |
| 126 | |
| 127 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR2, CGEN_SOC); |
| 128 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET2, HW_CTRL_EN); |
| 129 | mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET2, CLK_REQ_SW_EN); |
| 130 | |
| 131 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR3, CGEN_SOC); |
| 132 | mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET3, HW_CTRL_EN); |
| 133 | mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET3, CLK_REQ_SW_EN); |
| 134 | |
| 135 | mmio_write_32(APU_ACC_BASE + APU_ACC_CLK_INV_EN_SET, CLK_INV_EN); |
| 136 | } |
| 137 | |
| 138 | static void apu_buck_off_cfg(void) |
| 139 | { |
| 140 | mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_SET); |
| 141 | udelay(10); |
| 142 | |
| 143 | mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_SET); |
| 144 | udelay(10); |
| 145 | |
| 146 | mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_CLR); |
| 147 | udelay(10); |
| 148 | } |
| 149 | |
| 150 | static void apu_pcu_init(void) |
| 151 | { |
| 152 | uint32_t vapu_en_offset = BUCK_VAPU_PMIC_REG_EN_ADDR; |
| 153 | uint32_t vapu_sram_en_offset = BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR; |
| 154 | |
| 155 | mmio_write_32(APU_PCU_BASE + APU_PCU_CTRL_SET, AUTO_BUCK_EN); |
| 156 | |
| 157 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_STEP_SEL, BUCK_ON_OFF_CMD_EN); |
| 158 | |
| 159 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_L, |
| 160 | ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD)); |
| 161 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_H, CMD_OP); |
| 162 | |
| 163 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_L, |
| 164 | ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD)); |
| 165 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_H, CMD_OP); |
| 166 | |
| 167 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_L, |
| 168 | ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD)); |
| 169 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_H, CMD_OP); |
| 170 | |
| 171 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_L, |
| 172 | ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD)); |
| 173 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_H, CMD_OP); |
| 174 | |
| 175 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE0, APU_PCU_BUCK_ON_SETTLE_TIME); |
| 176 | mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE1, APU_PCU_BUCK_ON_SETTLE_TIME); |
| 177 | } |
| 178 | |
| 179 | static void apu_rpclite_init(void) |
| 180 | { |
| 181 | const uint32_t sleep_type_offset[] = { |
| 182 | APU_RPC_SW_TYPE2, |
| 183 | APU_RPC_SW_TYPE3, |
| 184 | APU_RPC_SW_TYPE4, |
| 185 | APU_RPC_SW_TYPE5, |
| 186 | APU_RPC_SW_TYPE6, |
| 187 | APU_RPC_SW_TYPE7, |
| 188 | APU_RPC_SW_TYPE8, |
| 189 | APU_RPC_SW_TYPE9 |
| 190 | }; |
| 191 | int ofs_arr_size = ARRAY_SIZE(sleep_type_offset); |
| 192 | int ofs_idx; |
| 193 | |
| 194 | for (ofs_idx = 0 ; ofs_idx < ofs_arr_size ; ofs_idx++) { |
| 195 | mmio_clrbits_32(APU_ACX0_RPC_LITE_BASE + sleep_type_offset[ofs_idx], |
| 196 | SW_TYPE); |
| 197 | } |
| 198 | |
| 199 | mmio_setbits_32(APU_ACX0_RPC_LITE_BASE + APU_RPC_TOP_SEL, RPC_CTRL); |
| 200 | } |
| 201 | |
| 202 | static void apu_rpc_init(void) |
| 203 | { |
| 204 | mmio_clrbits_32(APU_RPC_BASE + APU_RPC_SW_TYPE0, SW_TYPE); |
| 205 | mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, RPC_TOP_CTRL); |
| 206 | mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, RPC_TOP_CTRL1); |
| 207 | } |
| 208 | |
| 209 | static int apu_are_init(void) |
| 210 | { |
| 211 | int ret; |
| 212 | int are_id = 0; |
| 213 | const uint32_t are_base[APU_ARE_NUM] = { APU_ARE0_BASE, APU_ARE1_BASE, APU_ARE2_BASE }; |
| 214 | const uint32_t are_entry2_cfg_l[APU_ARE_NUM] = { |
| 215 | ARE0_ENTRY2_CFG_L, |
| 216 | ARE1_ENTRY2_CFG_L, |
| 217 | ARE2_ENTRY2_CFG_L |
| 218 | }; |
| 219 | |
| 220 | mmio_setbits_32(APU_AO_CTL_BASE + CSR_DUMMY_0_ADDR, VCORE_ARE_REQ); |
| 221 | |
| 222 | ret = apu_poll(APU_ARE2_BASE + APU_ARE_GLO_FSM, ARE_GLO_FSM_IDLE, ARE_GLO_FSM_IDLE, |
| 223 | APU_ARE_POLLING_TIMEOUT_US); |
| 224 | if (ret != 0) { |
| 225 | ERROR(MODULE_TAG "[%s][%d] ARE init timeout\n", |
| 226 | __func__, __LINE__); |
| 227 | return ret; |
| 228 | } |
| 229 | |
| 230 | for (are_id = APU_ARE0; are_id < APU_ARE_NUM; are_id++) { |
| 231 | mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_H, ARE_ENTRY0_SRAM_H_INIT); |
| 232 | mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_L, ARE_ENTRY0_SRAM_L_INIT); |
| 233 | |
| 234 | mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_H, ARE_ENTRY1_SRAM_H_INIT); |
| 235 | mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_L, ARE_ENTRY1_SRAM_L_INIT); |
| 236 | |
| 237 | mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H, ARE_ENTRY_CFG_H); |
| 238 | mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L, are_entry2_cfg_l[are_id]); |
| 239 | |
| 240 | mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H); |
| 241 | mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L); |
| 242 | |
| 243 | mmio_write_32(are_base[are_id] + APU_ARE_INI_CTRL, ARE_CONFG_INI); |
| 244 | } |
| 245 | |
| 246 | return ret; |
| 247 | } |
| 248 | |
| 249 | static void apu_aoc_init(void) |
| 250 | { |
| 251 | mmio_clrbits_32(SPM_BASE + APUSYS_BUCK_ISOLATION, IPU_EXT_BUCK_ISO); |
| 252 | mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_CLR); |
| 253 | udelay(10); |
| 254 | |
| 255 | mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_SET); |
| 256 | udelay(10); |
| 257 | |
| 258 | mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_CLR); |
| 259 | udelay(10); |
| 260 | |
| 261 | mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, SRAM_AOC_ISO_CLR); |
| 262 | udelay(10); |
| 263 | } |
| 264 | |
| 265 | static int init_hw_setting(void) |
| 266 | { |
| 267 | int ret; |
| 268 | |
| 269 | apu_aoc_init(); |
| 270 | apu_pcu_init(); |
| 271 | apu_rpc_init(); |
| 272 | apu_rpclite_init(); |
| 273 | |
| 274 | ret = apu_are_init(); |
| 275 | if (ret != 0) { |
| 276 | return ret; |
| 277 | } |
| 278 | |
| 279 | apu_pll_init(); |
| 280 | apu_acc_init(); |
| 281 | apu_buck_off_cfg(); |
| 282 | |
| 283 | return ret; |
| 284 | } |
| 285 | |
| 286 | int apusys_power_init(void) |
| 287 | { |
| 288 | int ret; |
| 289 | |
| 290 | ret = init_hw_setting(); |
| 291 | if (ret != 0) { |
| 292 | ERROR(MODULE_TAG "%s initial fail\n", __func__); |
| 293 | } else { |
| 294 | INFO(MODULE_TAG "%s initial done\n", __func__); |
| 295 | } |
| 296 | |
| 297 | return ret; |
| 298 | } |