Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | |
| 9 | #include <arch.h> |
| 10 | #include <lib/mmio.h> |
| 11 | |
| 12 | #include "msm8916_config.h" |
| 13 | #include "msm8916_gicv2.h" |
| 14 | #include <msm8916_mmap.h> |
| 15 | #include <platform_def.h> |
| 16 | |
| 17 | static void msm8916_configure_timer(void) |
| 18 | { |
| 19 | /* Set timer frequency */ |
| 20 | mmio_write_32(APCS_QTMR + CNTCTLBASE_CNTFRQ, PLAT_SYSCNT_FREQ); |
| 21 | |
| 22 | /* Make all timer frames available to non-secure world */ |
| 23 | mmio_write_32(APCS_QTMR + CNTNSAR, GENMASK_32(7, 0)); |
| 24 | } |
| 25 | |
| 26 | /* |
| 27 | * The APCS register regions always start with a SECURE register that should |
| 28 | * be cleared to 0 to only allow secure access. Since BL31 handles most of |
| 29 | * the CPU power management, most of them can be cleared to secure access only. |
| 30 | */ |
| 31 | #define APCS_GLB_SECURE_STS_NS BIT_32(0) |
| 32 | #define APCS_GLB_SECURE_PWR_NS BIT_32(1) |
| 33 | #define APCS_BOOT_START_ADDR_SEC (APCS_CFG + 0x04) |
| 34 | #define REMAP_EN BIT_32(0) |
| 35 | #define APCS_AA64NAA32_REG (APCS_CFG + 0x0c) |
| 36 | |
| 37 | static void msm8916_configure_cpu_pm(void) |
| 38 | { |
| 39 | unsigned int cpu; |
| 40 | |
| 41 | /* Disallow non-secure access to boot remapper / TCM registers */ |
| 42 | mmio_write_32(APCS_CFG, 0); |
| 43 | |
| 44 | /* |
| 45 | * Disallow non-secure access to power management registers. |
| 46 | * However, allow STS and PWR since those also seem to control access |
| 47 | * to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these |
| 48 | * bits are not set, CPU frequency control fails in the non-secure world. |
| 49 | */ |
| 50 | mmio_write_32(APCS_GLB, APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS); |
| 51 | |
| 52 | /* Disallow non-secure access to L2 SAW2 */ |
| 53 | mmio_write_32(APCS_L2_SAW2, 0); |
| 54 | |
| 55 | /* Disallow non-secure access to CPU ACS and SAW2 */ |
| 56 | for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { |
| 57 | mmio_write_32(APCS_ALIAS_ACS(cpu), 0); |
| 58 | mmio_write_32(APCS_ALIAS_SAW2(cpu), 0); |
| 59 | } |
| 60 | |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 61 | #ifdef __aarch64__ |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 62 | /* Make sure all further warm boots end up in BL31 and aarch64 state */ |
| 63 | CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned); |
| 64 | mmio_write_32(APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN); |
| 65 | mmio_write_32(APCS_AA64NAA32_REG, 1); |
Stephan Gerhold | b68e4e9 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 66 | #else |
| 67 | /* Make sure all further warm boots end up in BL32 */ |
| 68 | CASSERT((BL32_BASE & 0xffff) == 0, assert_bl32_base_64k_aligned); |
| 69 | mmio_write_32(APCS_BOOT_START_ADDR_SEC, BL32_BASE | REMAP_EN); |
| 70 | #endif |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | /* |
| 74 | * MSM8916 has a special "interrupt aggregation logic" in the APPS SMMU, |
| 75 | * which allows routing context bank interrupts to one of 3 interrupt numbers |
| 76 | * ("TZ/HYP/NS"). Route all interrupts to the non-secure interrupt number |
| 77 | * by default to avoid special setup on the non-secure side. |
| 78 | */ |
| 79 | #define CLK_OFF BIT_32(31) |
Stephan Gerhold | 419ebb8 | 2023-03-15 09:24:49 +0100 | [diff] [blame] | 80 | #define GCC_APSS_TCU_CBCR (GCC_BASE + 0x12018) |
| 81 | #define GCC_GFX_TCU_CBCR (GCC_BASE + 0x12020) |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 82 | #define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038) |
Stephan Gerhold | 419ebb8 | 2023-03-15 09:24:49 +0100 | [diff] [blame] | 83 | #define GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x3600c) |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 84 | #define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c) |
Stephan Gerhold | 419ebb8 | 2023-03-15 09:24:49 +0100 | [diff] [blame] | 85 | #define APSS_TCU_CLK_ENA BIT_32(1) |
| 86 | #define GFX_TCU_CLK_ENA BIT_32(2) |
| 87 | #define GFX_TBU_CLK_ENA BIT_32(3) |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 88 | #define SMMU_CFG_CLK_ENA BIT_32(12) |
| 89 | #define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000) |
| 90 | #define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff) |
| 91 | |
Stephan Gerhold | 419ebb8 | 2023-03-15 09:24:49 +0100 | [diff] [blame] | 92 | #define SMMU_SACR 0x010 |
| 93 | #define SMMU_SACR_CACHE_LOCK BIT_32(26) |
| 94 | #define SMMU_IDR7 0x03c |
| 95 | #define SMMU_IDR7_MINOR(val) (((val) >> 0) & 0xf) |
| 96 | #define SMMU_IDR7_MAJOR(val) (((val) >> 4) & 0xf) |
| 97 | |
| 98 | static void msm8916_smmu_cache_unlock(uintptr_t smmu_base, uintptr_t clk_cbcr) |
| 99 | { |
| 100 | uint32_t version; |
| 101 | |
| 102 | /* Wait for clock */ |
| 103 | while (mmio_read_32(clk_cbcr) & CLK_OFF) { |
| 104 | } |
| 105 | |
| 106 | version = mmio_read_32(smmu_base + SMMU_IDR7); |
| 107 | VERBOSE("SMMU(0x%lx) r%dp%d\n", smmu_base, |
| 108 | SMMU_IDR7_MAJOR(version), SMMU_IDR7_MINOR(version)); |
| 109 | |
| 110 | /* For SMMU r2p0+ clear CACHE_LOCK to allow writes to CBn_ACTLR */ |
| 111 | if (SMMU_IDR7_MAJOR(version) >= 2) { |
| 112 | mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK); |
| 113 | } |
| 114 | } |
| 115 | |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 116 | static void msm8916_configure_smmu(void) |
| 117 | { |
Stephan Gerhold | 419ebb8 | 2023-03-15 09:24:49 +0100 | [diff] [blame] | 118 | /* Enable SMMU clocks to enable register access */ |
| 119 | mmio_write_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA | |
| 120 | APSS_TCU_CLK_ENA | GFX_TCU_CLK_ENA | GFX_TBU_CLK_ENA); |
| 121 | |
| 122 | /* Wait for configuration clock */ |
Stephan Gerhold | fa35b80 | 2023-07-17 11:00:35 +0200 | [diff] [blame] | 123 | while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF) { |
| 124 | } |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 125 | |
| 126 | /* Route all context bank interrupts to non-secure interrupt */ |
| 127 | mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL); |
| 128 | |
Stephan Gerhold | 419ebb8 | 2023-03-15 09:24:49 +0100 | [diff] [blame] | 129 | /* Clear sACR.CACHE_LOCK bit if needed for MMU-500 r2p0+ */ |
| 130 | msm8916_smmu_cache_unlock(APPS_SMMU_BASE, GCC_APSS_TCU_CBCR); |
| 131 | msm8916_smmu_cache_unlock(GPU_SMMU_BASE, GCC_GFX_TCU_CBCR); |
| 132 | |
| 133 | /* |
| 134 | * Keep APCS vote for SMMU clocks for rest of booting process, but make |
| 135 | * sure other vote registers (such as RPM) do not keep permanent votes. |
| 136 | */ |
| 137 | VERBOSE("Clearing GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (was: 0x%x)\n", |
| 138 | mmio_read_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE)); |
| 139 | mmio_write_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE, 0); |
Stephan Gerhold | 4bc53a1 | 2022-08-28 15:18:55 +0200 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | void msm8916_configure(void) |
| 143 | { |
| 144 | msm8916_gicv2_configure(); |
| 145 | msm8916_configure_timer(); |
| 146 | msm8916_configure_cpu_pm(); |
| 147 | msm8916_configure_smmu(); |
| 148 | } |