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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A User Guide
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010011tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +000012Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +010013possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
Joel Huttonfe027712018-03-19 11:59:57 +000041The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
Dan Handley610e7e12018-03-01 18:44:00 +000051Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010052
53::
54
55 sudo apt-get install build-essential gcc make git libssl-dev
56
Dan Handley610e7e12018-03-01 18:44:00 +000057TF-A has been tested with `Linaro Release 17.10`_.
David Cunadob2de0992017-06-29 12:01:33 +010058
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010060The `Linaro Release Notes`_ documents which version of the compiler to use for a
61given Linaro Release. Also, these `Linaro instructions`_ provide further
62guidance and a script, which can be used to download Linaro deliverables
63automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
Dan Handley610e7e12018-03-01 18:44:00 +000065Optionally, TF-A can be built using clang or Arm Compiler 6.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010066See instructions below on how to switch the default compiler.
67
68In addition, the following optional packages and tools may be needed:
69
70- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
71 Tree (FDT) source files (``.dts`` files) provided with this software.
72
Dan Handley610e7e12018-03-01 18:44:00 +000073- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010074
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010075- To create and modify the diagram files included in the documentation, `Dia`_.
76 This tool can be found in most Linux distributions. Inkscape is needed to
77 generate the actual *.png files.
78
Dan Handley610e7e12018-03-01 18:44:00 +000079Getting the TF-A source code
80----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010081
Dan Handley610e7e12018-03-01 18:44:00 +000082Download the TF-A source code from Github:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010083
84::
85
86 git clone https://github.com/ARM-software/arm-trusted-firmware.git
87
Dan Handley610e7e12018-03-01 18:44:00 +000088Building TF-A
89-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010090
Dan Handley610e7e12018-03-01 18:44:00 +000091- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
92 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010093
94 For AArch64:
95
96 ::
97
98 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
99
100 For AArch32:
101
102 ::
103
104 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
105
Dan Handley610e7e12018-03-01 18:44:00 +0000106 It is possible to build TF-A using clang or Arm Compiler 6. To do so
107 ``CC`` needs to point to the clang or armclang binary. Only the compiler
108 is switched; the assembler and linker need to be provided by the GNU
109 toolchain, thus ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100110
Dan Handley610e7e12018-03-01 18:44:00 +0000111 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100112 to ``CC`` matches the string 'armclang'.
113
Dan Handley610e7e12018-03-01 18:44:00 +0000114 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100115
116 ::
117
118 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
119 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
120
121 Clang will be selected when the base name of the path assigned to ``CC``
122 contains the string 'clang'. This is to allow both clang and clang-X.Y
123 to work.
124
125 For AArch64 using clang:
126
127 ::
128
129 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
130 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
131
Dan Handley610e7e12018-03-01 18:44:00 +0000132- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100133
134 For AArch64:
135
136 ::
137
138 make PLAT=<platform> all
139
140 For AArch32:
141
142 ::
143
144 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
145
146 Notes:
147
148 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
149 `Summary of build options`_ for more information on available build
150 options.
151
152 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
153
154 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
155 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000156 provided by TF-A to demonstrate how PSCI Library can be integrated with
157 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
158 include other runtime services, for example Trusted OS services. A guide
159 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
160 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
163 image, is not compiled in by default. Refer to the
164 `Building the Test Secure Payload`_ section below.
165
166 - By default this produces a release version of the build. To produce a
167 debug version instead, refer to the "Debugging options" section below.
168
169 - The build process creates products in a ``build`` directory tree, building
170 the objects and binaries for each boot loader stage in separate
171 sub-directories. The following boot loader binary files are created
172 from the corresponding ELF files:
173
174 - ``build/<platform>/<build-type>/bl1.bin``
175 - ``build/<platform>/<build-type>/bl2.bin``
176 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
177 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
178
179 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
180 is either ``debug`` or ``release``. The actual number of images might differ
181 depending on the platform.
182
183- Build products for a specific build variant can be removed using:
184
185 ::
186
187 make DEBUG=<D> PLAT=<platform> clean
188
189 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
190
191 The build tree can be removed completely using:
192
193 ::
194
195 make realclean
196
197Summary of build options
198~~~~~~~~~~~~~~~~~~~~~~~~
199
Dan Handley610e7e12018-03-01 18:44:00 +0000200The TF-A build system supports the following build options. Unless mentioned
201otherwise, these options are expected to be specified at the build command
202line and are not to be modified in any component makefiles. Note that the
203build system doesn't track dependency for build options. Therefore, if any of
204the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100205performed.
206
207Common build options
208^^^^^^^^^^^^^^^^^^^^
209
210- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
211 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
212 directory containing the SP source, relative to the ``bl32/``; the directory
213 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
214
Dan Handley610e7e12018-03-01 18:44:00 +0000215- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
216 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
217 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100218
Dan Handley610e7e12018-03-01 18:44:00 +0000219- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
220 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
221 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
222 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100223
Dan Handley610e7e12018-03-01 18:44:00 +0000224- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
225 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
226 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100227
Dan Handley610e7e12018-03-01 18:44:00 +0000228- ``ARM_GIC_ARCH``: Choice of Arm GIC architecture version used by the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100229 Legacy GIC driver for implementing the platform GIC API. This API is used
230 by the interrupt management framework. Default is 2 (that is, version 2.0).
231 This build option is deprecated.
232
Dan Handley610e7e12018-03-01 18:44:00 +0000233- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000234 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
235 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
236 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
237 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100238
239- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000240 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
241 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000244 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100245
Roberto Vargasb1584272017-11-20 13:36:10 +0000246- ``BL2_AT_EL3``: This is an optional build option that enables the use of
247 BL2 at EL3 execution level.
248
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000249- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
250 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
251 the RW sections in RAM, while leaving the RO sections in place. This option
252 enable this use-case. For now, this option is only supported when BL2_AT_EL3
253 is set to '1'.
254
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100255- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000256 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
257 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100258
259- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
260 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
261 this file name will be used to save the key.
262
263- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000264 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
265 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100266
Summer Qin80726782017-04-20 16:28:39 +0100267- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
268 Trusted OS Extra1 image for the ``fip`` target.
269
270- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
271 Trusted OS Extra2 image for the ``fip`` target.
272
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100273- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
274 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
275 this file name will be used to save the key.
276
277- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000278 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
280- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
281 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
282 this file name will be used to save the key.
283
284- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
285 compilation of each build. It must be set to a C string (including quotes
286 where applicable). Defaults to a string that contains the time and date of
287 the compilation.
288
Dan Handley610e7e12018-03-01 18:44:00 +0000289- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A
290 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100291
292- ``CFLAGS``: Extra user options appended on the compiler's command line in
293 addition to the options set by the build system.
294
295- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
296 release several CPUs out of reset. It can take either 0 (several CPUs may be
297 brought up) or 1 (only one CPU will ever be brought up during cold reset).
298 Default is 0. If the platform always brings up a single CPU, there is no
299 need to distinguish between primary and secondary CPUs and the boot path can
300 be optimised. The ``plat_is_my_cpu_primary()`` and
301 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
302 to be implemented in this case.
303
304- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
305 register state when an unexpected exception occurs during execution of
306 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
307 this is only enabled for a debug build of the firmware.
308
309- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
310 certificate generation tool to create new keys in case no valid keys are
311 present or specified. Allowed options are '0' or '1'. Default is '1'.
312
313- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
314 the AArch32 system registers to be included when saving and restoring the
315 CPU context. The option must be set to 0 for AArch64-only platforms (that
316 is on hardware that does not implement AArch32, or at least not at EL1 and
317 higher ELs). Default value is 1.
318
319- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
320 registers to be included when saving and restoring the CPU context. Default
321 is 0.
322
323- ``DEBUG``: Chooses between a debug and release build. It can take either 0
324 (release) or 1 (debug) as values. 0 is the default.
325
Soby Mathew9fe88042018-03-26 12:43:37 +0100326- ``DYN_DISABLE_AUTH``: Enables the capability to disable Trusted Board Boot
327 authentication. This option is only meant to be enabled for development
328 platforms. Both TRUSTED_BOARD_BOOT and the LOAD_IMAGE_V2 flags need to be
329 set if this flag has to be enabled. 0 is the default.
330
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
332 the normal boot flow. It must specify the entry point address of the EL3
333 payload. Please refer to the "Booting an EL3 payload" section for more
334 details.
335
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100336- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100337 This is an optional architectural feature available on v8.4 onwards. Some
338 v8.2 implementations also implement an AMU and this option can be used to
339 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100340
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100341- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
342 are compiled out. For debug builds, this option defaults to 1, and calls to
343 ``assert()`` are left in place. For release builds, this option defaults to 0
344 and calls to ``assert()`` function are compiled out. This option can be set
345 independently of ``DEBUG``. It can also be used to hide any auxiliary code
346 that is only required for the assertion and does not fit in the assertion
347 itself.
348
349- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
350 Measurement Framework(PMF). Default is 0.
351
352- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
353 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
354 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
355 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
356 software.
357
358- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000359 instrumentation which injects timestamp collection points into TF-A to
360 allow runtime performance to be measured. Currently, only PSCI is
361 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
362 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100363
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100364- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100365 extensions. This is an optional architectural feature for AArch64.
366 The default is 1 but is automatically disabled when the target architecture
367 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100368
David Cunadoce88eee2017-10-20 11:30:57 +0100369- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
370 (SVE) for the Non-secure world only. SVE is an optional architectural feature
371 for AArch64. Note that when SVE is enabled for the Non-secure world, access
372 to SIMD and floating-point functionality from the Secure world is disabled.
373 This is to avoid corruption of the Non-secure world data in the Z-registers
374 which are aliased by the SIMD and FP registers. The build option is not
375 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
376 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
377 1. The default is 1 but is automatically disabled when the target
378 architecture is AArch32.
379
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100380- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
381 checks in GCC. Allowed values are "all", "strong" and "0" (default).
382 "strong" is the recommended stack protection level if this feature is
383 desired. 0 disables the stack protection. For all values other than 0, the
384 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
385 The value is passed as the last component of the option
386 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
387
388- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
389 deprecated platform APIs, helper functions or drivers within Trusted
390 Firmware as error. It can take the value 1 (flag the use of deprecated
391 APIs as error) or 0. The default is 0.
392
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100393- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
394 targeted at EL3. When set ``0`` (default), no exceptions are expected or
395 handled at EL3, and a panic will result. This is supported only for AArch64
396 builds.
397
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000398- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 externsions introduced support for fault
399 injection from lower ELs, and this build option enables lower ELs to use
400 Error Records accessed via System Registers to inject faults. This is
401 applicable only to AArch64 builds.
402
403 This feature is intended for testing purposes only, and is advisable to keep
404 disabled for production images.
405
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100406- ``FIP_NAME``: This is an optional build option which specifies the FIP
407 filename for the ``fip`` target. Default is ``fip.bin``.
408
409- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
410 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
411
412- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
413 tool to create certificates as per the Chain of Trust described in
414 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
415 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
416
417 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
418 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
419 the corresponding certificates, and to include those certificates in the
420 FIP and FWU\_FIP.
421
422 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
423 images will not include support for Trusted Board Boot. The FIP will still
424 include the corresponding certificates. This FIP can be used to verify the
425 Chain of Trust on the host machine through other mechanisms.
426
427 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
428 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
429 will not include the corresponding certificates, causing a boot failure.
430
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100431- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
432 inherent support for specific EL3 type interrupts. Setting this build option
433 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
434 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
435 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
436 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
437 the Secure Payload interrupts needs to be synchronously handed over to Secure
438 EL1 for handling. The default value of this option is ``0``, which means the
439 Group 0 interrupts are assumed to be handled by Secure EL1.
440
441 .. __: `platform-interrupt-controller-API.rst`
442 .. __: `interrupt-framework-design.rst`
443
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100444- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
445 will be always trapped in EL3 i.e. in BL31 at runtime.
446
Dan Handley610e7e12018-03-01 18:44:00 +0000447- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100448 software operations are required for CPUs to enter and exit coherency.
449 However, there exists newer systems where CPUs' entry to and exit from
450 coherency is managed in hardware. Such systems require software to only
451 initiate the operations, and the rest is managed in hardware, minimizing
Dan Handley610e7e12018-03-01 18:44:00 +0000452 active software management. In such systems, this boolean option enables
453 TF-A to carry out build and run-time optimizations during boot and power
454 management operations. This option defaults to 0 and if it is enabled,
455 then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100456
457- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
458 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
459 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
460 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
461 images.
462
Soby Mathew13b16052017-08-31 11:49:32 +0100463- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
464 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800465 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100466 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
467 retained only for compatibility. The default value of this flag is ``rsa``
468 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100469
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800470- ``HASH_ALG``: This build flag enables the user to select the secure hash
471 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
472 The default value of this flag is ``sha256``.
473
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100474- ``LDFLAGS``: Extra user options appended to the linkers' command line in
475 addition to the one set by the build system.
476
477- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
478 image loading, which provides more flexibility and scalability around what
479 images are loaded and executed during boot. Default is 0.
480 Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when
481 ``LOAD_IMAGE_V2`` is enabled.
482
483- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
484 output compiled into the build. This should be one of the following:
485
486 ::
487
488 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100489 10 (LOG_LEVEL_ERROR)
490 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100491 30 (LOG_LEVEL_WARNING)
492 40 (LOG_LEVEL_INFO)
493 50 (LOG_LEVEL_VERBOSE)
494
495 All log output up to and including the log level is compiled into the build.
496 The default value is 40 in debug builds and 20 in release builds.
497
498- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
499 specifies the file that contains the Non-Trusted World private key in PEM
500 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
501
502- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
503 optional. It is only needed if the platform makefile specifies that it
504 is required in order to build the ``fwu_fip`` target.
505
506- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
507 contents upon world switch. It can take either 0 (don't save and restore) or
508 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
509 wants the timer registers to be saved and restored.
510
511- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
512 the underlying hardware is not a full PL011 UART but a minimally compliant
513 generic UART, which is a subset of the PL011. The driver will not access
514 any register that is not part of the SBSA generic UART specification.
515 Default value is 0 (a full PL011 compliant UART is present).
516
Dan Handley610e7e12018-03-01 18:44:00 +0000517- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
518 must be subdirectory of any depth under ``plat/``, and must contain a
519 platform makefile named ``platform.mk``. For example, to build TF-A for the
520 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100521
522- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
523 instead of the normal boot flow. When defined, it must specify the entry
524 point address for the preloaded BL33 image. This option is incompatible with
525 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
526 over ``PRELOADED_BL33_BASE``.
527
528- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
529 vector address can be programmed or is fixed on the platform. It can take
530 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
531 programmable reset address, it is expected that a CPU will start executing
532 code directly at the right address, both on a cold and warm reset. In this
533 case, there is no need to identify the entrypoint on boot and the boot path
534 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
535 does not need to be implemented in this case.
536
537- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
538 possible for the PSCI power-state parameter viz original and extended
539 State-ID formats. This flag if set to 1, configures the generic PSCI layer
540 to use the extended format. The default value of this flag is 0, which
541 means by default the original power-state format is used by the PSCI
542 implementation. This flag should be specified by the platform makefile
543 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
Dan Handley610e7e12018-03-01 18:44:00 +0000544 smc function id. When this option is enabled on Arm platforms, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100545 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
546
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100547- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
548 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
549 or later CPUs.
550
551 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
552 set to ``1``.
553
554 This option is disabled by default.
555
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100556- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
557 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
558 entrypoint) or 1 (CPU reset to BL31 entrypoint).
559 The default value is 0.
560
Dan Handley610e7e12018-03-01 18:44:00 +0000561- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided
562 in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector
563 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
564 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100565
566- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
567 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
568 file name will be used to save the key.
569
570- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
571 certificate generation tool to save the keys used to establish the Chain of
572 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
573
574- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
575 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
576 target.
577
578- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
579 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
580 this file name will be used to save the key.
581
582- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
583 optional. It is only needed if the platform makefile specifies that it
584 is required in order to build the ``fwu_fip`` target.
585
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100586- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
587 Delegated Exception Interface to BL31 image. This defaults to ``0``.
588
589 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
590 set to ``1``.
591
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100592- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
593 isolated on separate memory pages. This is a trade-off between security and
594 memory usage. See "Isolating code and read-only data on separate memory
595 pages" section in `Firmware Design`_. This flag is disabled by default and
596 affects all BL images.
597
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100598- ``SMCCC_MAJOR_VERSION``: Numeric value that indicates the major version of
599 the SMC Calling Convention that the Trusted Firmware supports. The only two
600 allowed values are 1 and 2, and it defaults to 1. The minor version is
601 determined using this value.
602
Dan Handley610e7e12018-03-01 18:44:00 +0000603- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
604 This build option is only valid if ``ARCH=aarch64``. The value should be
605 the path to the directory containing the SPD source, relative to
606 ``services/spd/``; the directory is expected to contain a makefile called
607 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100608
609- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
610 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
611 execution in BL1 just before handing over to BL31. At this point, all
612 firmware images have been loaded in memory, and the MMU and caches are
613 turned off. Refer to the "Debugging options" section for more details.
614
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100615- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200616 secure interrupts (caught through the FIQ line). Platforms can enable
617 this directive if they need to handle such interruption. When enabled,
618 the FIQ are handled in monitor mode and non secure world is not allowed
619 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
620 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
621
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100622- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
623 Boot feature. When set to '1', BL1 and BL2 images include support to load
624 and verify the certificates and images in a FIP, and BL1 includes support
625 for the Firmware Update. The default value is '0'. Generation and inclusion
626 of certificates in the FIP and FWU\_FIP depends upon the value of the
627 ``GENERATE_COT`` option.
628
629 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
630 already exist in disk, they will be overwritten without further notice.
631
632- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
633 specifies the file that contains the Trusted World private key in PEM
634 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
635
636- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
637 synchronous, (see "Initializing a BL32 Image" section in
638 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
639 synchronous method) or 1 (BL32 is initialized using asynchronous method).
640 Default is 0.
641
642- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
643 routing model which routes non-secure interrupts asynchronously from TSP
644 to EL3 causing immediate preemption of TSP. The EL3 is responsible
645 for saving and restoring the TSP context in this routing model. The
646 default routing model (when the value is 0) is to route non-secure
647 interrupts to TSP allowing it to save its context and hand over
648 synchronously to EL3 via an SMC.
649
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000650 Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
651 must also be set to ``1``.
652
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100653- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
654 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000655 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100656 (Coherent memory region is included) or 0 (Coherent memory region is
657 excluded). Default is 1.
658
659- ``V``: Verbose build. If assigned anything other than 0, the build commands
660 are printed. Default is 0.
661
Dan Handley610e7e12018-03-01 18:44:00 +0000662- ``VERSION_STRING``: String used in the log output for each TF-A image.
663 Defaults to a string formed by concatenating the version number, build type
664 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100665
666- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
667 the CPU after warm boot. This is applicable for platforms which do not
668 require interconnect programming to enable cache coherency (eg: single
669 cluster platforms). If this option is enabled, then warm boot path
670 enables D-caches immediately after enabling MMU. This option defaults to 0.
671
Dan Handley610e7e12018-03-01 18:44:00 +0000672Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100673^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
674
675- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
676 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
677 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
678 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
679 flag.
680
681- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
682 of the memory reserved for each image. This affects the maximum size of each
683 BL image as well as the number of allocated memory regions and translation
684 tables. By default this flag is 0, which means it uses the default
Dan Handley610e7e12018-03-01 18:44:00 +0000685 unoptimised values for these macros. Arm development platforms that wish to
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100686 optimise memory usage need to set this flag to 1 and must override the
687 related macros.
688
689- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
690 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
691 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
692 match the frame used by the Non-Secure image (normally the Linux kernel).
693 Default is true (access to the frame is allowed).
694
695- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000696 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100697 an error is encountered during the boot process (for example, when an image
698 could not be loaded or authenticated). The watchdog is enabled in the early
699 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
700 Trusted Watchdog may be disabled at build time for testing or development
701 purposes.
702
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100703- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
704 have specific values at boot. This boolean option allows the Trusted Firmware
705 to have a Linux kernel image as BL33 by preparing the registers to these
706 values before jumping to BL33. This option defaults to 0 (disabled). For now,
707 it only supports AArch64 kernels. ``RESET_TO_BL31`` must be 1 when using it.
708 If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set to the
709 location of a device tree blob (DTB) already loaded in memory. The Linux
710 Image address must be specified using the ``PRELOADED_BL33_BASE`` option.
711
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100712- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
713 for the construction of composite state-ID in the power-state parameter.
714 The existing PSCI clients currently do not support this encoding of
715 State-ID yet. Hence this flag is used to configure whether to use the
716 recommended State-ID encoding or not. The default value of this flag is 0,
717 in which case the platform is configured to expect NULL in the State-ID
718 field of power-state parameter.
719
720- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
721 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000722 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100723 must be specified using the ``ROT_KEY`` option when building the Trusted
724 Firmware. This private key will be used by the certificate generation tool
725 to sign the BL2 and Trusted Key certificates. Available options for
726 ``ARM_ROTPK_LOCATION`` are:
727
728 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
729 registers. The private key corresponding to this ROTPK hash is not
730 currently available.
731 - ``devel_rsa`` : return a development public key hash embedded in the BL1
732 and BL2 binaries. This hash has been obtained from the RSA public key
733 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
734 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
735 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800736 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
737 and BL2 binaries. This hash has been obtained from the ECDSA public key
738 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
739 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
740 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100741
742- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
743
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800744 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100745 - ``tdram`` : Trusted DRAM (if available)
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800746 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
747 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100748
Dan Handley610e7e12018-03-01 18:44:00 +0000749- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
750 of the translation tables library instead of version 2. It is set to 0 by
751 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100752
Dan Handley610e7e12018-03-01 18:44:00 +0000753- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
754 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
755 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100756 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
757
Dan Handley610e7e12018-03-01 18:44:00 +0000758For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100759map is explained in the `Firmware Design`_.
760
Dan Handley610e7e12018-03-01 18:44:00 +0000761Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100762^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
763
764- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
765 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
766 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000767 TF-A no longer supports earlier SCP versions. If this option is set to 1
768 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100769
770- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
771 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
772 during boot. Default is 1.
773
Soby Mathew1ced6b82017-06-12 12:37:10 +0100774- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
775 instead of SCPI/BOM driver for communicating with the SCP during power
776 management operations and for SCP RAM Firmware transfer. If this option
777 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100778
Dan Handley610e7e12018-03-01 18:44:00 +0000779Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100780^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
781
782- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000783 build the topology tree within TF-A. By default TF-A is configured for dual
784 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100785
786- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
787 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
788 explained in the options below:
789
790 - ``FVP_CCI`` : The CCI driver is selected. This is the default
791 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
792 - ``FVP_CCN`` : The CCN driver is selected. This is the default
793 if ``FVP_CLUSTER_COUNT`` > 2.
794
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000795- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
796 a single cluster. This option defaults to 4.
797
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000798- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
799 in the system. This option defaults to 1. Note that the build option
800 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
801
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100802- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
803
804 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
805 - ``FVP_GICV2`` : The GICv2 only driver is selected
806 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
807 - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
Dan Handley610e7e12018-03-01 18:44:00 +0000808 Note: If TF-A is compiled with this option on FVPs with GICv3 hardware,
809 then it configures the hardware to run in GICv2 emulation mode
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100810
811- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
812 for functions that wait for an arbitrary time length (udelay and mdelay).
813 The default value is 0.
814
Soby Mathewb1bf0442018-02-16 14:52:52 +0000815- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
816 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
817 details on HW_CONFIG. By default, this is initialized to a sensible DTS
818 file in ``fdts/`` folder depending on other build options. But some cases,
819 like shifted affinity format for MPIDR, cannot be detected at build time
820 and this option is needed to specify the appropriate DTS file.
821
822- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
823 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
824 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
825 HW_CONFIG blob instead of the DTS file. This option is useful to override
826 the default HW_CONFIG selected by the build system.
827
Summer Qin13b95c22018-03-02 15:51:14 +0800828ARM JUNO platform specific build options
829^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
830
831- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
832 Media Protection (TZ-MP1). Default value of this flag is 0.
833
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100834Debugging options
835~~~~~~~~~~~~~~~~~
836
837To compile a debug version and make the build more verbose use
838
839::
840
841 make PLAT=<platform> DEBUG=1 V=1 all
842
843AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
844example DS-5) might not support this and may need an older version of DWARF
845symbols to be emitted by GCC. This can be achieved by using the
846``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
847version to 2 is recommended for DS-5 versions older than 5.16.
848
849When debugging logic problems it might also be useful to disable all compiler
850optimizations by using ``-O0``.
851
852NOTE: Using ``-O0`` could cause output images to be larger and base addresses
Dan Handley610e7e12018-03-01 18:44:00 +0000853might need to be recalculated (see the **Memory layout on Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100854platforms** section in the `Firmware Design`_).
855
856Extra debug options can be passed to the build system by setting ``CFLAGS`` or
857``LDFLAGS``:
858
859.. code:: makefile
860
861 CFLAGS='-O0 -gdwarf-2' \
862 make PLAT=<platform> DEBUG=1 V=1 all
863
864Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
865ignored as the linker is called directly.
866
867It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000868post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
869``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100870section. In this case, the developer may take control of the target using a
871debugger when indicated by the console output. When using DS-5, the following
872commands can be used:
873
874::
875
876 # Stop target execution
877 interrupt
878
879 #
880 # Prepare your debugging environment, e.g. set breakpoints
881 #
882
883 # Jump over the debug loop
884 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
885
886 # Resume execution
887 continue
888
889Building the Test Secure Payload
890~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
891
892The TSP is coupled with a companion runtime service in the BL31 firmware,
893called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
894must be recompiled as well. For more information on SPs and SPDs, see the
895`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
896
Dan Handley610e7e12018-03-01 18:44:00 +0000897First clean the TF-A build directory to get rid of any previous BL31 binary.
898Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100899
900::
901
902 make PLAT=<platform> SPD=tspd all
903
904An additional boot loader binary file is created in the ``build`` directory:
905
906::
907
908 build/<platform>/<build-type>/bl32.bin
909
910Checking source code style
911~~~~~~~~~~~~~~~~~~~~~~~~~~
912
913When making changes to the source for submission to the project, the source
914must be in compliance with the Linux style guide, and to assist with this check
915the project Makefile contains two targets, which both utilise the
916``checkpatch.pl`` script that ships with the Linux source tree.
917
Joel Huttonfe027712018-03-19 11:59:57 +0000918To check the entire source tree, you must first download copies of
919``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
920in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH``
921environment variable to point to ``checkpatch.pl`` (with the other 2 files in
922the same directory) and build the target
923checkcodebase:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100924
925::
926
927 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
928
929To just check the style on the files that differ between your local branch and
930the remote master, use:
931
932::
933
934 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
935
936If you wish to check your patch against something other than the remote master,
937set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
938is set to ``origin/master``.
939
940Building and using the FIP tool
941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
942
Dan Handley610e7e12018-03-01 18:44:00 +0000943Firmware Image Package (FIP) is a packaging format used by TF-A to package
944firmware images in a single binary. The number and type of images that should
945be packed in a FIP is platform specific and may include TF-A images and other
946firmware images required by the platform. For example, most platforms require
947a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
948U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100949
Dan Handley610e7e12018-03-01 18:44:00 +0000950The TF-A build system provides the make target ``fip`` to create a FIP file
951for the specified platform using the FIP creation tool included in the TF-A
952project. Examples below show how to build a FIP file for FVP, packaging TF-A
953and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100954
955For AArch64:
956
957::
958
959 make PLAT=fvp BL33=<path/to/bl33.bin> fip
960
961For AArch32:
962
963::
964
965 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
966
967Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
968UEFI, on FVP is not available upstream. Hence custom solutions are required to
969allow Linux boot on FVP. These instructions assume such a custom boot loader
970(BL33) is available.
971
972The resulting FIP may be found in:
973
974::
975
976 build/fvp/<build-type>/fip.bin
977
978For advanced operations on FIP files, it is also possible to independently build
979the tool and create or modify FIPs using this tool. To do this, follow these
980steps:
981
982It is recommended to remove old artifacts before building the tool:
983
984::
985
986 make -C tools/fiptool clean
987
988Build the tool:
989
990::
991
992 make [DEBUG=1] [V=1] fiptool
993
994The tool binary can be located in:
995
996::
997
998 ./tools/fiptool/fiptool
999
1000Invoking the tool with ``--help`` will print a help message with all available
1001options.
1002
1003Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1004
1005::
1006
1007 ./tools/fiptool/fiptool create \
1008 --tb-fw build/<platform>/<build-type>/bl2.bin \
1009 --soc-fw build/<platform>/<build-type>/bl31.bin \
1010 fip.bin
1011
1012Example 2: view the contents of an existing Firmware package:
1013
1014::
1015
1016 ./tools/fiptool/fiptool info <path-to>/fip.bin
1017
1018Example 3: update the entries of an existing Firmware package:
1019
1020::
1021
1022 # Change the BL2 from Debug to Release version
1023 ./tools/fiptool/fiptool update \
1024 --tb-fw build/<platform>/release/bl2.bin \
1025 build/<platform>/debug/fip.bin
1026
1027Example 4: unpack all entries from an existing Firmware package:
1028
1029::
1030
1031 # Images will be unpacked to the working directory
1032 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1033
1034Example 5: remove an entry from an existing Firmware package:
1035
1036::
1037
1038 ./tools/fiptool/fiptool remove \
1039 --tb-fw build/<platform>/debug/fip.bin
1040
1041Note that if the destination FIP file exists, the create, update and
1042remove operations will automatically overwrite it.
1043
1044The unpack operation will fail if the images already exist at the
1045destination. In that case, use -f or --force to continue.
1046
1047More information about FIP can be found in the `Firmware Design`_ document.
1048
1049Migrating from fip\_create to fiptool
1050^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1051
1052The previous version of fiptool was called fip\_create. A compatibility script
1053that emulates the basic functionality of the previous fip\_create is provided.
1054However, users are strongly encouraged to migrate to fiptool.
1055
1056- To create a new FIP file, replace "fip\_create" with "fiptool create".
1057- To update a FIP file, replace "fip\_create" with "fiptool update".
1058- To dump the contents of a FIP file, replace "fip\_create --dump"
1059 with "fiptool info".
1060
1061Building FIP images with support for Trusted Board Boot
1062~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1063
1064Trusted Board Boot primarily consists of the following two features:
1065
1066- Image Authentication, described in `Trusted Board Boot`_, and
1067- Firmware Update, described in `Firmware Update`_
1068
1069The following steps should be followed to build FIP and (optionally) FWU\_FIP
1070images with support for these features:
1071
1072#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1073 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001074 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001075 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001076 information. The latest version of TF-A is tested with tag
1077 ``mbedtls-2.6.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001078
1079 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1080 source files the modules depend upon.
1081 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1082 options required to build the mbed TLS sources.
1083
1084 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001085 license. Using mbed TLS source code will affect the licensing of TF-A
1086 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001087
1088#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001089 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001090
1091 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1092 - ``TRUSTED_BOARD_BOOT=1``
1093 - ``GENERATE_COT=1``
1094
Dan Handley610e7e12018-03-01 18:44:00 +00001095 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001096 specified at build time. Two locations are currently supported (see
1097 ``ARM_ROTPK_LOCATION`` build option):
1098
1099 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1100 root-key storage registers present in the platform. On Juno, this
1101 registers are read-only. On FVP Base and Cortex models, the registers
1102 are read-only, but the value can be specified using the command line
1103 option ``bp.trusted_key_storage.public_key`` when launching the model.
1104 On both Juno and FVP models, the default value corresponds to an
1105 ECDSA-SECP256R1 public key hash, whose private part is not currently
1106 available.
1107
1108 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001109 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001110 found in ``plat/arm/board/common/rotpk``.
1111
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001112 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001113 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001114 found in ``plat/arm/board/common/rotpk``.
1115
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001116 Example of command line using RSA development keys:
1117
1118 ::
1119
1120 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1121 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1122 ARM_ROTPK_LOCATION=devel_rsa \
1123 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1124 BL33=<path-to>/<bl33_image> \
1125 all fip
1126
1127 The result of this build will be the bl1.bin and the fip.bin binaries. This
1128 FIP will include the certificates corresponding to the Chain of Trust
1129 described in the TBBR-client document. These certificates can also be found
1130 in the output build directory.
1131
1132#. The optional FWU\_FIP contains any additional images to be loaded from
1133 Non-Volatile storage during the `Firmware Update`_ process. To build the
1134 FWU\_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001135 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001136
1137 - NS\_BL2U. The AP non-secure Firmware Updater image.
1138 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1139
1140 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1141 targets using RSA development:
1142
1143 ::
1144
1145 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1146 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1147 ARM_ROTPK_LOCATION=devel_rsa \
1148 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1149 BL33=<path-to>/<bl33_image> \
1150 SCP_BL2=<path-to>/<scp_bl2_image> \
1151 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1152 NS_BL2U=<path-to>/<ns_bl2u_image> \
1153 all fip fwu_fip
1154
1155 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1156 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1157 to the command line above.
1158
1159 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1160 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1161
1162 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1163 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1164 Chain of Trust described in the TBBR-client document. These certificates
1165 can also be found in the output build directory.
1166
1167Building the Certificate Generation Tool
1168~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1169
Dan Handley610e7e12018-03-01 18:44:00 +00001170The ``cert_create`` tool is built as part of the TF-A build process when the
1171``fip`` make target is specified and TBB is enabled (as described in the
1172previous section), but it can also be built separately with the following
1173command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001174
1175::
1176
1177 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1178
1179For platforms that do not require their own IDs in certificate files,
1180the generic 'cert\_create' tool can be built with the following command:
1181
1182::
1183
1184 make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
1185
1186``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1187verbose. The following command should be used to obtain help about the tool:
1188
1189::
1190
1191 ./tools/cert_create/cert_create -h
1192
1193Building a FIP for Juno and FVP
1194-------------------------------
1195
1196This section provides Juno and FVP specific instructions to build Trusted
1197Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001198a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001199
David Cunadob2de0992017-06-29 12:01:33 +01001200Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1201onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001202
Joel Huttonfe027712018-03-19 11:59:57 +00001203Note: Follow the full instructions for one platform before switching to a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001204different one. Mixing instructions for different platforms may result in
1205corrupted binaries.
1206
Joel Huttonfe027712018-03-19 11:59:57 +00001207Note: The uboot image downloaded by the Linaro workspace script does not always
1208match the uboot image packaged as BL33 in the corresponding fip file. It is
1209recommended to use the version that is packaged in the fip file using the
1210instructions below.
1211
Soby Mathewecd94ad2018-05-09 13:59:29 +01001212Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
1213by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1214section for more info on selecting the right FDT to use.
1215
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001216#. Clean the working directory
1217
1218 ::
1219
1220 make realclean
1221
1222#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1223
1224 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1225 package included in the Linaro release:
1226
1227 ::
1228
1229 # Build the fiptool
1230 make [DEBUG=1] [V=1] fiptool
1231
1232 # Unpack firmware images from Linaro FIP
1233 ./tools/fiptool/fiptool unpack \
1234 <path/to/linaro/release>/fip.bin
1235
1236 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001237 current working directory. The SCP\_BL2 image corresponds to
1238 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001239
Joel Huttonfe027712018-03-19 11:59:57 +00001240 Note: The fiptool will complain if the images to be unpacked already
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001241 exist in the current directory. If that is the case, either delete those
1242 files or use the ``--force`` option to overwrite.
1243
Joel Huttonfe027712018-03-19 11:59:57 +00001244 Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001245 Normal world boot loader that supports AArch32.
1246
Dan Handley610e7e12018-03-01 18:44:00 +00001247#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001248
1249 ::
1250
1251 # AArch64
1252 make PLAT=fvp BL33=nt-fw.bin all fip
1253
1254 # AArch32
1255 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1256
Dan Handley610e7e12018-03-01 18:44:00 +00001257#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001258
1259 For AArch64:
1260
1261 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1262 as a build parameter.
1263
1264 ::
1265
1266 make PLAT=juno all fip \
1267 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1268 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1269
1270 For AArch32:
1271
1272 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1273 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1274 separately for AArch32.
1275
1276 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1277 to the AArch32 Linaro cross compiler.
1278
1279 ::
1280
1281 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1282
1283 - Build BL32 in AArch32.
1284
1285 ::
1286
1287 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1288 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1289
1290 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1291 must point to the AArch64 Linaro cross compiler.
1292
1293 ::
1294
1295 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1296
1297 - The following parameters should be used to build BL1 and BL2 in AArch64
1298 and point to the BL32 file.
1299
1300 ::
1301
1302 make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
1303 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001304 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001305 BL32=<path-to-bl32>/bl32.bin all fip
1306
1307The resulting BL1 and FIP images may be found in:
1308
1309::
1310
1311 # Juno
1312 ./build/juno/release/bl1.bin
1313 ./build/juno/release/fip.bin
1314
1315 # FVP
1316 ./build/fvp/release/bl1.bin
1317 ./build/fvp/release/fip.bin
1318
Roberto Vargas096f3a02017-10-17 10:19:00 +01001319
1320Booting Firmware Update images
1321-------------------------------------
1322
1323When Firmware Update (FWU) is enabled there are at least 2 new images
1324that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1325FWU FIP.
1326
1327Juno
1328~~~~
1329
1330The new images must be programmed in flash memory by adding
1331an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1332on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1333Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1334programming" for more information. User should ensure these do not
1335overlap with any other entries in the file.
1336
1337::
1338
1339 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1340 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1341 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1342 NOR10LOAD: 00000000 ;Image Load Address
1343 NOR10ENTRY: 00000000 ;Image Entry Point
1344
1345 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1346 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1347 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1348 NOR11LOAD: 00000000 ;Image Load Address
1349
1350The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1351In the same way, the address ns_bl2u_base_address is the value of
1352NS_BL2U_BASE - 0x8000000.
1353
1354FVP
1355~~~
1356
1357The additional fip images must be loaded with:
1358
1359::
1360
1361 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1362 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1363
1364The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1365In the same way, the address ns_bl2u_base_address is the value of
1366NS_BL2U_BASE.
1367
1368
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001369EL3 payloads alternative boot flow
1370----------------------------------
1371
1372On a pre-production system, the ability to execute arbitrary, bare-metal code at
1373the highest exception level is required. It allows full, direct access to the
1374hardware, for example to run silicon soak tests.
1375
1376Although it is possible to implement some baremetal secure firmware from
1377scratch, this is a complex task on some platforms, depending on the level of
1378configuration required to put the system in the expected state.
1379
1380Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001381``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1382boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1383other BL images and passing control to BL31. It reduces the complexity of
1384developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001385
1386- putting the system into a known architectural state;
1387- taking care of platform secure world initialization;
1388- loading the SCP\_BL2 image if required by the platform.
1389
Dan Handley610e7e12018-03-01 18:44:00 +00001390When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001391TrustZone controller is simplified such that only region 0 is enabled and is
1392configured to permit secure access only. This gives full access to the whole
1393DRAM to the EL3 payload.
1394
1395The system is left in the same state as when entering BL31 in the default boot
1396flow. In particular:
1397
1398- Running in EL3;
1399- Current state is AArch64;
1400- Little-endian data access;
1401- All exceptions disabled;
1402- MMU disabled;
1403- Caches disabled.
1404
1405Booting an EL3 payload
1406~~~~~~~~~~~~~~~~~~~~~~
1407
1408The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001409not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001410
1411- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1412 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001413 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001414
1415- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1416 run-time.
1417
1418To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1419used. The infinite loop that it introduces in BL1 stops execution at the right
1420moment for a debugger to take control of the target and load the payload (for
1421example, over JTAG).
1422
1423It is expected that this loading method will work in most cases, as a debugger
1424connection is usually available in a pre-production system. The user is free to
1425use any other platform-specific mechanism to load the EL3 payload, though.
1426
1427Booting an EL3 payload on FVP
1428^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1429
1430The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1431the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1432is undefined on the FVP platform and the FVP platform code doesn't clear it.
1433Therefore, one must modify the way the model is normally invoked in order to
1434clear the mailbox at start-up.
1435
1436One way to do that is to create an 8-byte file containing all zero bytes using
1437the following command:
1438
1439::
1440
1441 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1442
1443and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1444using the following model parameters:
1445
1446::
1447
1448 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1449 --data=mailbox.dat@0x04000000 [Foundation FVP]
1450
1451To provide the model with the EL3 payload image, the following methods may be
1452used:
1453
1454#. If the EL3 payload is able to execute in place, it may be programmed into
1455 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1456 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1457 used for the FIP):
1458
1459 ::
1460
1461 -C bp.flashloader1.fname="/path/to/el3-payload"
1462
1463 On Foundation FVP, there is no flash loader component and the EL3 payload
1464 may be programmed anywhere in flash using method 3 below.
1465
1466#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1467 command may be used to load the EL3 payload ELF image over JTAG:
1468
1469 ::
1470
1471 load /path/to/el3-payload.elf
1472
1473#. The EL3 payload may be pre-loaded in volatile memory using the following
1474 model parameters:
1475
1476 ::
1477
1478 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1479 --data="/path/to/el3-payload"@address [Foundation FVP]
1480
1481 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001482 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001483
1484Booting an EL3 payload on Juno
1485^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1486
1487If the EL3 payload is able to execute in place, it may be programmed in flash
1488memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1489on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1490Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1491programming" for more information.
1492
1493Alternatively, the same DS-5 command mentioned in the FVP section above can
1494be used to load the EL3 payload's ELF file over JTAG on Juno.
1495
1496Preloaded BL33 alternative boot flow
1497------------------------------------
1498
1499Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001500on TF-A to load it. This may simplify packaging of the normal world code and
1501improve performance in a development environment. When secure world cold boot
1502is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001503
1504For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001505used when compiling TF-A. For example, the following command will create a FIP
1506without a BL33 and prepare to jump to a BL33 image loaded at address
15070x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001508
1509::
1510
1511 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1512
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001513Boot of a preloaded kernel image on Base FVP
1514~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001515
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001516The following example uses a simplified boot flow by directly jumping from the
1517TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1518useful if both the kernel and the device tree blob (DTB) are already present in
1519memory (like in FVP).
1520
1521For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1522address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001523
1524::
1525
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001526 CROSS_COMPILE=aarch64-linux-gnu- \
1527 make PLAT=fvp DEBUG=1 \
1528 RESET_TO_BL31=1 \
1529 ARM_LINUX_KERNEL_AS_BL33=1 \
1530 PRELOADED_BL33_BASE=0x80080000 \
1531 ARM_PRELOADED_DTB_BASE=0x82000000 \
1532 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001533
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001534Now, it is needed to modify the DTB so that the kernel knows the address of the
1535ramdisk. The following script generates a patched DTB from the provided one,
1536assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1537script assumes that the user is using a ramdisk image prepared for U-Boot, like
1538the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1539offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001540
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001541.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001542
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001543 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001544
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001545 # Path to the input DTB
1546 KERNEL_DTB=<path-to>/<fdt>
1547 # Path to the output DTB
1548 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1549 # Base address of the ramdisk
1550 INITRD_BASE=0x84000000
1551 # Path to the ramdisk
1552 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001553
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001554 # Skip uboot header (64 bytes)
1555 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1556 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1557 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1558
1559 CHOSEN_NODE=$(echo \
1560 "/ { \
1561 chosen { \
1562 linux,initrd-start = <${INITRD_START}>; \
1563 linux,initrd-end = <${INITRD_END}>; \
1564 }; \
1565 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001566
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001567 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1568 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001569
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001570And the FVP binary can be run with the following command:
1571
1572::
1573
1574 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1575 -C pctl.startup=0.0.0.0 \
1576 -C bp.secure_memory=1 \
1577 -C cluster0.NUM_CORES=4 \
1578 -C cluster1.NUM_CORES=4 \
1579 -C cache_state_modelled=1 \
1580 -C cluster0.cpu0.RVBAR=0x04020000 \
1581 -C cluster0.cpu1.RVBAR=0x04020000 \
1582 -C cluster0.cpu2.RVBAR=0x04020000 \
1583 -C cluster0.cpu3.RVBAR=0x04020000 \
1584 -C cluster1.cpu0.RVBAR=0x04020000 \
1585 -C cluster1.cpu1.RVBAR=0x04020000 \
1586 -C cluster1.cpu2.RVBAR=0x04020000 \
1587 -C cluster1.cpu3.RVBAR=0x04020000 \
1588 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1589 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1590 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1591 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1592
1593Boot of a preloaded kernel image on Juno
1594~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001595
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001596The Trusted Firmware must be compiled in a similar way as for FVP explained
1597above. The process to load binaries to memory is the one explained in
1598`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001599
1600Running the software on FVP
1601---------------------------
1602
David Cunado7c032642018-03-12 18:47:05 +00001603The latest version of the AArch64 build of TF-A has been tested on the following
1604Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1605(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001606
David Cunado82509be2017-12-19 16:33:25 +00001607NOTE: Unless otherwise stated, the model version is Version 11.2 Build 11.2.33.
David Cunado124415e2017-06-27 17:31:12 +01001608
1609- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001610- ``FVP_Base_AEMv8A-AEMv8A`` (and also Version 9.0, Build 0.8.9005)
David Cunado124415e2017-06-27 17:31:12 +01001611- ``FVP_Base_Cortex-A35x4``
1612- ``FVP_Base_Cortex-A53x4``
1613- ``FVP_Base_Cortex-A57x4-A53x4``
1614- ``FVP_Base_Cortex-A57x4``
1615- ``FVP_Base_Cortex-A72x4-A53x4``
1616- ``FVP_Base_Cortex-A72x4``
1617- ``FVP_Base_Cortex-A73x4-A53x4``
1618- ``FVP_Base_Cortex-A73x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001619
David Cunado7c032642018-03-12 18:47:05 +00001620Additionally, the AArch64 build was tested on the following Arm FVPs with
1621shifted affinities, supporting threaded CPU cores (64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001622
David Cunado7c032642018-03-12 18:47:05 +00001623- ``FVP_Base_Cortex-A55x4-A75x4`` (Version 0.0, build 0.0.4395)
1624- ``FVP_Base_Cortex-A55x4`` (Version 0.0, build 0.0.4395)
1625- ``FVP_Base_Cortex-A75x4`` (Version 0.0, build 0.0.4395)
1626- ``FVP_Base_RevC-2xAEMv8A``
1627
1628The latest version of the AArch32 build of TF-A has been tested on the following
1629Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1630(64-bit host machine only).
1631
1632- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001633- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001634
David Cunado7c032642018-03-12 18:47:05 +00001635NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1636is not compatible with legacy GIC configurations. Therefore this FVP does not
1637support these legacy GIC configurations.
1638
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001639NOTE: The build numbers quoted above are those reported by launching the FVP
1640with the ``--version`` parameter.
1641
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001642NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1643file systems that can be downloaded separately. To run an FVP with a virtio
1644file system image an additional FVP configuration option
1645``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1646used.
1647
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001648NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1649The commands below would report an ``unhandled argument`` error in this case.
1650
1651NOTE: FVPs can be launched with ``--cadi-server`` option such that a
Dan Handley610e7e12018-03-01 18:44:00 +00001652CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001653execution.
1654
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001655NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001656the internal synchronisation timings changed compared to older versions of the
1657models. The models can be launched with ``-Q 100`` option if they are required
1658to match the run time characteristics of the older versions.
1659
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001660The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001661downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001662
David Cunado124415e2017-06-27 17:31:12 +01001663The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001664`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001665
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001666Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001667parameter options. A brief description of the important ones that affect TF-A
1668and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001669
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001670Obtaining the Flattened Device Trees
1671~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1672
1673Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001674FDT files are required. FDT source files for the Foundation and Base FVPs can
1675be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1676a subset of the Base FVP components. For example, the Foundation FVP lacks
1677CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001678
1679Note: It is not recommended to use the FDTs built along the kernel because not
1680all FDTs are available from there.
1681
Soby Mathewecd94ad2018-05-09 13:59:29 +01001682The dynamic configuration capability is enabled in the firmware for FVPs.
1683This means that the firmware can authenticate and load the FDT if present in
1684FIP. A default FDT is packaged into FIP during the build based on
1685the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1686or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1687`Arm FVP platform specific build options`_ section for detail on the options).
1688
1689- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001690
David Cunado7c032642018-03-12 18:47:05 +00001691 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1692 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693
Soby Mathewecd94ad2018-05-09 13:59:29 +01001694- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001695
David Cunado7c032642018-03-12 18:47:05 +00001696 For use with models such as the Cortex-A32 Base FVPs without shifted
1697 affinities and running Linux in AArch32 state with Base memory map
1698 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001699
Soby Mathewecd94ad2018-05-09 13:59:29 +01001700- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001701
David Cunado7c032642018-03-12 18:47:05 +00001702 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1703 affinities and with Base memory map configuration and Linux GICv3 support.
1704
Soby Mathewecd94ad2018-05-09 13:59:29 +01001705- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001706
1707 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1708 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1709
Soby Mathewecd94ad2018-05-09 13:59:29 +01001710- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001711
1712 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1713 single cluster, single threaded CPUs, Base memory map configuration and Linux
1714 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001715
Soby Mathewecd94ad2018-05-09 13:59:29 +01001716- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001717
David Cunado7c032642018-03-12 18:47:05 +00001718 For use with models such as the Cortex-A32 Base FVPs without shifted
1719 affinities and running Linux in AArch32 state with Base memory map
1720 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001721
Soby Mathewecd94ad2018-05-09 13:59:29 +01001722- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001723
1724 For use with Foundation FVP with Base memory map configuration.
1725
Soby Mathewecd94ad2018-05-09 13:59:29 +01001726- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001727
1728 (Default) For use with Foundation FVP with Base memory map configuration
1729 and Linux GICv3 support.
1730
1731Running on the Foundation FVP with reset to BL1 entrypoint
1732~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1733
1734The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000017354 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001736
1737::
1738
1739 <path-to>/Foundation_Platform \
1740 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001741 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001742 --secure-memory \
1743 --visualization \
1744 --gicv3 \
1745 --data="<path-to>/<bl1-binary>"@0x0 \
1746 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001747 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001748 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001749
1750Notes:
1751
1752- BL1 is loaded at the start of the Trusted ROM.
1753- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001754- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1755 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001756- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1757 and enable the GICv3 device in the model. Note that without this option,
1758 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001759 is not supported by TF-A.
1760- In order for TF-A to run correctly on the Foundation FVP, the architecture
1761 versions must match. The Foundation FVP defaults to the highest v8.x
1762 version it supports but the default build for TF-A is for v8.0. To avoid
1763 issues either start the Foundation FVP to use v8.0 architecture using the
1764 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1765 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001766
1767Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1768~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1769
David Cunado7c032642018-03-12 18:47:05 +00001770The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001771with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001772
1773::
1774
David Cunado7c032642018-03-12 18:47:05 +00001775 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001776 -C pctl.startup=0.0.0.0 \
1777 -C bp.secure_memory=1 \
1778 -C bp.tzc_400.diagnostics=1 \
1779 -C cluster0.NUM_CORES=4 \
1780 -C cluster1.NUM_CORES=4 \
1781 -C cache_state_modelled=1 \
1782 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1783 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001784 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001785 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001786
1787Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1788~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1789
1790The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001791with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001792
1793::
1794
1795 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1796 -C pctl.startup=0.0.0.0 \
1797 -C bp.secure_memory=1 \
1798 -C bp.tzc_400.diagnostics=1 \
1799 -C cluster0.NUM_CORES=4 \
1800 -C cluster1.NUM_CORES=4 \
1801 -C cache_state_modelled=1 \
1802 -C cluster0.cpu0.CONFIG64=0 \
1803 -C cluster0.cpu1.CONFIG64=0 \
1804 -C cluster0.cpu2.CONFIG64=0 \
1805 -C cluster0.cpu3.CONFIG64=0 \
1806 -C cluster1.cpu0.CONFIG64=0 \
1807 -C cluster1.cpu1.CONFIG64=0 \
1808 -C cluster1.cpu2.CONFIG64=0 \
1809 -C cluster1.cpu3.CONFIG64=0 \
1810 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1811 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001812 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001813 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001814
1815Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1816~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1817
1818The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001819boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001820
1821::
1822
1823 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1824 -C pctl.startup=0.0.0.0 \
1825 -C bp.secure_memory=1 \
1826 -C bp.tzc_400.diagnostics=1 \
1827 -C cache_state_modelled=1 \
1828 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1829 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001830 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001831 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001832
1833Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1834~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1835
1836The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001837boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001838
1839::
1840
1841 <path-to>/FVP_Base_Cortex-A32x4 \
1842 -C pctl.startup=0.0.0.0 \
1843 -C bp.secure_memory=1 \
1844 -C bp.tzc_400.diagnostics=1 \
1845 -C cache_state_modelled=1 \
1846 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1847 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001848 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001849 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001850
1851Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1852~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1853
David Cunado7c032642018-03-12 18:47:05 +00001854The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001855with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001856
1857::
1858
David Cunado7c032642018-03-12 18:47:05 +00001859 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001860 -C pctl.startup=0.0.0.0 \
1861 -C bp.secure_memory=1 \
1862 -C bp.tzc_400.diagnostics=1 \
1863 -C cluster0.NUM_CORES=4 \
1864 -C cluster1.NUM_CORES=4 \
1865 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001866 -C cluster0.cpu0.RVBAR=0x04020000 \
1867 -C cluster0.cpu1.RVBAR=0x04020000 \
1868 -C cluster0.cpu2.RVBAR=0x04020000 \
1869 -C cluster0.cpu3.RVBAR=0x04020000 \
1870 -C cluster1.cpu0.RVBAR=0x04020000 \
1871 -C cluster1.cpu1.RVBAR=0x04020000 \
1872 -C cluster1.cpu2.RVBAR=0x04020000 \
1873 -C cluster1.cpu3.RVBAR=0x04020000 \
1874 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001875 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1876 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001877 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001878 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001879 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001880
1881Notes:
1882
1883- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1884 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1885 parameter is needed to load the individual bootloader images in memory.
1886 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01001887 Payload. For the same reason, the FDT needs to be compiled from the DT source
1888 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
1889 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001890
1891- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1892 X and Y are the cluster and CPU numbers respectively, is used to set the
1893 reset vector for each core.
1894
1895- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1896 changing the value of
1897 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1898 ``BL32_BASE``.
1899
1900Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1901~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1902
1903The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001904with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001905
1906::
1907
1908 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1909 -C pctl.startup=0.0.0.0 \
1910 -C bp.secure_memory=1 \
1911 -C bp.tzc_400.diagnostics=1 \
1912 -C cluster0.NUM_CORES=4 \
1913 -C cluster1.NUM_CORES=4 \
1914 -C cache_state_modelled=1 \
1915 -C cluster0.cpu0.CONFIG64=0 \
1916 -C cluster0.cpu1.CONFIG64=0 \
1917 -C cluster0.cpu2.CONFIG64=0 \
1918 -C cluster0.cpu3.CONFIG64=0 \
1919 -C cluster1.cpu0.CONFIG64=0 \
1920 -C cluster1.cpu1.CONFIG64=0 \
1921 -C cluster1.cpu2.CONFIG64=0 \
1922 -C cluster1.cpu3.CONFIG64=0 \
1923 -C cluster0.cpu0.RVBAR=0x04001000 \
1924 -C cluster0.cpu1.RVBAR=0x04001000 \
1925 -C cluster0.cpu2.RVBAR=0x04001000 \
1926 -C cluster0.cpu3.RVBAR=0x04001000 \
1927 -C cluster1.cpu0.RVBAR=0x04001000 \
1928 -C cluster1.cpu1.RVBAR=0x04001000 \
1929 -C cluster1.cpu2.RVBAR=0x04001000 \
1930 -C cluster1.cpu3.RVBAR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001931 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001932 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001933 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001934 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001935 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001936
1937Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1938It should match the address programmed into the RVBAR register as well.
1939
1940Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1942
1943The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001944boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001945
1946::
1947
1948 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1949 -C pctl.startup=0.0.0.0 \
1950 -C bp.secure_memory=1 \
1951 -C bp.tzc_400.diagnostics=1 \
1952 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001953 -C cluster0.cpu0.RVBARADDR=0x04020000 \
1954 -C cluster0.cpu1.RVBARADDR=0x04020000 \
1955 -C cluster0.cpu2.RVBARADDR=0x04020000 \
1956 -C cluster0.cpu3.RVBARADDR=0x04020000 \
1957 -C cluster1.cpu0.RVBARADDR=0x04020000 \
1958 -C cluster1.cpu1.RVBARADDR=0x04020000 \
1959 -C cluster1.cpu2.RVBARADDR=0x04020000 \
1960 -C cluster1.cpu3.RVBARADDR=0x04020000 \
1961 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001962 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001963 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001964 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001965 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001966 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001967
1968Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1969~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1970
1971The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001972boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001973
1974::
1975
1976 <path-to>/FVP_Base_Cortex-A32x4 \
1977 -C pctl.startup=0.0.0.0 \
1978 -C bp.secure_memory=1 \
1979 -C bp.tzc_400.diagnostics=1 \
1980 -C cache_state_modelled=1 \
1981 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1982 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1983 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1984 -C cluster0.cpu3.RVBARADDR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001985 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001986 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001987 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001988 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001989 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001990
1991Running the software on Juno
1992----------------------------
1993
Dan Handley610e7e12018-03-01 18:44:00 +00001994This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001995
1996To execute the software stack on Juno, the version of the Juno board recovery
1997image indicated in the `Linaro Release Notes`_ must be installed. If you have an
1998earlier version installed or are unsure which version is installed, please
1999re-install the recovery image by following the
2000`Instructions for using Linaro's deliverables on Juno`_.
2001
Dan Handley610e7e12018-03-01 18:44:00 +00002002Preparing TF-A images
2003~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002004
Dan Handley610e7e12018-03-01 18:44:00 +00002005After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2006``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002007
2008Other Juno software information
2009~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2010
Dan Handley610e7e12018-03-01 18:44:00 +00002011Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002012software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002013get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002014configure it.
2015
2016Testing SYSTEM SUSPEND on Juno
2017~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2018
2019The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2020to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2021on Juno, at the linux shell prompt, issue the following command:
2022
2023::
2024
2025 echo +10 > /sys/class/rtc/rtc0/wakealarm
2026 echo -n mem > /sys/power/state
2027
2028The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2029wakeup interrupt from RTC.
2030
2031--------------
2032
Dan Handley610e7e12018-03-01 18:44:00 +00002033*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002034
David Cunadob2de0992017-06-29 12:01:33 +01002035.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002036.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00002037.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
2038.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes#1710
2039.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
2040.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002041.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002042.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Joel Huttonfe027712018-03-19 11:59:57 +00002043.. _Linux master tree: <https://github.com/torvalds/linux/tree/master/>
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002044.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002045.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002046.. _Trusted Board Boot: trusted-board-boot.rst
Soby Mathewecd94ad2018-05-09 13:59:29 +01002047.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002048.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002049.. _Firmware Update: firmware-update.rst
2050.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002051.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2052.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002053.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002054.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002055.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002056.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf