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Yann Gautier740ca302023-06-14 18:00:58 +02001/*
Gabriel Fernandezbcd95062022-04-20 10:08:49 +02002 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
Yann Gautier740ca302023-06-14 18:00:58 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP2_RCC_H
8#define STM32MP2_RCC_H
9
10#include <lib/utils_def.h>
11
12#define RCC_SECCFGR0 U(0x0)
13#define RCC_SECCFGR1 U(0x4)
14#define RCC_SECCFGR2 U(0x8)
15#define RCC_SECCFGR3 U(0xC)
16#define RCC_PRIVCFGR0 U(0x10)
17#define RCC_PRIVCFGR1 U(0x14)
18#define RCC_PRIVCFGR2 U(0x18)
19#define RCC_PRIVCFGR3 U(0x1C)
20#define RCC_RCFGLOCKR0 U(0x20)
21#define RCC_RCFGLOCKR1 U(0x24)
22#define RCC_RCFGLOCKR2 U(0x28)
23#define RCC_RCFGLOCKR3 U(0x2C)
24#define RCC_R0CIDCFGR U(0x30)
25#define RCC_R0SEMCR U(0x34)
26#define RCC_R1CIDCFGR U(0x38)
27#define RCC_R1SEMCR U(0x3C)
28#define RCC_R2CIDCFGR U(0x40)
29#define RCC_R2SEMCR U(0x44)
30#define RCC_R3CIDCFGR U(0x48)
31#define RCC_R3SEMCR U(0x4C)
32#define RCC_R4CIDCFGR U(0x50)
33#define RCC_R4SEMCR U(0x54)
34#define RCC_R5CIDCFGR U(0x58)
35#define RCC_R5SEMCR U(0x5C)
36#define RCC_R6CIDCFGR U(0x60)
37#define RCC_R6SEMCR U(0x64)
38#define RCC_R7CIDCFGR U(0x68)
39#define RCC_R7SEMCR U(0x6C)
40#define RCC_R8CIDCFGR U(0x70)
41#define RCC_R8SEMCR U(0x74)
42#define RCC_R9CIDCFGR U(0x78)
43#define RCC_R9SEMCR U(0x7C)
44#define RCC_R10CIDCFGR U(0x80)
45#define RCC_R10SEMCR U(0x84)
46#define RCC_R11CIDCFGR U(0x88)
47#define RCC_R11SEMCR U(0x8C)
48#define RCC_R12CIDCFGR U(0x90)
49#define RCC_R12SEMCR U(0x94)
50#define RCC_R13CIDCFGR U(0x98)
51#define RCC_R13SEMCR U(0x9C)
52#define RCC_R14CIDCFGR U(0xA0)
53#define RCC_R14SEMCR U(0xA4)
54#define RCC_R15CIDCFGR U(0xA8)
55#define RCC_R15SEMCR U(0xAC)
56#define RCC_R16CIDCFGR U(0xB0)
57#define RCC_R16SEMCR U(0xB4)
58#define RCC_R17CIDCFGR U(0xB8)
59#define RCC_R17SEMCR U(0xBC)
60#define RCC_R18CIDCFGR U(0xC0)
61#define RCC_R18SEMCR U(0xC4)
62#define RCC_R19CIDCFGR U(0xC8)
63#define RCC_R19SEMCR U(0xCC)
64#define RCC_R20CIDCFGR U(0xD0)
65#define RCC_R20SEMCR U(0xD4)
66#define RCC_R21CIDCFGR U(0xD8)
67#define RCC_R21SEMCR U(0xDC)
68#define RCC_R22CIDCFGR U(0xE0)
69#define RCC_R22SEMCR U(0xE4)
70#define RCC_R23CIDCFGR U(0xE8)
71#define RCC_R23SEMCR U(0xEC)
72#define RCC_R24CIDCFGR U(0xF0)
73#define RCC_R24SEMCR U(0xF4)
74#define RCC_R25CIDCFGR U(0xF8)
75#define RCC_R25SEMCR U(0xFC)
76#define RCC_R26CIDCFGR U(0x100)
77#define RCC_R26SEMCR U(0x104)
78#define RCC_R27CIDCFGR U(0x108)
79#define RCC_R27SEMCR U(0x10C)
80#define RCC_R28CIDCFGR U(0x110)
81#define RCC_R28SEMCR U(0x114)
82#define RCC_R29CIDCFGR U(0x118)
83#define RCC_R29SEMCR U(0x11C)
84#define RCC_R30CIDCFGR U(0x120)
85#define RCC_R30SEMCR U(0x124)
86#define RCC_R31CIDCFGR U(0x128)
87#define RCC_R31SEMCR U(0x12C)
88#define RCC_R32CIDCFGR U(0x130)
89#define RCC_R32SEMCR U(0x134)
90#define RCC_R33CIDCFGR U(0x138)
91#define RCC_R33SEMCR U(0x13C)
92#define RCC_R34CIDCFGR U(0x140)
93#define RCC_R34SEMCR U(0x144)
94#define RCC_R35CIDCFGR U(0x148)
95#define RCC_R35SEMCR U(0x14C)
96#define RCC_R36CIDCFGR U(0x150)
97#define RCC_R36SEMCR U(0x154)
98#define RCC_R37CIDCFGR U(0x158)
99#define RCC_R37SEMCR U(0x15C)
100#define RCC_R38CIDCFGR U(0x160)
101#define RCC_R38SEMCR U(0x164)
102#define RCC_R39CIDCFGR U(0x168)
103#define RCC_R39SEMCR U(0x16C)
104#define RCC_R40CIDCFGR U(0x170)
105#define RCC_R40SEMCR U(0x174)
106#define RCC_R41CIDCFGR U(0x178)
107#define RCC_R41SEMCR U(0x17C)
108#define RCC_R42CIDCFGR U(0x180)
109#define RCC_R42SEMCR U(0x184)
110#define RCC_R43CIDCFGR U(0x188)
111#define RCC_R43SEMCR U(0x18C)
112#define RCC_R44CIDCFGR U(0x190)
113#define RCC_R44SEMCR U(0x194)
114#define RCC_R45CIDCFGR U(0x198)
115#define RCC_R45SEMCR U(0x19C)
116#define RCC_R46CIDCFGR U(0x1A0)
117#define RCC_R46SEMCR U(0x1A4)
118#define RCC_R47CIDCFGR U(0x1A8)
119#define RCC_R47SEMCR U(0x1AC)
120#define RCC_R48CIDCFGR U(0x1B0)
121#define RCC_R48SEMCR U(0x1B4)
122#define RCC_R49CIDCFGR U(0x1B8)
123#define RCC_R49SEMCR U(0x1BC)
124#define RCC_R50CIDCFGR U(0x1C0)
125#define RCC_R50SEMCR U(0x1C4)
126#define RCC_R51CIDCFGR U(0x1C8)
127#define RCC_R51SEMCR U(0x1CC)
128#define RCC_R52CIDCFGR U(0x1D0)
129#define RCC_R52SEMCR U(0x1D4)
130#define RCC_R53CIDCFGR U(0x1D8)
131#define RCC_R53SEMCR U(0x1DC)
132#define RCC_R54CIDCFGR U(0x1E0)
133#define RCC_R54SEMCR U(0x1E4)
134#define RCC_R55CIDCFGR U(0x1E8)
135#define RCC_R55SEMCR U(0x1EC)
136#define RCC_R56CIDCFGR U(0x1F0)
137#define RCC_R56SEMCR U(0x1F4)
138#define RCC_R57CIDCFGR U(0x1F8)
139#define RCC_R57SEMCR U(0x1FC)
140#define RCC_R58CIDCFGR U(0x200)
141#define RCC_R58SEMCR U(0x204)
142#define RCC_R59CIDCFGR U(0x208)
143#define RCC_R59SEMCR U(0x20C)
144#define RCC_R60CIDCFGR U(0x210)
145#define RCC_R60SEMCR U(0x214)
146#define RCC_R61CIDCFGR U(0x218)
147#define RCC_R61SEMCR U(0x21C)
148#define RCC_R62CIDCFGR U(0x220)
149#define RCC_R62SEMCR U(0x224)
150#define RCC_R63CIDCFGR U(0x228)
151#define RCC_R63SEMCR U(0x22C)
152#define RCC_R64CIDCFGR U(0x230)
153#define RCC_R64SEMCR U(0x234)
154#define RCC_R65CIDCFGR U(0x238)
155#define RCC_R65SEMCR U(0x23C)
156#define RCC_R66CIDCFGR U(0x240)
157#define RCC_R66SEMCR U(0x244)
158#define RCC_R67CIDCFGR U(0x248)
159#define RCC_R67SEMCR U(0x24C)
160#define RCC_R68CIDCFGR U(0x250)
161#define RCC_R68SEMCR U(0x254)
162#define RCC_R69CIDCFGR U(0x258)
163#define RCC_R69SEMCR U(0x25C)
164#define RCC_R70CIDCFGR U(0x260)
165#define RCC_R70SEMCR U(0x264)
166#define RCC_R71CIDCFGR U(0x268)
167#define RCC_R71SEMCR U(0x26C)
168#define RCC_R72CIDCFGR U(0x270)
169#define RCC_R72SEMCR U(0x274)
170#define RCC_R73CIDCFGR U(0x278)
171#define RCC_R73SEMCR U(0x27C)
172#define RCC_R74CIDCFGR U(0x280)
173#define RCC_R74SEMCR U(0x284)
174#define RCC_R75CIDCFGR U(0x288)
175#define RCC_R75SEMCR U(0x28C)
176#define RCC_R76CIDCFGR U(0x290)
177#define RCC_R76SEMCR U(0x294)
178#define RCC_R77CIDCFGR U(0x298)
179#define RCC_R77SEMCR U(0x29C)
180#define RCC_R78CIDCFGR U(0x2A0)
181#define RCC_R78SEMCR U(0x2A4)
182#define RCC_R79CIDCFGR U(0x2A8)
183#define RCC_R79SEMCR U(0x2AC)
184#define RCC_R80CIDCFGR U(0x2B0)
185#define RCC_R80SEMCR U(0x2B4)
186#define RCC_R81CIDCFGR U(0x2B8)
187#define RCC_R81SEMCR U(0x2BC)
188#define RCC_R82CIDCFGR U(0x2C0)
189#define RCC_R82SEMCR U(0x2C4)
190#define RCC_R83CIDCFGR U(0x2C8)
191#define RCC_R83SEMCR U(0x2CC)
192#define RCC_R84CIDCFGR U(0x2D0)
193#define RCC_R84SEMCR U(0x2D4)
194#define RCC_R85CIDCFGR U(0x2D8)
195#define RCC_R85SEMCR U(0x2DC)
196#define RCC_R86CIDCFGR U(0x2E0)
197#define RCC_R86SEMCR U(0x2E4)
198#define RCC_R87CIDCFGR U(0x2E8)
199#define RCC_R87SEMCR U(0x2EC)
200#define RCC_R88CIDCFGR U(0x2F0)
201#define RCC_R88SEMCR U(0x2F4)
202#define RCC_R89CIDCFGR U(0x2F8)
203#define RCC_R89SEMCR U(0x2FC)
204#define RCC_R90CIDCFGR U(0x300)
205#define RCC_R90SEMCR U(0x304)
206#define RCC_R91CIDCFGR U(0x308)
207#define RCC_R91SEMCR U(0x30C)
208#define RCC_R92CIDCFGR U(0x310)
209#define RCC_R92SEMCR U(0x314)
210#define RCC_R93CIDCFGR U(0x318)
211#define RCC_R93SEMCR U(0x31C)
212#define RCC_R94CIDCFGR U(0x320)
213#define RCC_R94SEMCR U(0x324)
214#define RCC_R95CIDCFGR U(0x328)
215#define RCC_R95SEMCR U(0x32C)
216#define RCC_R96CIDCFGR U(0x330)
217#define RCC_R96SEMCR U(0x334)
218#define RCC_R97CIDCFGR U(0x338)
219#define RCC_R97SEMCR U(0x33C)
220#define RCC_R98CIDCFGR U(0x340)
221#define RCC_R98SEMCR U(0x344)
222#define RCC_R99CIDCFGR U(0x348)
223#define RCC_R99SEMCR U(0x34C)
224#define RCC_R100CIDCFGR U(0x350)
225#define RCC_R100SEMCR U(0x354)
226#define RCC_R101CIDCFGR U(0x358)
227#define RCC_R101SEMCR U(0x35C)
228#define RCC_R102CIDCFGR U(0x360)
229#define RCC_R102SEMCR U(0x364)
230#define RCC_R103CIDCFGR U(0x368)
231#define RCC_R103SEMCR U(0x36C)
232#define RCC_R104CIDCFGR U(0x370)
233#define RCC_R104SEMCR U(0x374)
234#define RCC_R105CIDCFGR U(0x378)
235#define RCC_R105SEMCR U(0x37C)
236#define RCC_R106CIDCFGR U(0x380)
237#define RCC_R106SEMCR U(0x384)
238#define RCC_R107CIDCFGR U(0x388)
239#define RCC_R107SEMCR U(0x38C)
240#define RCC_R108CIDCFGR U(0x390)
241#define RCC_R108SEMCR U(0x394)
242#define RCC_R109CIDCFGR U(0x398)
243#define RCC_R109SEMCR U(0x39C)
244#define RCC_R110CIDCFGR U(0x3A0)
245#define RCC_R110SEMCR U(0x3A4)
246#define RCC_R111CIDCFGR U(0x3A8)
247#define RCC_R111SEMCR U(0x3AC)
248#define RCC_R112CIDCFGR U(0x3B0)
249#define RCC_R112SEMCR U(0x3B4)
250#define RCC_R113CIDCFGR U(0x3B8)
251#define RCC_R113SEMCR U(0x3BC)
252#define RCC_GRSTCSETR U(0x400)
253#define RCC_C1RSTCSETR U(0x404)
254#define RCC_C1P1RSTCSETR U(0x408)
255#define RCC_C2RSTCSETR U(0x40C)
256#define RCC_HWRSTSCLRR U(0x410)
257#define RCC_C1HWRSTSCLRR U(0x414)
258#define RCC_C2HWRSTSCLRR U(0x418)
259#define RCC_C1BOOTRSTSSETR U(0x41C)
260#define RCC_C1BOOTRSTSCLRR U(0x420)
261#define RCC_C2BOOTRSTSSETR U(0x424)
262#define RCC_C2BOOTRSTSCLRR U(0x428)
263#define RCC_C1SREQSETR U(0x42C)
264#define RCC_C1SREQCLRR U(0x430)
265#define RCC_CPUBOOTCR U(0x434)
266#define RCC_STBYBOOTCR U(0x438)
267#define RCC_LEGBOOTCR U(0x43C)
268#define RCC_BDCR U(0x440)
269#define RCC_D3DCR U(0x444)
270#define RCC_D3DSR U(0x448)
271#define RCC_RDCR U(0x44C)
272#define RCC_C1MSRDCR U(0x450)
273#define RCC_PWRLPDLYCR U(0x454)
274#define RCC_C1CIESETR U(0x458)
275#define RCC_C1CIFCLRR U(0x45C)
276#define RCC_C2CIESETR U(0x460)
277#define RCC_C2CIFCLRR U(0x464)
278#define RCC_IWDGC1FZSETR U(0x468)
279#define RCC_IWDGC1FZCLRR U(0x46C)
280#define RCC_IWDGC1CFGSETR U(0x470)
281#define RCC_IWDGC1CFGCLRR U(0x474)
282#define RCC_IWDGC2FZSETR U(0x478)
283#define RCC_IWDGC2FZCLRR U(0x47C)
284#define RCC_IWDGC2CFGSETR U(0x480)
285#define RCC_IWDGC2CFGCLRR U(0x484)
286#define RCC_IWDGC3CFGSETR U(0x488)
287#define RCC_IWDGC3CFGCLRR U(0x48C)
288#define RCC_C3CFGR U(0x490)
289#define RCC_MCO1CFGR U(0x494)
290#define RCC_MCO2CFGR U(0x498)
291#define RCC_OCENSETR U(0x49C)
292#define RCC_OCENCLRR U(0x4A0)
293#define RCC_OCRDYR U(0x4A4)
294#define RCC_HSICFGR U(0x4A8)
295#define RCC_CSICFGR U(0x4AC)
296#define RCC_RTCDIVR U(0x4B0)
297#define RCC_APB1DIVR U(0x4B4)
298#define RCC_APB2DIVR U(0x4B8)
299#define RCC_APB3DIVR U(0x4BC)
300#define RCC_APB4DIVR U(0x4C0)
301#define RCC_APBDBGDIVR U(0x4C4)
302#define RCC_TIMG1PRER U(0x4C8)
303#define RCC_TIMG2PRER U(0x4CC)
304#define RCC_LSMCUDIVR U(0x4D0)
305#define RCC_DDRCPCFGR U(0x4D4)
306#define RCC_DDRCAPBCFGR U(0x4D8)
307#define RCC_DDRPHYCAPBCFGR U(0x4DC)
308#define RCC_DDRPHYCCFGR U(0x4E0)
309#define RCC_DDRCFGR U(0x4E4)
310#define RCC_DDRITFCFGR U(0x4E8)
311#define RCC_SYSRAMCFGR U(0x4F0)
312#define RCC_VDERAMCFGR U(0x4F4)
313#define RCC_SRAM1CFGR U(0x4F8)
314#define RCC_SRAM2CFGR U(0x4FC)
315#define RCC_RETRAMCFGR U(0x500)
316#define RCC_BKPSRAMCFGR U(0x504)
317#define RCC_LPSRAM1CFGR U(0x508)
318#define RCC_LPSRAM2CFGR U(0x50C)
319#define RCC_LPSRAM3CFGR U(0x510)
320#define RCC_OSPI1CFGR U(0x514)
321#define RCC_OSPI2CFGR U(0x518)
322#define RCC_FMCCFGR U(0x51C)
323#define RCC_DBGCFGR U(0x520)
324#define RCC_STM500CFGR U(0x524)
325#define RCC_ETRCFGR U(0x528)
326#define RCC_GPIOACFGR U(0x52C)
327#define RCC_GPIOBCFGR U(0x530)
328#define RCC_GPIOCCFGR U(0x534)
329#define RCC_GPIODCFGR U(0x538)
330#define RCC_GPIOECFGR U(0x53C)
331#define RCC_GPIOFCFGR U(0x540)
332#define RCC_GPIOGCFGR U(0x544)
333#define RCC_GPIOHCFGR U(0x548)
334#define RCC_GPIOICFGR U(0x54C)
335#define RCC_GPIOJCFGR U(0x550)
336#define RCC_GPIOKCFGR U(0x554)
337#define RCC_GPIOZCFGR U(0x558)
338#define RCC_HPDMA1CFGR U(0x55C)
339#define RCC_HPDMA2CFGR U(0x560)
340#define RCC_HPDMA3CFGR U(0x564)
341#define RCC_LPDMACFGR U(0x568)
342#define RCC_HSEMCFGR U(0x56C)
343#define RCC_IPCC1CFGR U(0x570)
344#define RCC_IPCC2CFGR U(0x574)
345#define RCC_RTCCFGR U(0x578)
346#define RCC_SYSCPU1CFGR U(0x580)
347#define RCC_BSECCFGR U(0x584)
348#define RCC_IS2MCFGR U(0x58C)
349#define RCC_PLL2CFGR1 U(0x590)
350#define RCC_PLL2CFGR2 U(0x594)
351#define RCC_PLL2CFGR3 U(0x598)
352#define RCC_PLL2CFGR4 U(0x59C)
353#define RCC_PLL2CFGR5 U(0x5A0)
354#define RCC_PLL2CFGR6 U(0x5A8)
355#define RCC_PLL2CFGR7 U(0x5AC)
356#define RCC_PLL3CFGR1 U(0x5B8)
357#define RCC_PLL3CFGR2 U(0x5BC)
358#define RCC_PLL3CFGR3 U(0x5C0)
359#define RCC_PLL3CFGR4 U(0x5C4)
360#define RCC_PLL3CFGR5 U(0x5C8)
361#define RCC_PLL3CFGR6 U(0x5D0)
362#define RCC_PLL3CFGR7 U(0x5D4)
363#define RCC_HSIFMONCR U(0x5E0)
364#define RCC_HSIFVALR U(0x5E4)
365#define RCC_TIM1CFGR U(0x700)
366#define RCC_TIM2CFGR U(0x704)
367#define RCC_TIM3CFGR U(0x708)
368#define RCC_TIM4CFGR U(0x70C)
369#define RCC_TIM5CFGR U(0x710)
370#define RCC_TIM6CFGR U(0x714)
371#define RCC_TIM7CFGR U(0x718)
372#define RCC_TIM8CFGR U(0x71C)
373#define RCC_TIM10CFGR U(0x720)
374#define RCC_TIM11CFGR U(0x724)
375#define RCC_TIM12CFGR U(0x728)
376#define RCC_TIM13CFGR U(0x72C)
377#define RCC_TIM14CFGR U(0x730)
378#define RCC_TIM15CFGR U(0x734)
379#define RCC_TIM16CFGR U(0x738)
380#define RCC_TIM17CFGR U(0x73C)
381#define RCC_TIM20CFGR U(0x740)
382#define RCC_LPTIM1CFGR U(0x744)
383#define RCC_LPTIM2CFGR U(0x748)
384#define RCC_LPTIM3CFGR U(0x74C)
385#define RCC_LPTIM4CFGR U(0x750)
386#define RCC_LPTIM5CFGR U(0x754)
387#define RCC_SPI1CFGR U(0x758)
388#define RCC_SPI2CFGR U(0x75C)
389#define RCC_SPI3CFGR U(0x760)
390#define RCC_SPI4CFGR U(0x764)
391#define RCC_SPI5CFGR U(0x768)
392#define RCC_SPI6CFGR U(0x76C)
393#define RCC_SPI7CFGR U(0x770)
394#define RCC_SPI8CFGR U(0x774)
395#define RCC_SPDIFRXCFGR U(0x778)
396#define RCC_USART1CFGR U(0x77C)
397#define RCC_USART2CFGR U(0x780)
398#define RCC_USART3CFGR U(0x784)
399#define RCC_UART4CFGR U(0x788)
400#define RCC_UART5CFGR U(0x78C)
401#define RCC_USART6CFGR U(0x790)
402#define RCC_UART7CFGR U(0x794)
403#define RCC_UART8CFGR U(0x798)
404#define RCC_UART9CFGR U(0x79C)
405#define RCC_LPUART1CFGR U(0x7A0)
406#define RCC_I2C1CFGR U(0x7A4)
407#define RCC_I2C2CFGR U(0x7A8)
408#define RCC_I2C3CFGR U(0x7AC)
409#define RCC_I2C4CFGR U(0x7B0)
410#define RCC_I2C5CFGR U(0x7B4)
411#define RCC_I2C6CFGR U(0x7B8)
412#define RCC_I2C7CFGR U(0x7BC)
413#define RCC_I2C8CFGR U(0x7C0)
414#define RCC_SAI1CFGR U(0x7C4)
415#define RCC_SAI2CFGR U(0x7C8)
416#define RCC_SAI3CFGR U(0x7CC)
417#define RCC_SAI4CFGR U(0x7D0)
418#define RCC_MDF1CFGR U(0x7D8)
419#define RCC_ADF1CFGR U(0x7DC)
420#define RCC_FDCANCFGR U(0x7E0)
421#define RCC_HDPCFGR U(0x7E4)
422#define RCC_ADC12CFGR U(0x7E8)
423#define RCC_ADC3CFGR U(0x7EC)
424#define RCC_ETH1CFGR U(0x7F0)
425#define RCC_ETH2CFGR U(0x7F4)
426#define RCC_USB2CFGR U(0x7FC)
427#define RCC_USB2PHY1CFGR U(0x800)
428#define RCC_USB2PHY2CFGR U(0x804)
Gabriel Fernandezbcd95062022-04-20 10:08:49 +0200429#define RCC_USB3DRCFGR U(0x808)
Yann Gautier740ca302023-06-14 18:00:58 +0200430#define RCC_USB3PCIEPHYCFGR U(0x80C)
431#define RCC_PCIECFGR U(0x810)
432#define RCC_USBTCCFGR U(0x814)
433#define RCC_ETHSWCFGR U(0x818)
434#define RCC_ETHSWACMCFGR U(0x81C)
435#define RCC_ETHSWACMMSGCFGR U(0x820)
436#define RCC_STGENCFGR U(0x824)
437#define RCC_SDMMC1CFGR U(0x830)
438#define RCC_SDMMC2CFGR U(0x834)
439#define RCC_SDMMC3CFGR U(0x838)
440#define RCC_GPUCFGR U(0x83C)
441#define RCC_LTDCCFGR U(0x840)
442#define RCC_DSICFGR U(0x844)
443#define RCC_LVDSCFGR U(0x850)
444#define RCC_CSI2CFGR U(0x858)
445#define RCC_DCMIPPCFGR U(0x85C)
446#define RCC_CCICFGR U(0x860)
447#define RCC_VDECCFGR U(0x864)
448#define RCC_VENCCFGR U(0x868)
449#define RCC_RNGCFGR U(0x870)
450#define RCC_PKACFGR U(0x874)
451#define RCC_SAESCFGR U(0x878)
452#define RCC_HASHCFGR U(0x87C)
453#define RCC_CRYP1CFGR U(0x880)
454#define RCC_CRYP2CFGR U(0x884)
455#define RCC_IWDG1CFGR U(0x888)
456#define RCC_IWDG2CFGR U(0x88C)
457#define RCC_IWDG3CFGR U(0x890)
458#define RCC_IWDG4CFGR U(0x894)
459#define RCC_IWDG5CFGR U(0x898)
460#define RCC_WWDG1CFGR U(0x89C)
461#define RCC_WWDG2CFGR U(0x8A0)
Yann Gautier740ca302023-06-14 18:00:58 +0200462#define RCC_VREFCFGR U(0x8A8)
463#define RCC_TMPSENSCFGR U(0x8AC)
464#define RCC_CRCCFGR U(0x8B4)
465#define RCC_SERCCFGR U(0x8B8)
466#define RCC_OSPIIOMCFGR U(0x8BC)
467#define RCC_GICV2MCFGR U(0x8C0)
468#define RCC_I3C1CFGR U(0x8C8)
469#define RCC_I3C2CFGR U(0x8CC)
470#define RCC_I3C3CFGR U(0x8D0)
471#define RCC_I3C4CFGR U(0x8D4)
472#define RCC_MUXSELCFGR U(0x1000)
473#define RCC_XBAR0CFGR U(0x1018)
474#define RCC_XBAR1CFGR U(0x101C)
475#define RCC_XBAR2CFGR U(0x1020)
476#define RCC_XBAR3CFGR U(0x1024)
477#define RCC_XBAR4CFGR U(0x1028)
478#define RCC_XBAR5CFGR U(0x102C)
479#define RCC_XBAR6CFGR U(0x1030)
480#define RCC_XBAR7CFGR U(0x1034)
481#define RCC_XBAR8CFGR U(0x1038)
482#define RCC_XBAR9CFGR U(0x103C)
483#define RCC_XBAR10CFGR U(0x1040)
484#define RCC_XBAR11CFGR U(0x1044)
485#define RCC_XBAR12CFGR U(0x1048)
486#define RCC_XBAR13CFGR U(0x104C)
487#define RCC_XBAR14CFGR U(0x1050)
488#define RCC_XBAR15CFGR U(0x1054)
489#define RCC_XBAR16CFGR U(0x1058)
490#define RCC_XBAR17CFGR U(0x105C)
491#define RCC_XBAR18CFGR U(0x1060)
492#define RCC_XBAR19CFGR U(0x1064)
493#define RCC_XBAR20CFGR U(0x1068)
494#define RCC_XBAR21CFGR U(0x106C)
495#define RCC_XBAR22CFGR U(0x1070)
496#define RCC_XBAR23CFGR U(0x1074)
497#define RCC_XBAR24CFGR U(0x1078)
498#define RCC_XBAR25CFGR U(0x107C)
499#define RCC_XBAR26CFGR U(0x1080)
500#define RCC_XBAR27CFGR U(0x1084)
501#define RCC_XBAR28CFGR U(0x1088)
502#define RCC_XBAR29CFGR U(0x108C)
503#define RCC_XBAR30CFGR U(0x1090)
504#define RCC_XBAR31CFGR U(0x1094)
505#define RCC_XBAR32CFGR U(0x1098)
506#define RCC_XBAR33CFGR U(0x109C)
507#define RCC_XBAR34CFGR U(0x10A0)
508#define RCC_XBAR35CFGR U(0x10A4)
509#define RCC_XBAR36CFGR U(0x10A8)
510#define RCC_XBAR37CFGR U(0x10AC)
511#define RCC_XBAR38CFGR U(0x10B0)
512#define RCC_XBAR39CFGR U(0x10B4)
513#define RCC_XBAR40CFGR U(0x10B8)
514#define RCC_XBAR41CFGR U(0x10BC)
515#define RCC_XBAR42CFGR U(0x10C0)
516#define RCC_XBAR43CFGR U(0x10C4)
517#define RCC_XBAR44CFGR U(0x10C8)
518#define RCC_XBAR45CFGR U(0x10CC)
519#define RCC_XBAR46CFGR U(0x10D0)
520#define RCC_XBAR47CFGR U(0x10D4)
521#define RCC_XBAR48CFGR U(0x10D8)
522#define RCC_XBAR49CFGR U(0x10DC)
523#define RCC_XBAR50CFGR U(0x10E0)
524#define RCC_XBAR51CFGR U(0x10E4)
525#define RCC_XBAR52CFGR U(0x10E8)
526#define RCC_XBAR53CFGR U(0x10EC)
527#define RCC_XBAR54CFGR U(0x10F0)
528#define RCC_XBAR55CFGR U(0x10F4)
529#define RCC_XBAR56CFGR U(0x10F8)
530#define RCC_XBAR57CFGR U(0x10FC)
531#define RCC_XBAR58CFGR U(0x1100)
532#define RCC_XBAR59CFGR U(0x1104)
533#define RCC_XBAR60CFGR U(0x1108)
534#define RCC_XBAR61CFGR U(0x110C)
535#define RCC_XBAR62CFGR U(0x1110)
536#define RCC_XBAR63CFGR U(0x1114)
537#define RCC_PREDIV0CFGR U(0x1118)
538#define RCC_PREDIV1CFGR U(0x111C)
539#define RCC_PREDIV2CFGR U(0x1120)
540#define RCC_PREDIV3CFGR U(0x1124)
541#define RCC_PREDIV4CFGR U(0x1128)
542#define RCC_PREDIV5CFGR U(0x112C)
543#define RCC_PREDIV6CFGR U(0x1130)
544#define RCC_PREDIV7CFGR U(0x1134)
545#define RCC_PREDIV8CFGR U(0x1138)
546#define RCC_PREDIV9CFGR U(0x113C)
547#define RCC_PREDIV10CFGR U(0x1140)
548#define RCC_PREDIV11CFGR U(0x1144)
549#define RCC_PREDIV12CFGR U(0x1148)
550#define RCC_PREDIV13CFGR U(0x114C)
551#define RCC_PREDIV14CFGR U(0x1150)
552#define RCC_PREDIV15CFGR U(0x1154)
553#define RCC_PREDIV16CFGR U(0x1158)
554#define RCC_PREDIV17CFGR U(0x115C)
555#define RCC_PREDIV18CFGR U(0x1160)
556#define RCC_PREDIV19CFGR U(0x1164)
557#define RCC_PREDIV20CFGR U(0x1168)
558#define RCC_PREDIV21CFGR U(0x116C)
559#define RCC_PREDIV22CFGR U(0x1170)
560#define RCC_PREDIV23CFGR U(0x1174)
561#define RCC_PREDIV24CFGR U(0x1178)
562#define RCC_PREDIV25CFGR U(0x117C)
563#define RCC_PREDIV26CFGR U(0x1180)
564#define RCC_PREDIV27CFGR U(0x1184)
565#define RCC_PREDIV28CFGR U(0x1188)
566#define RCC_PREDIV29CFGR U(0x118C)
567#define RCC_PREDIV30CFGR U(0x1190)
568#define RCC_PREDIV31CFGR U(0x1194)
569#define RCC_PREDIV32CFGR U(0x1198)
570#define RCC_PREDIV33CFGR U(0x119C)
571#define RCC_PREDIV34CFGR U(0x11A0)
572#define RCC_PREDIV35CFGR U(0x11A4)
573#define RCC_PREDIV36CFGR U(0x11A8)
574#define RCC_PREDIV37CFGR U(0x11AC)
575#define RCC_PREDIV38CFGR U(0x11B0)
576#define RCC_PREDIV39CFGR U(0x11B4)
577#define RCC_PREDIV40CFGR U(0x11B8)
578#define RCC_PREDIV41CFGR U(0x11BC)
579#define RCC_PREDIV42CFGR U(0x11C0)
580#define RCC_PREDIV43CFGR U(0x11C4)
581#define RCC_PREDIV44CFGR U(0x11C8)
582#define RCC_PREDIV45CFGR U(0x11CC)
583#define RCC_PREDIV46CFGR U(0x11D0)
584#define RCC_PREDIV47CFGR U(0x11D4)
585#define RCC_PREDIV48CFGR U(0x11D8)
586#define RCC_PREDIV49CFGR U(0x11DC)
587#define RCC_PREDIV50CFGR U(0x11E0)
588#define RCC_PREDIV51CFGR U(0x11E4)
589#define RCC_PREDIV52CFGR U(0x11E8)
590#define RCC_PREDIV53CFGR U(0x11EC)
591#define RCC_PREDIV54CFGR U(0x11F0)
592#define RCC_PREDIV55CFGR U(0x11F4)
593#define RCC_PREDIV56CFGR U(0x11F8)
594#define RCC_PREDIV57CFGR U(0x11FC)
595#define RCC_PREDIV58CFGR U(0x1200)
596#define RCC_PREDIV59CFGR U(0x1204)
597#define RCC_PREDIV60CFGR U(0x1208)
598#define RCC_PREDIV61CFGR U(0x120C)
599#define RCC_PREDIV62CFGR U(0x1210)
600#define RCC_PREDIV63CFGR U(0x1214)
601#define RCC_PREDIVSR1 U(0x1218)
602#define RCC_PREDIVSR2 U(0x121C)
603#define RCC_FINDIV0CFGR U(0x1224)
604#define RCC_FINDIV1CFGR U(0x1228)
605#define RCC_FINDIV2CFGR U(0x122C)
606#define RCC_FINDIV3CFGR U(0x1230)
607#define RCC_FINDIV4CFGR U(0x1234)
608#define RCC_FINDIV5CFGR U(0x1238)
609#define RCC_FINDIV6CFGR U(0x123C)
610#define RCC_FINDIV7CFGR U(0x1240)
611#define RCC_FINDIV8CFGR U(0x1244)
612#define RCC_FINDIV9CFGR U(0x1248)
613#define RCC_FINDIV10CFGR U(0x124C)
614#define RCC_FINDIV11CFGR U(0x1250)
615#define RCC_FINDIV12CFGR U(0x1254)
616#define RCC_FINDIV13CFGR U(0x1258)
617#define RCC_FINDIV14CFGR U(0x125C)
618#define RCC_FINDIV15CFGR U(0x1260)
619#define RCC_FINDIV16CFGR U(0x1264)
620#define RCC_FINDIV17CFGR U(0x1268)
621#define RCC_FINDIV18CFGR U(0x126C)
622#define RCC_FINDIV19CFGR U(0x1270)
623#define RCC_FINDIV20CFGR U(0x1274)
624#define RCC_FINDIV21CFGR U(0x1278)
625#define RCC_FINDIV22CFGR U(0x127C)
626#define RCC_FINDIV23CFGR U(0x1280)
627#define RCC_FINDIV24CFGR U(0x1284)
628#define RCC_FINDIV25CFGR U(0x1288)
629#define RCC_FINDIV26CFGR U(0x128C)
630#define RCC_FINDIV27CFGR U(0x1290)
631#define RCC_FINDIV28CFGR U(0x1294)
632#define RCC_FINDIV29CFGR U(0x1298)
633#define RCC_FINDIV30CFGR U(0x129C)
634#define RCC_FINDIV31CFGR U(0x12A0)
635#define RCC_FINDIV32CFGR U(0x12A4)
636#define RCC_FINDIV33CFGR U(0x12A8)
637#define RCC_FINDIV34CFGR U(0x12AC)
638#define RCC_FINDIV35CFGR U(0x12B0)
639#define RCC_FINDIV36CFGR U(0x12B4)
640#define RCC_FINDIV37CFGR U(0x12B8)
641#define RCC_FINDIV38CFGR U(0x12BC)
642#define RCC_FINDIV39CFGR U(0x12C0)
643#define RCC_FINDIV40CFGR U(0x12C4)
644#define RCC_FINDIV41CFGR U(0x12C8)
645#define RCC_FINDIV42CFGR U(0x12CC)
646#define RCC_FINDIV43CFGR U(0x12D0)
647#define RCC_FINDIV44CFGR U(0x12D4)
648#define RCC_FINDIV45CFGR U(0x12D8)
649#define RCC_FINDIV46CFGR U(0x12DC)
650#define RCC_FINDIV47CFGR U(0x12E0)
651#define RCC_FINDIV48CFGR U(0x12E4)
652#define RCC_FINDIV49CFGR U(0x12E8)
653#define RCC_FINDIV50CFGR U(0x12EC)
654#define RCC_FINDIV51CFGR U(0x12F0)
655#define RCC_FINDIV52CFGR U(0x12F4)
656#define RCC_FINDIV53CFGR U(0x12F8)
657#define RCC_FINDIV54CFGR U(0x12FC)
658#define RCC_FINDIV55CFGR U(0x1300)
659#define RCC_FINDIV56CFGR U(0x1304)
660#define RCC_FINDIV57CFGR U(0x1308)
661#define RCC_FINDIV58CFGR U(0x130C)
662#define RCC_FINDIV59CFGR U(0x1310)
663#define RCC_FINDIV60CFGR U(0x1314)
664#define RCC_FINDIV61CFGR U(0x1318)
665#define RCC_FINDIV62CFGR U(0x131C)
666#define RCC_FINDIV63CFGR U(0x1320)
667#define RCC_FINDIVSR1 U(0x1324)
668#define RCC_FINDIVSR2 U(0x1328)
669#define RCC_FCALCOBS0CFGR U(0x1340)
670#define RCC_FCALCOBS1CFGR U(0x1344)
671#define RCC_FCALCREFCFGR U(0x1348)
672#define RCC_FCALCCR1 U(0x134C)
673#define RCC_FCALCCR2 U(0x1354)
674#define RCC_FCALCSR U(0x1358)
675#define RCC_PLL4CFGR1 U(0x1360)
676#define RCC_PLL4CFGR2 U(0x1364)
677#define RCC_PLL4CFGR3 U(0x1368)
678#define RCC_PLL4CFGR4 U(0x136C)
679#define RCC_PLL4CFGR5 U(0x1370)
680#define RCC_PLL4CFGR6 U(0x1378)
681#define RCC_PLL4CFGR7 U(0x137C)
682#define RCC_PLL5CFGR1 U(0x1388)
683#define RCC_PLL5CFGR2 U(0x138C)
684#define RCC_PLL5CFGR3 U(0x1390)
685#define RCC_PLL5CFGR4 U(0x1394)
686#define RCC_PLL5CFGR5 U(0x1398)
687#define RCC_PLL5CFGR6 U(0x13A0)
688#define RCC_PLL5CFGR7 U(0x13A4)
689#define RCC_PLL6CFGR1 U(0x13B0)
690#define RCC_PLL6CFGR2 U(0x13B4)
691#define RCC_PLL6CFGR3 U(0x13B8)
692#define RCC_PLL6CFGR4 U(0x13BC)
693#define RCC_PLL6CFGR5 U(0x13C0)
694#define RCC_PLL6CFGR6 U(0x13C8)
695#define RCC_PLL6CFGR7 U(0x13CC)
696#define RCC_PLL7CFGR1 U(0x13D8)
697#define RCC_PLL7CFGR2 U(0x13DC)
698#define RCC_PLL7CFGR3 U(0x13E0)
699#define RCC_PLL7CFGR4 U(0x13E4)
700#define RCC_PLL7CFGR5 U(0x13E8)
701#define RCC_PLL7CFGR6 U(0x13F0)
702#define RCC_PLL7CFGR7 U(0x13F4)
703#define RCC_PLL8CFGR1 U(0x1400)
704#define RCC_PLL8CFGR2 U(0x1404)
705#define RCC_PLL8CFGR3 U(0x1408)
706#define RCC_PLL8CFGR4 U(0x140C)
707#define RCC_PLL8CFGR5 U(0x1410)
708#define RCC_PLL8CFGR6 U(0x1418)
709#define RCC_PLL8CFGR7 U(0x141C)
710#define RCC_VERR U(0xFFF4)
711#define RCC_IDR U(0xFFF8)
712#define RCC_SIDR U(0xFFFC)
713
714/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
715#define RCC_MP_ENCLRR_OFFSET U(4)
716
717/* RCC_SECCFGR3 register fields */
718#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0)
719#define RCC_SECCFGR3_SEC_SHIFT 0
720
721/* RCC_PRIVCFGR3 register fields */
722#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0)
723#define RCC_PRIVCFGR3_PRIV_SHIFT 0
724
725/* RCC_RCFGLOCKR3 register fields */
726#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0)
727#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0
728
729/* RCC_R0CIDCFGR register fields */
730#define RCC_R0CIDCFGR_CFEN BIT(0)
731#define RCC_R0CIDCFGR_SEM_EN BIT(1)
732#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
733#define RCC_R0CIDCFGR_SCID_SHIFT 4
734#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
735#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16
736
737/* RCC_R0SEMCR register fields */
738#define RCC_R0SEMCR_SEM_MUTEX BIT(0)
739#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4)
740#define RCC_R0SEMCR_SEMCID_SHIFT 4
741
742/* RCC_R1CIDCFGR register fields */
743#define RCC_R1CIDCFGR_CFEN BIT(0)
744#define RCC_R1CIDCFGR_SEM_EN BIT(1)
745#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
746#define RCC_R1CIDCFGR_SCID_SHIFT 4
747#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
748#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16
749
750/* RCC_R1SEMCR register fields */
751#define RCC_R1SEMCR_SEM_MUTEX BIT(0)
752#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
753#define RCC_R1SEMCR_SEMCID_SHIFT 4
754
755/* RCC_R2CIDCFGR register fields */
756#define RCC_R2CIDCFGR_CFEN BIT(0)
757#define RCC_R2CIDCFGR_SEM_EN BIT(1)
758#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
759#define RCC_R2CIDCFGR_SCID_SHIFT 4
760#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
761#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16
762
763/* RCC_R2SEMCR register fields */
764#define RCC_R2SEMCR_SEM_MUTEX BIT(0)
765#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
766#define RCC_R2SEMCR_SEMCID_SHIFT 4
767
768/* RCC_R3CIDCFGR register fields */
769#define RCC_R3CIDCFGR_CFEN BIT(0)
770#define RCC_R3CIDCFGR_SEM_EN BIT(1)
771#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
772#define RCC_R3CIDCFGR_SCID_SHIFT 4
773#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
774#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16
775
776/* RCC_R3SEMCR register fields */
777#define RCC_R3SEMCR_SEM_MUTEX BIT(0)
778#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
779#define RCC_R3SEMCR_SEMCID_SHIFT 4
780
781/* RCC_R4CIDCFGR register fields */
782#define RCC_R4CIDCFGR_CFEN BIT(0)
783#define RCC_R4CIDCFGR_SEM_EN BIT(1)
784#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
785#define RCC_R4CIDCFGR_SCID_SHIFT 4
786#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
787#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16
788
789/* RCC_R4SEMCR register fields */
790#define RCC_R4SEMCR_SEM_MUTEX BIT(0)
791#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
792#define RCC_R4SEMCR_SEMCID_SHIFT 4
793
794/* RCC_R5CIDCFGR register fields */
795#define RCC_R5CIDCFGR_CFEN BIT(0)
796#define RCC_R5CIDCFGR_SEM_EN BIT(1)
797#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
798#define RCC_R5CIDCFGR_SCID_SHIFT 4
799#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
800#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16
801
802/* RCC_R5SEMCR register fields */
803#define RCC_R5SEMCR_SEM_MUTEX BIT(0)
804#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
805#define RCC_R5SEMCR_SEMCID_SHIFT 4
806
807/* RCC_R6CIDCFGR register fields */
808#define RCC_R6CIDCFGR_CFEN BIT(0)
809#define RCC_R6CIDCFGR_SEM_EN BIT(1)
810#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
811#define RCC_R6CIDCFGR_SCID_SHIFT 4
812#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
813#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16
814
815/* RCC_R6SEMCR register fields */
816#define RCC_R6SEMCR_SEM_MUTEX BIT(0)
817#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
818#define RCC_R6SEMCR_SEMCID_SHIFT 4
819
820/* RCC_R7CIDCFGR register fields */
821#define RCC_R7CIDCFGR_CFEN BIT(0)
822#define RCC_R7CIDCFGR_SEM_EN BIT(1)
823#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4)
824#define RCC_R7CIDCFGR_SCID_SHIFT 4
825#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
826#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16
827
828/* RCC_R7SEMCR register fields */
829#define RCC_R7SEMCR_SEM_MUTEX BIT(0)
830#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4)
831#define RCC_R7SEMCR_SEMCID_SHIFT 4
832
833/* RCC_R8CIDCFGR register fields */
834#define RCC_R8CIDCFGR_CFEN BIT(0)
835#define RCC_R8CIDCFGR_SEM_EN BIT(1)
836#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4)
837#define RCC_R8CIDCFGR_SCID_SHIFT 4
838#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
839#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16
840
841/* RCC_R8SEMCR register fields */
842#define RCC_R8SEMCR_SEM_MUTEX BIT(0)
843#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4)
844#define RCC_R8SEMCR_SEMCID_SHIFT 4
845
846/* RCC_R9CIDCFGR register fields */
847#define RCC_R9CIDCFGR_CFEN BIT(0)
848#define RCC_R9CIDCFGR_SEM_EN BIT(1)
849#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4)
850#define RCC_R9CIDCFGR_SCID_SHIFT 4
851#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
852#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16
853
854/* RCC_R9SEMCR register fields */
855#define RCC_R9SEMCR_SEM_MUTEX BIT(0)
856#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4)
857#define RCC_R9SEMCR_SEMCID_SHIFT 4
858
859/* RCC_R10CIDCFGR register fields */
860#define RCC_R10CIDCFGR_CFEN BIT(0)
861#define RCC_R10CIDCFGR_SEM_EN BIT(1)
862#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4)
863#define RCC_R10CIDCFGR_SCID_SHIFT 4
864#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
865#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16
866
867/* RCC_R10SEMCR register fields */
868#define RCC_R10SEMCR_SEM_MUTEX BIT(0)
869#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4)
870#define RCC_R10SEMCR_SEMCID_SHIFT 4
871
872/* RCC_R11CIDCFGR register fields */
873#define RCC_R11CIDCFGR_CFEN BIT(0)
874#define RCC_R11CIDCFGR_SEM_EN BIT(1)
875#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4)
876#define RCC_R11CIDCFGR_SCID_SHIFT 4
877#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
878#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16
879
880/* RCC_R11SEMCR register fields */
881#define RCC_R11SEMCR_SEM_MUTEX BIT(0)
882#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4)
883#define RCC_R11SEMCR_SEMCID_SHIFT 4
884
885/* RCC_R12CIDCFGR register fields */
886#define RCC_R12CIDCFGR_CFEN BIT(0)
887#define RCC_R12CIDCFGR_SEM_EN BIT(1)
888#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4)
889#define RCC_R12CIDCFGR_SCID_SHIFT 4
890#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
891#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16
892
893/* RCC_R12SEMCR register fields */
894#define RCC_R12SEMCR_SEM_MUTEX BIT(0)
895#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4)
896#define RCC_R12SEMCR_SEMCID_SHIFT 4
897
898/* RCC_R13CIDCFGR register fields */
899#define RCC_R13CIDCFGR_CFEN BIT(0)
900#define RCC_R13CIDCFGR_SEM_EN BIT(1)
901#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4)
902#define RCC_R13CIDCFGR_SCID_SHIFT 4
903#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
904#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16
905
906/* RCC_R13SEMCR register fields */
907#define RCC_R13SEMCR_SEM_MUTEX BIT(0)
908#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4)
909#define RCC_R13SEMCR_SEMCID_SHIFT 4
910
911/* RCC_R14CIDCFGR register fields */
912#define RCC_R14CIDCFGR_CFEN BIT(0)
913#define RCC_R14CIDCFGR_SEM_EN BIT(1)
914#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4)
915#define RCC_R14CIDCFGR_SCID_SHIFT 4
916#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
917#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16
918
919/* RCC_R14SEMCR register fields */
920#define RCC_R14SEMCR_SEM_MUTEX BIT(0)
921#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4)
922#define RCC_R14SEMCR_SEMCID_SHIFT 4
923
924/* RCC_R15CIDCFGR register fields */
925#define RCC_R15CIDCFGR_CFEN BIT(0)
926#define RCC_R15CIDCFGR_SEM_EN BIT(1)
927#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4)
928#define RCC_R15CIDCFGR_SCID_SHIFT 4
929#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
930#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16
931
932/* RCC_R15SEMCR register fields */
933#define RCC_R15SEMCR_SEM_MUTEX BIT(0)
934#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4)
935#define RCC_R15SEMCR_SEMCID_SHIFT 4
936
937/* RCC_R16CIDCFGR register fields */
938#define RCC_R16CIDCFGR_CFEN BIT(0)
939#define RCC_R16CIDCFGR_SEM_EN BIT(1)
940#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4)
941#define RCC_R16CIDCFGR_SCID_SHIFT 4
942#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
943#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16
944
945/* RCC_R16SEMCR register fields */
946#define RCC_R16SEMCR_SEM_MUTEX BIT(0)
947#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4)
948#define RCC_R16SEMCR_SEMCID_SHIFT 4
949
950/* RCC_R17CIDCFGR register fields */
951#define RCC_R17CIDCFGR_CFEN BIT(0)
952#define RCC_R17CIDCFGR_SEM_EN BIT(1)
953#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4)
954#define RCC_R17CIDCFGR_SCID_SHIFT 4
955#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
956#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16
957
958/* RCC_R17SEMCR register fields */
959#define RCC_R17SEMCR_SEM_MUTEX BIT(0)
960#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4)
961#define RCC_R17SEMCR_SEMCID_SHIFT 4
962
963/* RCC_R18CIDCFGR register fields */
964#define RCC_R18CIDCFGR_CFEN BIT(0)
965#define RCC_R18CIDCFGR_SEM_EN BIT(1)
966#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4)
967#define RCC_R18CIDCFGR_SCID_SHIFT 4
968#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
969#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16
970
971/* RCC_R18SEMCR register fields */
972#define RCC_R18SEMCR_SEM_MUTEX BIT(0)
973#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4)
974#define RCC_R18SEMCR_SEMCID_SHIFT 4
975
976/* RCC_R19CIDCFGR register fields */
977#define RCC_R19CIDCFGR_CFEN BIT(0)
978#define RCC_R19CIDCFGR_SEM_EN BIT(1)
979#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4)
980#define RCC_R19CIDCFGR_SCID_SHIFT 4
981#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
982#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16
983
984/* RCC_R19SEMCR register fields */
985#define RCC_R19SEMCR_SEM_MUTEX BIT(0)
986#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4)
987#define RCC_R19SEMCR_SEMCID_SHIFT 4
988
989/* RCC_R20CIDCFGR register fields */
990#define RCC_R20CIDCFGR_CFEN BIT(0)
991#define RCC_R20CIDCFGR_SEM_EN BIT(1)
992#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4)
993#define RCC_R20CIDCFGR_SCID_SHIFT 4
994#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
995#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16
996
997/* RCC_R20SEMCR register fields */
998#define RCC_R20SEMCR_SEM_MUTEX BIT(0)
999#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1000#define RCC_R20SEMCR_SEMCID_SHIFT 4
1001
1002/* RCC_R21CIDCFGR register fields */
1003#define RCC_R21CIDCFGR_CFEN BIT(0)
1004#define RCC_R21CIDCFGR_SEM_EN BIT(1)
1005#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1006#define RCC_R21CIDCFGR_SCID_SHIFT 4
1007#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1008#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16
1009
1010/* RCC_R21SEMCR register fields */
1011#define RCC_R21SEMCR_SEM_MUTEX BIT(0)
1012#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1013#define RCC_R21SEMCR_SEMCID_SHIFT 4
1014
1015/* RCC_R22CIDCFGR register fields */
1016#define RCC_R22CIDCFGR_CFEN BIT(0)
1017#define RCC_R22CIDCFGR_SEM_EN BIT(1)
1018#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1019#define RCC_R22CIDCFGR_SCID_SHIFT 4
1020#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1021#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16
1022
1023/* RCC_R22SEMCR register fields */
1024#define RCC_R22SEMCR_SEM_MUTEX BIT(0)
1025#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1026#define RCC_R22SEMCR_SEMCID_SHIFT 4
1027
1028/* RCC_R23CIDCFGR register fields */
1029#define RCC_R23CIDCFGR_CFEN BIT(0)
1030#define RCC_R23CIDCFGR_SEM_EN BIT(1)
1031#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1032#define RCC_R23CIDCFGR_SCID_SHIFT 4
1033#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1034#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16
1035
1036/* RCC_R23SEMCR register fields */
1037#define RCC_R23SEMCR_SEM_MUTEX BIT(0)
1038#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1039#define RCC_R23SEMCR_SEMCID_SHIFT 4
1040
1041/* RCC_R24CIDCFGR register fields */
1042#define RCC_R24CIDCFGR_CFEN BIT(0)
1043#define RCC_R24CIDCFGR_SEM_EN BIT(1)
1044#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1045#define RCC_R24CIDCFGR_SCID_SHIFT 4
1046#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1047#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16
1048
1049/* RCC_R24SEMCR register fields */
1050#define RCC_R24SEMCR_SEM_MUTEX BIT(0)
1051#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1052#define RCC_R24SEMCR_SEMCID_SHIFT 4
1053
1054/* RCC_R25CIDCFGR register fields */
1055#define RCC_R25CIDCFGR_CFEN BIT(0)
1056#define RCC_R25CIDCFGR_SEM_EN BIT(1)
1057#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1058#define RCC_R25CIDCFGR_SCID_SHIFT 4
1059#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1060#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16
1061
1062/* RCC_R25SEMCR register fields */
1063#define RCC_R25SEMCR_SEM_MUTEX BIT(0)
1064#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1065#define RCC_R25SEMCR_SEMCID_SHIFT 4
1066
1067/* RCC_R26CIDCFGR register fields */
1068#define RCC_R26CIDCFGR_CFEN BIT(0)
1069#define RCC_R26CIDCFGR_SEM_EN BIT(1)
1070#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1071#define RCC_R26CIDCFGR_SCID_SHIFT 4
1072#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1073#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16
1074
1075/* RCC_R26SEMCR register fields */
1076#define RCC_R26SEMCR_SEM_MUTEX BIT(0)
1077#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1078#define RCC_R26SEMCR_SEMCID_SHIFT 4
1079
1080/* RCC_R27CIDCFGR register fields */
1081#define RCC_R27CIDCFGR_CFEN BIT(0)
1082#define RCC_R27CIDCFGR_SEM_EN BIT(1)
1083#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1084#define RCC_R27CIDCFGR_SCID_SHIFT 4
1085#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1086#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16
1087
1088/* RCC_R27SEMCR register fields */
1089#define RCC_R27SEMCR_SEM_MUTEX BIT(0)
1090#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1091#define RCC_R27SEMCR_SEMCID_SHIFT 4
1092
1093/* RCC_R28CIDCFGR register fields */
1094#define RCC_R28CIDCFGR_CFEN BIT(0)
1095#define RCC_R28CIDCFGR_SEM_EN BIT(1)
1096#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1097#define RCC_R28CIDCFGR_SCID_SHIFT 4
1098#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1099#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16
1100
1101/* RCC_R28SEMCR register fields */
1102#define RCC_R28SEMCR_SEM_MUTEX BIT(0)
1103#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1104#define RCC_R28SEMCR_SEMCID_SHIFT 4
1105
1106/* RCC_R29CIDCFGR register fields */
1107#define RCC_R29CIDCFGR_CFEN BIT(0)
1108#define RCC_R29CIDCFGR_SEM_EN BIT(1)
1109#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1110#define RCC_R29CIDCFGR_SCID_SHIFT 4
1111#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1112#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16
1113
1114/* RCC_R29SEMCR register fields */
1115#define RCC_R29SEMCR_SEM_MUTEX BIT(0)
1116#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1117#define RCC_R29SEMCR_SEMCID_SHIFT 4
1118
1119/* RCC_R30CIDCFGR register fields */
1120#define RCC_R30CIDCFGR_CFEN BIT(0)
1121#define RCC_R30CIDCFGR_SEM_EN BIT(1)
1122#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1123#define RCC_R30CIDCFGR_SCID_SHIFT 4
1124#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1125#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16
1126
1127/* RCC_R30SEMCR register fields */
1128#define RCC_R30SEMCR_SEM_MUTEX BIT(0)
1129#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1130#define RCC_R30SEMCR_SEMCID_SHIFT 4
1131
1132/* RCC_R31CIDCFGR register fields */
1133#define RCC_R31CIDCFGR_CFEN BIT(0)
1134#define RCC_R31CIDCFGR_SEM_EN BIT(1)
1135#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1136#define RCC_R31CIDCFGR_SCID_SHIFT 4
1137#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1138#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16
1139
1140/* RCC_R31SEMCR register fields */
1141#define RCC_R31SEMCR_SEM_MUTEX BIT(0)
1142#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1143#define RCC_R31SEMCR_SEMCID_SHIFT 4
1144
1145/* RCC_R32CIDCFGR register fields */
1146#define RCC_R32CIDCFGR_CFEN BIT(0)
1147#define RCC_R32CIDCFGR_SEM_EN BIT(1)
1148#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1149#define RCC_R32CIDCFGR_SCID_SHIFT 4
1150#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1151#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16
1152
1153/* RCC_R32SEMCR register fields */
1154#define RCC_R32SEMCR_SEM_MUTEX BIT(0)
1155#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1156#define RCC_R32SEMCR_SEMCID_SHIFT 4
1157
1158/* RCC_R33CIDCFGR register fields */
1159#define RCC_R33CIDCFGR_CFEN BIT(0)
1160#define RCC_R33CIDCFGR_SEM_EN BIT(1)
1161#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1162#define RCC_R33CIDCFGR_SCID_SHIFT 4
1163#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1164#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16
1165
1166/* RCC_R33SEMCR register fields */
1167#define RCC_R33SEMCR_SEM_MUTEX BIT(0)
1168#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1169#define RCC_R33SEMCR_SEMCID_SHIFT 4
1170
1171/* RCC_R34CIDCFGR register fields */
1172#define RCC_R34CIDCFGR_CFEN BIT(0)
1173#define RCC_R34CIDCFGR_SEM_EN BIT(1)
1174#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1175#define RCC_R34CIDCFGR_SCID_SHIFT 4
1176#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1177#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16
1178
1179/* RCC_R34SEMCR register fields */
1180#define RCC_R34SEMCR_SEM_MUTEX BIT(0)
1181#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1182#define RCC_R34SEMCR_SEMCID_SHIFT 4
1183
1184/* RCC_R35CIDCFGR register fields */
1185#define RCC_R35CIDCFGR_CFEN BIT(0)
1186#define RCC_R35CIDCFGR_SEM_EN BIT(1)
1187#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1188#define RCC_R35CIDCFGR_SCID_SHIFT 4
1189#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1190#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16
1191
1192/* RCC_R35SEMCR register fields */
1193#define RCC_R35SEMCR_SEM_MUTEX BIT(0)
1194#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1195#define RCC_R35SEMCR_SEMCID_SHIFT 4
1196
1197/* RCC_R36CIDCFGR register fields */
1198#define RCC_R36CIDCFGR_CFEN BIT(0)
1199#define RCC_R36CIDCFGR_SEM_EN BIT(1)
1200#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1201#define RCC_R36CIDCFGR_SCID_SHIFT 4
1202#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1203#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16
1204
1205/* RCC_R36SEMCR register fields */
1206#define RCC_R36SEMCR_SEM_MUTEX BIT(0)
1207#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1208#define RCC_R36SEMCR_SEMCID_SHIFT 4
1209
1210/* RCC_R37CIDCFGR register fields */
1211#define RCC_R37CIDCFGR_CFEN BIT(0)
1212#define RCC_R37CIDCFGR_SEM_EN BIT(1)
1213#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1214#define RCC_R37CIDCFGR_SCID_SHIFT 4
1215#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1216#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16
1217
1218/* RCC_R37SEMCR register fields */
1219#define RCC_R37SEMCR_SEM_MUTEX BIT(0)
1220#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1221#define RCC_R37SEMCR_SEMCID_SHIFT 4
1222
1223/* RCC_R38CIDCFGR register fields */
1224#define RCC_R38CIDCFGR_CFEN BIT(0)
1225#define RCC_R38CIDCFGR_SEM_EN BIT(1)
1226#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1227#define RCC_R38CIDCFGR_SCID_SHIFT 4
1228#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1229#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16
1230
1231/* RCC_R38SEMCR register fields */
1232#define RCC_R38SEMCR_SEM_MUTEX BIT(0)
1233#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1234#define RCC_R38SEMCR_SEMCID_SHIFT 4
1235
1236/* RCC_R39CIDCFGR register fields */
1237#define RCC_R39CIDCFGR_CFEN BIT(0)
1238#define RCC_R39CIDCFGR_SEM_EN BIT(1)
1239#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1240#define RCC_R39CIDCFGR_SCID_SHIFT 4
1241#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1242#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16
1243
1244/* RCC_R39SEMCR register fields */
1245#define RCC_R39SEMCR_SEM_MUTEX BIT(0)
1246#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1247#define RCC_R39SEMCR_SEMCID_SHIFT 4
1248
1249/* RCC_R40CIDCFGR register fields */
1250#define RCC_R40CIDCFGR_CFEN BIT(0)
1251#define RCC_R40CIDCFGR_SEM_EN BIT(1)
1252#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1253#define RCC_R40CIDCFGR_SCID_SHIFT 4
1254#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1255#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16
1256
1257/* RCC_R40SEMCR register fields */
1258#define RCC_R40SEMCR_SEM_MUTEX BIT(0)
1259#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1260#define RCC_R40SEMCR_SEMCID_SHIFT 4
1261
1262/* RCC_R41CIDCFGR register fields */
1263#define RCC_R41CIDCFGR_CFEN BIT(0)
1264#define RCC_R41CIDCFGR_SEM_EN BIT(1)
1265#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1266#define RCC_R41CIDCFGR_SCID_SHIFT 4
1267#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1268#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16
1269
1270/* RCC_R41SEMCR register fields */
1271#define RCC_R41SEMCR_SEM_MUTEX BIT(0)
1272#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1273#define RCC_R41SEMCR_SEMCID_SHIFT 4
1274
1275/* RCC_R42CIDCFGR register fields */
1276#define RCC_R42CIDCFGR_CFEN BIT(0)
1277#define RCC_R42CIDCFGR_SEM_EN BIT(1)
1278#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1279#define RCC_R42CIDCFGR_SCID_SHIFT 4
1280#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1281#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16
1282
1283/* RCC_R42SEMCR register fields */
1284#define RCC_R42SEMCR_SEM_MUTEX BIT(0)
1285#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1286#define RCC_R42SEMCR_SEMCID_SHIFT 4
1287
1288/* RCC_R43CIDCFGR register fields */
1289#define RCC_R43CIDCFGR_CFEN BIT(0)
1290#define RCC_R43CIDCFGR_SEM_EN BIT(1)
1291#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1292#define RCC_R43CIDCFGR_SCID_SHIFT 4
1293#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1294#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16
1295
1296/* RCC_R43SEMCR register fields */
1297#define RCC_R43SEMCR_SEM_MUTEX BIT(0)
1298#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1299#define RCC_R43SEMCR_SEMCID_SHIFT 4
1300
1301/* RCC_R44CIDCFGR register fields */
1302#define RCC_R44CIDCFGR_CFEN BIT(0)
1303#define RCC_R44CIDCFGR_SEM_EN BIT(1)
1304#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1305#define RCC_R44CIDCFGR_SCID_SHIFT 4
1306#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1307#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16
1308
1309/* RCC_R44SEMCR register fields */
1310#define RCC_R44SEMCR_SEM_MUTEX BIT(0)
1311#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1312#define RCC_R44SEMCR_SEMCID_SHIFT 4
1313
1314/* RCC_R45CIDCFGR register fields */
1315#define RCC_R45CIDCFGR_CFEN BIT(0)
1316#define RCC_R45CIDCFGR_SEM_EN BIT(1)
1317#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1318#define RCC_R45CIDCFGR_SCID_SHIFT 4
1319#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1320#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16
1321
1322/* RCC_R45SEMCR register fields */
1323#define RCC_R45SEMCR_SEM_MUTEX BIT(0)
1324#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1325#define RCC_R45SEMCR_SEMCID_SHIFT 4
1326
1327/* RCC_R46CIDCFGR register fields */
1328#define RCC_R46CIDCFGR_CFEN BIT(0)
1329#define RCC_R46CIDCFGR_SEM_EN BIT(1)
1330#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1331#define RCC_R46CIDCFGR_SCID_SHIFT 4
1332#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1333#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16
1334
1335/* RCC_R46SEMCR register fields */
1336#define RCC_R46SEMCR_SEM_MUTEX BIT(0)
1337#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1338#define RCC_R46SEMCR_SEMCID_SHIFT 4
1339
1340/* RCC_R47CIDCFGR register fields */
1341#define RCC_R47CIDCFGR_CFEN BIT(0)
1342#define RCC_R47CIDCFGR_SEM_EN BIT(1)
1343#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1344#define RCC_R47CIDCFGR_SCID_SHIFT 4
1345#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1346#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16
1347
1348/* RCC_R47SEMCR register fields */
1349#define RCC_R47SEMCR_SEM_MUTEX BIT(0)
1350#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1351#define RCC_R47SEMCR_SEMCID_SHIFT 4
1352
1353/* RCC_R48CIDCFGR register fields */
1354#define RCC_R48CIDCFGR_CFEN BIT(0)
1355#define RCC_R48CIDCFGR_SEM_EN BIT(1)
1356#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1357#define RCC_R48CIDCFGR_SCID_SHIFT 4
1358#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1359#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16
1360
1361/* RCC_R48SEMCR register fields */
1362#define RCC_R48SEMCR_SEM_MUTEX BIT(0)
1363#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1364#define RCC_R48SEMCR_SEMCID_SHIFT 4
1365
1366/* RCC_R49CIDCFGR register fields */
1367#define RCC_R49CIDCFGR_CFEN BIT(0)
1368#define RCC_R49CIDCFGR_SEM_EN BIT(1)
1369#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1370#define RCC_R49CIDCFGR_SCID_SHIFT 4
1371#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1372#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16
1373
1374/* RCC_R49SEMCR register fields */
1375#define RCC_R49SEMCR_SEM_MUTEX BIT(0)
1376#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1377#define RCC_R49SEMCR_SEMCID_SHIFT 4
1378
1379/* RCC_R50CIDCFGR register fields */
1380#define RCC_R50CIDCFGR_CFEN BIT(0)
1381#define RCC_R50CIDCFGR_SEM_EN BIT(1)
1382#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1383#define RCC_R50CIDCFGR_SCID_SHIFT 4
1384#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1385#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16
1386
1387/* RCC_R50SEMCR register fields */
1388#define RCC_R50SEMCR_SEM_MUTEX BIT(0)
1389#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1390#define RCC_R50SEMCR_SEMCID_SHIFT 4
1391
1392/* RCC_R51CIDCFGR register fields */
1393#define RCC_R51CIDCFGR_CFEN BIT(0)
1394#define RCC_R51CIDCFGR_SEM_EN BIT(1)
1395#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1396#define RCC_R51CIDCFGR_SCID_SHIFT 4
1397#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1398#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16
1399
1400/* RCC_R51SEMCR register fields */
1401#define RCC_R51SEMCR_SEM_MUTEX BIT(0)
1402#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1403#define RCC_R51SEMCR_SEMCID_SHIFT 4
1404
1405/* RCC_R52CIDCFGR register fields */
1406#define RCC_R52CIDCFGR_CFEN BIT(0)
1407#define RCC_R52CIDCFGR_SEM_EN BIT(1)
1408#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1409#define RCC_R52CIDCFGR_SCID_SHIFT 4
1410#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1411#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16
1412
1413/* RCC_R52SEMCR register fields */
1414#define RCC_R52SEMCR_SEM_MUTEX BIT(0)
1415#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1416#define RCC_R52SEMCR_SEMCID_SHIFT 4
1417
1418/* RCC_R53CIDCFGR register fields */
1419#define RCC_R53CIDCFGR_CFEN BIT(0)
1420#define RCC_R53CIDCFGR_SEM_EN BIT(1)
1421#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1422#define RCC_R53CIDCFGR_SCID_SHIFT 4
1423#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1424#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16
1425
1426/* RCC_R53SEMCR register fields */
1427#define RCC_R53SEMCR_SEM_MUTEX BIT(0)
1428#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1429#define RCC_R53SEMCR_SEMCID_SHIFT 4
1430
1431/* RCC_R54CIDCFGR register fields */
1432#define RCC_R54CIDCFGR_CFEN BIT(0)
1433#define RCC_R54CIDCFGR_SEM_EN BIT(1)
1434#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1435#define RCC_R54CIDCFGR_SCID_SHIFT 4
1436#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1437#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16
1438
1439/* RCC_R54SEMCR register fields */
1440#define RCC_R54SEMCR_SEM_MUTEX BIT(0)
1441#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1442#define RCC_R54SEMCR_SEMCID_SHIFT 4
1443
1444/* RCC_R55CIDCFGR register fields */
1445#define RCC_R55CIDCFGR_CFEN BIT(0)
1446#define RCC_R55CIDCFGR_SEM_EN BIT(1)
1447#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1448#define RCC_R55CIDCFGR_SCID_SHIFT 4
1449#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1450#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16
1451
1452/* RCC_R55SEMCR register fields */
1453#define RCC_R55SEMCR_SEM_MUTEX BIT(0)
1454#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1455#define RCC_R55SEMCR_SEMCID_SHIFT 4
1456
1457/* RCC_R56CIDCFGR register fields */
1458#define RCC_R56CIDCFGR_CFEN BIT(0)
1459#define RCC_R56CIDCFGR_SEM_EN BIT(1)
1460#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1461#define RCC_R56CIDCFGR_SCID_SHIFT 4
1462#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1463#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16
1464
1465/* RCC_R56SEMCR register fields */
1466#define RCC_R56SEMCR_SEM_MUTEX BIT(0)
1467#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1468#define RCC_R56SEMCR_SEMCID_SHIFT 4
1469
1470/* RCC_R57CIDCFGR register fields */
1471#define RCC_R57CIDCFGR_CFEN BIT(0)
1472#define RCC_R57CIDCFGR_SEM_EN BIT(1)
1473#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1474#define RCC_R57CIDCFGR_SCID_SHIFT 4
1475#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1476#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16
1477
1478/* RCC_R57SEMCR register fields */
1479#define RCC_R57SEMCR_SEM_MUTEX BIT(0)
1480#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1481#define RCC_R57SEMCR_SEMCID_SHIFT 4
1482
1483/* RCC_R58CIDCFGR register fields */
1484#define RCC_R58CIDCFGR_CFEN BIT(0)
1485#define RCC_R58CIDCFGR_SEM_EN BIT(1)
1486#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1487#define RCC_R58CIDCFGR_SCID_SHIFT 4
1488#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1489#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16
1490
1491/* RCC_R58SEMCR register fields */
1492#define RCC_R58SEMCR_SEM_MUTEX BIT(0)
1493#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1494#define RCC_R58SEMCR_SEMCID_SHIFT 4
1495
1496/* RCC_R59CIDCFGR register fields */
1497#define RCC_R59CIDCFGR_CFEN BIT(0)
1498#define RCC_R59CIDCFGR_SEM_EN BIT(1)
1499#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1500#define RCC_R59CIDCFGR_SCID_SHIFT 4
1501#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1502#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16
1503
1504/* RCC_R59SEMCR register fields */
1505#define RCC_R59SEMCR_SEM_MUTEX BIT(0)
1506#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1507#define RCC_R59SEMCR_SEMCID_SHIFT 4
1508
1509/* RCC_R60CIDCFGR register fields */
1510#define RCC_R60CIDCFGR_CFEN BIT(0)
1511#define RCC_R60CIDCFGR_SEM_EN BIT(1)
1512#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1513#define RCC_R60CIDCFGR_SCID_SHIFT 4
1514#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1515#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16
1516
1517/* RCC_R60SEMCR register fields */
1518#define RCC_R60SEMCR_SEM_MUTEX BIT(0)
1519#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1520#define RCC_R60SEMCR_SEMCID_SHIFT 4
1521
1522/* RCC_R61CIDCFGR register fields */
1523#define RCC_R61CIDCFGR_CFEN BIT(0)
1524#define RCC_R61CIDCFGR_SEM_EN BIT(1)
1525#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1526#define RCC_R61CIDCFGR_SCID_SHIFT 4
1527#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1528#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16
1529
1530/* RCC_R61SEMCR register fields */
1531#define RCC_R61SEMCR_SEM_MUTEX BIT(0)
1532#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1533#define RCC_R61SEMCR_SEMCID_SHIFT 4
1534
1535/* RCC_R62CIDCFGR register fields */
1536#define RCC_R62CIDCFGR_CFEN BIT(0)
1537#define RCC_R62CIDCFGR_SEM_EN BIT(1)
1538#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1539#define RCC_R62CIDCFGR_SCID_SHIFT 4
1540#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1541#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16
1542
1543/* RCC_R62SEMCR register fields */
1544#define RCC_R62SEMCR_SEM_MUTEX BIT(0)
1545#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1546#define RCC_R62SEMCR_SEMCID_SHIFT 4
1547
1548/* RCC_R63CIDCFGR register fields */
1549#define RCC_R63CIDCFGR_CFEN BIT(0)
1550#define RCC_R63CIDCFGR_SEM_EN BIT(1)
1551#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1552#define RCC_R63CIDCFGR_SCID_SHIFT 4
1553#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1554#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16
1555
1556/* RCC_R63SEMCR register fields */
1557#define RCC_R63SEMCR_SEM_MUTEX BIT(0)
1558#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1559#define RCC_R63SEMCR_SEMCID_SHIFT 4
1560
1561/* RCC_R64CIDCFGR register fields */
1562#define RCC_R64CIDCFGR_CFEN BIT(0)
1563#define RCC_R64CIDCFGR_SEM_EN BIT(1)
1564#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1565#define RCC_R64CIDCFGR_SCID_SHIFT 4
1566#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1567#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16
1568
1569/* RCC_R64SEMCR register fields */
1570#define RCC_R64SEMCR_SEM_MUTEX BIT(0)
1571#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1572#define RCC_R64SEMCR_SEMCID_SHIFT 4
1573
1574/* RCC_R65CIDCFGR register fields */
1575#define RCC_R65CIDCFGR_CFEN BIT(0)
1576#define RCC_R65CIDCFGR_SEM_EN BIT(1)
1577#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1578#define RCC_R65CIDCFGR_SCID_SHIFT 4
1579#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1580#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16
1581
1582/* RCC_R65SEMCR register fields */
1583#define RCC_R65SEMCR_SEM_MUTEX BIT(0)
1584#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1585#define RCC_R65SEMCR_SEMCID_SHIFT 4
1586
1587/* RCC_R66CIDCFGR register fields */
1588#define RCC_R66CIDCFGR_CFEN BIT(0)
1589#define RCC_R66CIDCFGR_SEM_EN BIT(1)
1590#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1591#define RCC_R66CIDCFGR_SCID_SHIFT 4
1592#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1593#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16
1594
1595/* RCC_R66SEMCR register fields */
1596#define RCC_R66SEMCR_SEM_MUTEX BIT(0)
1597#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1598#define RCC_R66SEMCR_SEMCID_SHIFT 4
1599
1600/* RCC_R67CIDCFGR register fields */
1601#define RCC_R67CIDCFGR_CFEN BIT(0)
1602#define RCC_R67CIDCFGR_SEM_EN BIT(1)
1603#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1604#define RCC_R67CIDCFGR_SCID_SHIFT 4
1605#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1606#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16
1607
1608/* RCC_R67SEMCR register fields */
1609#define RCC_R67SEMCR_SEM_MUTEX BIT(0)
1610#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1611#define RCC_R67SEMCR_SEMCID_SHIFT 4
1612
1613/* RCC_R68CIDCFGR register fields */
1614#define RCC_R68CIDCFGR_CFEN BIT(0)
1615#define RCC_R68CIDCFGR_SEM_EN BIT(1)
1616#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1617#define RCC_R68CIDCFGR_SCID_SHIFT 4
1618#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1619#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16
1620
1621/* RCC_R68SEMCR register fields */
1622#define RCC_R68SEMCR_SEM_MUTEX BIT(0)
1623#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1624#define RCC_R68SEMCR_SEMCID_SHIFT 4
1625
1626/* RCC_R69CIDCFGR register fields */
1627#define RCC_R69CIDCFGR_CFEN BIT(0)
1628#define RCC_R69CIDCFGR_SEM_EN BIT(1)
1629#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1630#define RCC_R69CIDCFGR_SCID_SHIFT 4
1631#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1632#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16
1633
1634/* RCC_R69SEMCR register fields */
1635#define RCC_R69SEMCR_SEM_MUTEX BIT(0)
1636#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1637#define RCC_R69SEMCR_SEMCID_SHIFT 4
1638
1639/* RCC_R70CIDCFGR register fields */
1640#define RCC_R70CIDCFGR_CFEN BIT(0)
1641#define RCC_R70CIDCFGR_SEM_EN BIT(1)
1642#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1643#define RCC_R70CIDCFGR_SCID_SHIFT 4
1644#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1645#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16
1646
1647/* RCC_R70SEMCR register fields */
1648#define RCC_R70SEMCR_SEM_MUTEX BIT(0)
1649#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1650#define RCC_R70SEMCR_SEMCID_SHIFT 4
1651
1652/* RCC_R71CIDCFGR register fields */
1653#define RCC_R71CIDCFGR_CFEN BIT(0)
1654#define RCC_R71CIDCFGR_SEM_EN BIT(1)
1655#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1656#define RCC_R71CIDCFGR_SCID_SHIFT 4
1657#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1658#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16
1659
1660/* RCC_R71SEMCR register fields */
1661#define RCC_R71SEMCR_SEM_MUTEX BIT(0)
1662#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1663#define RCC_R71SEMCR_SEMCID_SHIFT 4
1664
1665/* RCC_R72CIDCFGR register fields */
1666#define RCC_R72CIDCFGR_CFEN BIT(0)
1667#define RCC_R72CIDCFGR_SEM_EN BIT(1)
1668#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1669#define RCC_R72CIDCFGR_SCID_SHIFT 4
1670#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1671#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16
1672
1673/* RCC_R72SEMCR register fields */
1674#define RCC_R72SEMCR_SEM_MUTEX BIT(0)
1675#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1676#define RCC_R72SEMCR_SEMCID_SHIFT 4
1677
1678/* RCC_R73CIDCFGR register fields */
1679#define RCC_R73CIDCFGR_CFEN BIT(0)
1680#define RCC_R73CIDCFGR_SEM_EN BIT(1)
1681#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1682#define RCC_R73CIDCFGR_SCID_SHIFT 4
1683#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1684#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16
1685
1686/* RCC_R73SEMCR register fields */
1687#define RCC_R73SEMCR_SEM_MUTEX BIT(0)
1688#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1689#define RCC_R73SEMCR_SEMCID_SHIFT 4
1690
1691/* RCC_R74CIDCFGR register fields */
1692#define RCC_R74CIDCFGR_CFEN BIT(0)
1693#define RCC_R74CIDCFGR_SEM_EN BIT(1)
1694#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1695#define RCC_R74CIDCFGR_SCID_SHIFT 4
1696#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1697#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16
1698
1699/* RCC_R74SEMCR register fields */
1700#define RCC_R74SEMCR_SEM_MUTEX BIT(0)
1701#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1702#define RCC_R74SEMCR_SEMCID_SHIFT 4
1703
1704/* RCC_R75CIDCFGR register fields */
1705#define RCC_R75CIDCFGR_CFEN BIT(0)
1706#define RCC_R75CIDCFGR_SEM_EN BIT(1)
1707#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1708#define RCC_R75CIDCFGR_SCID_SHIFT 4
1709#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1710#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16
1711
1712/* RCC_R75SEMCR register fields */
1713#define RCC_R75SEMCR_SEM_MUTEX BIT(0)
1714#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1715#define RCC_R75SEMCR_SEMCID_SHIFT 4
1716
1717/* RCC_R76CIDCFGR register fields */
1718#define RCC_R76CIDCFGR_CFEN BIT(0)
1719#define RCC_R76CIDCFGR_SEM_EN BIT(1)
1720#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1721#define RCC_R76CIDCFGR_SCID_SHIFT 4
1722#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1723#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16
1724
1725/* RCC_R76SEMCR register fields */
1726#define RCC_R76SEMCR_SEM_MUTEX BIT(0)
1727#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1728#define RCC_R76SEMCR_SEMCID_SHIFT 4
1729
1730/* RCC_R77CIDCFGR register fields */
1731#define RCC_R77CIDCFGR_CFEN BIT(0)
1732#define RCC_R77CIDCFGR_SEM_EN BIT(1)
1733#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1734#define RCC_R77CIDCFGR_SCID_SHIFT 4
1735#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1736#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16
1737
1738/* RCC_R77SEMCR register fields */
1739#define RCC_R77SEMCR_SEM_MUTEX BIT(0)
1740#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1741#define RCC_R77SEMCR_SEMCID_SHIFT 4
1742
1743/* RCC_R78CIDCFGR register fields */
1744#define RCC_R78CIDCFGR_CFEN BIT(0)
1745#define RCC_R78CIDCFGR_SEM_EN BIT(1)
1746#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1747#define RCC_R78CIDCFGR_SCID_SHIFT 4
1748#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1749#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16
1750
1751/* RCC_R78SEMCR register fields */
1752#define RCC_R78SEMCR_SEM_MUTEX BIT(0)
1753#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1754#define RCC_R78SEMCR_SEMCID_SHIFT 4
1755
1756/* RCC_R79CIDCFGR register fields */
1757#define RCC_R79CIDCFGR_CFEN BIT(0)
1758#define RCC_R79CIDCFGR_SEM_EN BIT(1)
1759#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1760#define RCC_R79CIDCFGR_SCID_SHIFT 4
1761#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1762#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16
1763
1764/* RCC_R79SEMCR register fields */
1765#define RCC_R79SEMCR_SEM_MUTEX BIT(0)
1766#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1767#define RCC_R79SEMCR_SEMCID_SHIFT 4
1768
1769/* RCC_R80CIDCFGR register fields */
1770#define RCC_R80CIDCFGR_CFEN BIT(0)
1771#define RCC_R80CIDCFGR_SEM_EN BIT(1)
1772#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1773#define RCC_R80CIDCFGR_SCID_SHIFT 4
1774#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1775#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16
1776
1777/* RCC_R80SEMCR register fields */
1778#define RCC_R80SEMCR_SEM_MUTEX BIT(0)
1779#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1780#define RCC_R80SEMCR_SEMCID_SHIFT 4
1781
1782/* RCC_R81CIDCFGR register fields */
1783#define RCC_R81CIDCFGR_CFEN BIT(0)
1784#define RCC_R81CIDCFGR_SEM_EN BIT(1)
1785#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1786#define RCC_R81CIDCFGR_SCID_SHIFT 4
1787#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1788#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16
1789
1790/* RCC_R81SEMCR register fields */
1791#define RCC_R81SEMCR_SEM_MUTEX BIT(0)
1792#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1793#define RCC_R81SEMCR_SEMCID_SHIFT 4
1794
1795/* RCC_R82CIDCFGR register fields */
1796#define RCC_R82CIDCFGR_CFEN BIT(0)
1797#define RCC_R82CIDCFGR_SEM_EN BIT(1)
1798#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1799#define RCC_R82CIDCFGR_SCID_SHIFT 4
1800#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1801#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16
1802
1803/* RCC_R82SEMCR register fields */
1804#define RCC_R82SEMCR_SEM_MUTEX BIT(0)
1805#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1806#define RCC_R82SEMCR_SEMCID_SHIFT 4
1807
1808/* RCC_R83CIDCFGR register fields */
1809#define RCC_R83CIDCFGR_CFEN BIT(0)
1810#define RCC_R83CIDCFGR_SEM_EN BIT(1)
1811#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1812#define RCC_R83CIDCFGR_SCID_SHIFT 4
1813#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1814#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16
1815
1816/* RCC_R83SEMCR register fields */
1817#define RCC_R83SEMCR_SEM_MUTEX BIT(0)
1818#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1819#define RCC_R83SEMCR_SEMCID_SHIFT 4
1820
1821/* RCC_R84CIDCFGR register fields */
1822#define RCC_R84CIDCFGR_CFEN BIT(0)
1823#define RCC_R84CIDCFGR_SEM_EN BIT(1)
1824#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1825#define RCC_R84CIDCFGR_SCID_SHIFT 4
1826#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1827#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16
1828
1829/* RCC_R84SEMCR register fields */
1830#define RCC_R84SEMCR_SEM_MUTEX BIT(0)
1831#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1832#define RCC_R84SEMCR_SEMCID_SHIFT 4
1833
1834/* RCC_R85CIDCFGR register fields */
1835#define RCC_R85CIDCFGR_CFEN BIT(0)
1836#define RCC_R85CIDCFGR_SEM_EN BIT(1)
1837#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1838#define RCC_R85CIDCFGR_SCID_SHIFT 4
1839#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1840#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16
1841
1842/* RCC_R85SEMCR register fields */
1843#define RCC_R85SEMCR_SEM_MUTEX BIT(0)
1844#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1845#define RCC_R85SEMCR_SEMCID_SHIFT 4
1846
1847/* RCC_R86CIDCFGR register fields */
1848#define RCC_R86CIDCFGR_CFEN BIT(0)
1849#define RCC_R86CIDCFGR_SEM_EN BIT(1)
1850#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1851#define RCC_R86CIDCFGR_SCID_SHIFT 4
1852#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1853#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16
1854
1855/* RCC_R86SEMCR register fields */
1856#define RCC_R86SEMCR_SEM_MUTEX BIT(0)
1857#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1858#define RCC_R86SEMCR_SEMCID_SHIFT 4
1859
1860/* RCC_R87CIDCFGR register fields */
1861#define RCC_R87CIDCFGR_CFEN BIT(0)
1862#define RCC_R87CIDCFGR_SEM_EN BIT(1)
1863#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1864#define RCC_R87CIDCFGR_SCID_SHIFT 4
1865#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1866#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16
1867
1868/* RCC_R87SEMCR register fields */
1869#define RCC_R87SEMCR_SEM_MUTEX BIT(0)
1870#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1871#define RCC_R87SEMCR_SEMCID_SHIFT 4
1872
1873/* RCC_R88CIDCFGR register fields */
1874#define RCC_R88CIDCFGR_CFEN BIT(0)
1875#define RCC_R88CIDCFGR_SEM_EN BIT(1)
1876#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1877#define RCC_R88CIDCFGR_SCID_SHIFT 4
1878#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1879#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16
1880
1881/* RCC_R88SEMCR register fields */
1882#define RCC_R88SEMCR_SEM_MUTEX BIT(0)
1883#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1884#define RCC_R88SEMCR_SEMCID_SHIFT 4
1885
1886/* RCC_R89CIDCFGR register fields */
1887#define RCC_R89CIDCFGR_CFEN BIT(0)
1888#define RCC_R89CIDCFGR_SEM_EN BIT(1)
1889#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1890#define RCC_R89CIDCFGR_SCID_SHIFT 4
1891#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1892#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16
1893
1894/* RCC_R89SEMCR register fields */
1895#define RCC_R89SEMCR_SEM_MUTEX BIT(0)
1896#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1897#define RCC_R89SEMCR_SEMCID_SHIFT 4
1898
1899/* RCC_R90CIDCFGR register fields */
1900#define RCC_R90CIDCFGR_CFEN BIT(0)
1901#define RCC_R90CIDCFGR_SEM_EN BIT(1)
1902#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1903#define RCC_R90CIDCFGR_SCID_SHIFT 4
1904#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1905#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16
1906
1907/* RCC_R90SEMCR register fields */
1908#define RCC_R90SEMCR_SEM_MUTEX BIT(0)
1909#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1910#define RCC_R90SEMCR_SEMCID_SHIFT 4
1911
1912/* RCC_R91CIDCFGR register fields */
1913#define RCC_R91CIDCFGR_CFEN BIT(0)
1914#define RCC_R91CIDCFGR_SEM_EN BIT(1)
1915#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1916#define RCC_R91CIDCFGR_SCID_SHIFT 4
1917#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1918#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16
1919
1920/* RCC_R91SEMCR register fields */
1921#define RCC_R91SEMCR_SEM_MUTEX BIT(0)
1922#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1923#define RCC_R91SEMCR_SEMCID_SHIFT 4
1924
1925/* RCC_R92CIDCFGR register fields */
1926#define RCC_R92CIDCFGR_CFEN BIT(0)
1927#define RCC_R92CIDCFGR_SEM_EN BIT(1)
1928#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1929#define RCC_R92CIDCFGR_SCID_SHIFT 4
1930#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1931#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16
1932
1933/* RCC_R92SEMCR register fields */
1934#define RCC_R92SEMCR_SEM_MUTEX BIT(0)
1935#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1936#define RCC_R92SEMCR_SEMCID_SHIFT 4
1937
1938/* RCC_R93CIDCFGR register fields */
1939#define RCC_R93CIDCFGR_CFEN BIT(0)
1940#define RCC_R93CIDCFGR_SEM_EN BIT(1)
1941#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1942#define RCC_R93CIDCFGR_SCID_SHIFT 4
1943#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1944#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16
1945
1946/* RCC_R93SEMCR register fields */
1947#define RCC_R93SEMCR_SEM_MUTEX BIT(0)
1948#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1949#define RCC_R93SEMCR_SEMCID_SHIFT 4
1950
1951/* RCC_R94CIDCFGR register fields */
1952#define RCC_R94CIDCFGR_CFEN BIT(0)
1953#define RCC_R94CIDCFGR_SEM_EN BIT(1)
1954#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1955#define RCC_R94CIDCFGR_SCID_SHIFT 4
1956#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1957#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16
1958
1959/* RCC_R94SEMCR register fields */
1960#define RCC_R94SEMCR_SEM_MUTEX BIT(0)
1961#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1962#define RCC_R94SEMCR_SEMCID_SHIFT 4
1963
1964/* RCC_R95CIDCFGR register fields */
1965#define RCC_R95CIDCFGR_CFEN BIT(0)
1966#define RCC_R95CIDCFGR_SEM_EN BIT(1)
1967#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1968#define RCC_R95CIDCFGR_SCID_SHIFT 4
1969#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1970#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16
1971
1972/* RCC_R95SEMCR register fields */
1973#define RCC_R95SEMCR_SEM_MUTEX BIT(0)
1974#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1975#define RCC_R95SEMCR_SEMCID_SHIFT 4
1976
1977/* RCC_R96CIDCFGR register fields */
1978#define RCC_R96CIDCFGR_CFEN BIT(0)
1979#define RCC_R96CIDCFGR_SEM_EN BIT(1)
1980#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1981#define RCC_R96CIDCFGR_SCID_SHIFT 4
1982#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1983#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16
1984
1985/* RCC_R96SEMCR register fields */
1986#define RCC_R96SEMCR_SEM_MUTEX BIT(0)
1987#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4)
1988#define RCC_R96SEMCR_SEMCID_SHIFT 4
1989
1990/* RCC_R97CIDCFGR register fields */
1991#define RCC_R97CIDCFGR_CFEN BIT(0)
1992#define RCC_R97CIDCFGR_SEM_EN BIT(1)
1993#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4)
1994#define RCC_R97CIDCFGR_SCID_SHIFT 4
1995#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
1996#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16
1997
1998/* RCC_R97SEMCR register fields */
1999#define RCC_R97SEMCR_SEM_MUTEX BIT(0)
2000#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2001#define RCC_R97SEMCR_SEMCID_SHIFT 4
2002
2003/* RCC_R98CIDCFGR register fields */
2004#define RCC_R98CIDCFGR_CFEN BIT(0)
2005#define RCC_R98CIDCFGR_SEM_EN BIT(1)
2006#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2007#define RCC_R98CIDCFGR_SCID_SHIFT 4
2008#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2009#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16
2010
2011/* RCC_R98SEMCR register fields */
2012#define RCC_R98SEMCR_SEM_MUTEX BIT(0)
2013#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2014#define RCC_R98SEMCR_SEMCID_SHIFT 4
2015
2016/* RCC_R99CIDCFGR register fields */
2017#define RCC_R99CIDCFGR_CFEN BIT(0)
2018#define RCC_R99CIDCFGR_SEM_EN BIT(1)
2019#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2020#define RCC_R99CIDCFGR_SCID_SHIFT 4
2021#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2022#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16
2023
2024/* RCC_R99SEMCR register fields */
2025#define RCC_R99SEMCR_SEM_MUTEX BIT(0)
2026#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2027#define RCC_R99SEMCR_SEMCID_SHIFT 4
2028
2029/* RCC_R100CIDCFGR register fields */
2030#define RCC_R100CIDCFGR_CFEN BIT(0)
2031#define RCC_R100CIDCFGR_SEM_EN BIT(1)
2032#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2033#define RCC_R100CIDCFGR_SCID_SHIFT 4
2034#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2035#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16
2036
2037/* RCC_R100SEMCR register fields */
2038#define RCC_R100SEMCR_SEM_MUTEX BIT(0)
2039#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2040#define RCC_R100SEMCR_SEMCID_SHIFT 4
2041
2042/* RCC_R101CIDCFGR register fields */
2043#define RCC_R101CIDCFGR_CFEN BIT(0)
2044#define RCC_R101CIDCFGR_SEM_EN BIT(1)
2045#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2046#define RCC_R101CIDCFGR_SCID_SHIFT 4
2047#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2048#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16
2049
2050/* RCC_R101SEMCR register fields */
2051#define RCC_R101SEMCR_SEM_MUTEX BIT(0)
2052#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2053#define RCC_R101SEMCR_SEMCID_SHIFT 4
2054
2055/* RCC_R102CIDCFGR register fields */
2056#define RCC_R102CIDCFGR_CFEN BIT(0)
2057#define RCC_R102CIDCFGR_SEM_EN BIT(1)
2058#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2059#define RCC_R102CIDCFGR_SCID_SHIFT 4
2060#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2061#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16
2062
2063/* RCC_R102SEMCR register fields */
2064#define RCC_R102SEMCR_SEM_MUTEX BIT(0)
2065#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2066#define RCC_R102SEMCR_SEMCID_SHIFT 4
2067
2068/* RCC_R103CIDCFGR register fields */
2069#define RCC_R103CIDCFGR_CFEN BIT(0)
2070#define RCC_R103CIDCFGR_SEM_EN BIT(1)
2071#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2072#define RCC_R103CIDCFGR_SCID_SHIFT 4
2073#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2074#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16
2075
2076/* RCC_R103SEMCR register fields */
2077#define RCC_R103SEMCR_SEM_MUTEX BIT(0)
2078#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2079#define RCC_R103SEMCR_SEMCID_SHIFT 4
2080
2081/* RCC_R104CIDCFGR register fields */
2082#define RCC_R104CIDCFGR_CFEN BIT(0)
2083#define RCC_R104CIDCFGR_SEM_EN BIT(1)
2084#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2085#define RCC_R104CIDCFGR_SCID_SHIFT 4
2086#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2087#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16
2088
2089/* RCC_R104SEMCR register fields */
2090#define RCC_R104SEMCR_SEM_MUTEX BIT(0)
2091#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2092#define RCC_R104SEMCR_SEMCID_SHIFT 4
2093
2094/* RCC_R105CIDCFGR register fields */
2095#define RCC_R105CIDCFGR_CFEN BIT(0)
2096#define RCC_R105CIDCFGR_SEM_EN BIT(1)
2097#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2098#define RCC_R105CIDCFGR_SCID_SHIFT 4
2099#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2100#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16
2101
2102/* RCC_R105SEMCR register fields */
2103#define RCC_R105SEMCR_SEM_MUTEX BIT(0)
2104#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2105#define RCC_R105SEMCR_SEMCID_SHIFT 4
2106
2107/* RCC_R106CIDCFGR register fields */
2108#define RCC_R106CIDCFGR_CFEN BIT(0)
2109#define RCC_R106CIDCFGR_SEM_EN BIT(1)
2110#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2111#define RCC_R106CIDCFGR_SCID_SHIFT 4
2112#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2113#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16
2114
2115/* RCC_R106SEMCR register fields */
2116#define RCC_R106SEMCR_SEM_MUTEX BIT(0)
2117#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2118#define RCC_R106SEMCR_SEMCID_SHIFT 4
2119
2120/* RCC_R107CIDCFGR register fields */
2121#define RCC_R107CIDCFGR_CFEN BIT(0)
2122#define RCC_R107CIDCFGR_SEM_EN BIT(1)
2123#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2124#define RCC_R107CIDCFGR_SCID_SHIFT 4
2125#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2126#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16
2127
2128/* RCC_R107SEMCR register fields */
2129#define RCC_R107SEMCR_SEM_MUTEX BIT(0)
2130#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2131#define RCC_R107SEMCR_SEMCID_SHIFT 4
2132
2133/* RCC_R108CIDCFGR register fields */
2134#define RCC_R108CIDCFGR_CFEN BIT(0)
2135#define RCC_R108CIDCFGR_SEM_EN BIT(1)
2136#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2137#define RCC_R108CIDCFGR_SCID_SHIFT 4
2138#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2139#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16
2140
2141/* RCC_R108SEMCR register fields */
2142#define RCC_R108SEMCR_SEM_MUTEX BIT(0)
2143#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2144#define RCC_R108SEMCR_SEMCID_SHIFT 4
2145
2146/* RCC_R109CIDCFGR register fields */
2147#define RCC_R109CIDCFGR_CFEN BIT(0)
2148#define RCC_R109CIDCFGR_SEM_EN BIT(1)
2149#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2150#define RCC_R109CIDCFGR_SCID_SHIFT 4
2151#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2152#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16
2153
2154/* RCC_R109SEMCR register fields */
2155#define RCC_R109SEMCR_SEM_MUTEX BIT(0)
2156#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2157#define RCC_R109SEMCR_SEMCID_SHIFT 4
2158
2159/* RCC_R110CIDCFGR register fields */
2160#define RCC_R110CIDCFGR_CFEN BIT(0)
2161#define RCC_R110CIDCFGR_SEM_EN BIT(1)
2162#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2163#define RCC_R110CIDCFGR_SCID_SHIFT 4
2164#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2165#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16
2166
2167/* RCC_R110SEMCR register fields */
2168#define RCC_R110SEMCR_SEM_MUTEX BIT(0)
2169#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2170#define RCC_R110SEMCR_SEMCID_SHIFT 4
2171
2172/* RCC_R111CIDCFGR register fields */
2173#define RCC_R111CIDCFGR_CFEN BIT(0)
2174#define RCC_R111CIDCFGR_SEM_EN BIT(1)
2175#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2176#define RCC_R111CIDCFGR_SCID_SHIFT 4
2177#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2178#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16
2179
2180/* RCC_R111SEMCR register fields */
2181#define RCC_R111SEMCR_SEM_MUTEX BIT(0)
2182#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2183#define RCC_R111SEMCR_SEMCID_SHIFT 4
2184
2185/* RCC_R112CIDCFGR register fields */
2186#define RCC_R112CIDCFGR_CFEN BIT(0)
2187#define RCC_R112CIDCFGR_SEM_EN BIT(1)
2188#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2189#define RCC_R112CIDCFGR_SCID_SHIFT 4
2190#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2191#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16
2192
2193/* RCC_R112SEMCR register fields */
2194#define RCC_R112SEMCR_SEM_MUTEX BIT(0)
2195#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2196#define RCC_R112SEMCR_SEMCID_SHIFT 4
2197
2198/* RCC_R113CIDCFGR register fields */
2199#define RCC_R113CIDCFGR_CFEN BIT(0)
2200#define RCC_R113CIDCFGR_SEM_EN BIT(1)
2201#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4)
2202#define RCC_R113CIDCFGR_SCID_SHIFT 4
2203#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2204#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16
2205
2206/* RCC_R113SEMCR register fields */
2207#define RCC_R113SEMCR_SEM_MUTEX BIT(0)
2208#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4)
2209#define RCC_R113SEMCR_SEMCID_SHIFT 4
2210
2211/* RCC_RxCIDCFGR register fields */
2212#define RCC_RxCIDCFGR_CFEN BIT(0)
2213#define RCC_RxCIDCFGR_SEM_EN BIT(1)
2214#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4)
2215#define RCC_RxCIDCFGR_SCID_SHIFT 4
2216#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
2217#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16
2218
2219/* RCC_RxSEMCR register fields */
2220#define RCC_RxSEMCR_SEM_MUTEX BIT(0)
2221#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4)
2222#define RCC_RxSEMCR_SEMCID_SHIFT 4
2223
2224/* RCC_GRSTCSETR register fields */
2225#define RCC_GRSTCSETR_SYSRST BIT(0)
2226
2227/* RCC_C1RSTCSETR register fields */
2228#define RCC_C1RSTCSETR_C1RST BIT(0)
2229
2230/* RCC_C1P1RSTCSETR register fields */
2231#define RCC_C1P1RSTCSETR_C1P1PORRST BIT(0)
2232#define RCC_C1P1RSTCSETR_C1P1RST BIT(1)
2233
2234/* RCC_C2RSTCSETR register fields */
2235#define RCC_C2RSTCSETR_C2RST BIT(0)
2236
2237/* RCC_CxRSTCSETR register fields */
2238#define RCC_CxRSTCSETR_CxRST BIT(0)
2239
2240/* RCC_HWRSTSCLRR register fields */
2241#define RCC_HWRSTSCLRR_PORRSTF BIT(0)
2242#define RCC_HWRSTSCLRR_BORRSTF BIT(1)
2243#define RCC_HWRSTSCLRR_PADRSTF BIT(2)
2244#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3)
2245#define RCC_HWRSTSCLRR_VCORERSTF BIT(4)
2246#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5)
2247#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6)
2248#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7)
2249#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8)
2250#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9)
2251#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10)
2252#define RCC_HWRSTSCLRR_IWDG5SYSRSTF BIT(11)
2253#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12)
2254#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13)
2255#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14)
2256
2257/* RCC_C1HWRSTSCLRR register fields */
2258#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0)
2259#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1)
2260#define RCC_C1HWRSTSCLRR_C1P1RSTF BIT(2)
2261
2262/* RCC_C2HWRSTSCLRR register fields */
2263#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0)
2264
2265/* RCC_C1BOOTRSTSSETR register fields */
2266#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0)
2267#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1)
2268#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2)
2269#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3)
2270#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4)
2271#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5)
2272#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6)
2273#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7)
2274#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
2275#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
2276#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
2277#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
2278#define RCC_C1BOOTRSTSSETR_IWDG5SYSRSTF BIT(12)
2279#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13)
2280#define RCC_C1BOOTRSTSSETR_C1P1RSTF BIT(16)
2281#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
2282#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
2283#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
2284#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20)
2285#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22)
2286#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23)
2287
2288/* RCC_C1BOOTRSTSCLRR register fields */
2289#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0)
2290#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1)
2291#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2)
2292#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3)
2293#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4)
2294#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5)
2295#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6)
2296#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7)
2297#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
2298#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
2299#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
2300#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
2301#define RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12)
2302#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13)
2303#define RCC_C1BOOTRSTSCLRR_C1P1RSTF BIT(16)
2304#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
2305#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
2306#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
2307#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20)
2308#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
2309#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
2310
Gabriel Fernandezeb6a4672025-05-07 15:45:04 +02002311#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
2312 RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
2313 RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
2314 RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF | \
2315 RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF)
2316
Yann Gautier740ca302023-06-14 18:00:58 +02002317/* RCC_C2BOOTRSTSSETR register fields */
2318#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
2319#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
2320#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2)
2321#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3)
2322#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4)
2323#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6)
2324#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7)
2325#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
2326#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
2327#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
2328#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
2329#define RCC_C2BOOTRSTSSETR_IWDG5SYSRSTF BIT(12)
2330#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14)
2331#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
2332#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
2333#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
2334#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21)
2335#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23)
2336
2337/* RCC_C2BOOTRSTSCLRR register fields */
2338#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0)
2339#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1)
2340#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2)
2341#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3)
2342#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4)
2343#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6)
2344#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7)
2345#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
2346#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
2347#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
2348#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
2349#define RCC_C2BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12)
2350#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14)
2351#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
2352#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
2353#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
2354#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21)
2355#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23)
2356
2357/* RCC_C1SREQSETR register fields */
2358#define RCC_C1SREQSETR_STPREQ_P0 BIT(0)
2359#define RCC_C1SREQSETR_STPREQ_P1 BIT(1)
Gabriel Fernandezbcd95062022-04-20 10:08:49 +02002360#define RCC_C1SREQSETR_STPREQ_MASK GENMASK_32(1, 0)
Yann Gautier740ca302023-06-14 18:00:58 +02002361#define RCC_C1SREQSETR_ESLPREQ BIT(16)
2362
2363/* RCC_C1SREQCLRR register fields */
2364#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0)
2365#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1)
Gabriel Fernandezbcd95062022-04-20 10:08:49 +02002366#define RCC_C1SREQCLRR_STPREQ_MASK GENMASK_32(1, 0)
Yann Gautier740ca302023-06-14 18:00:58 +02002367#define RCC_C1SREQCLRR_ESLPREQ BIT(16)
2368
2369/* RCC_CPUBOOTCR register fields */
2370#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0)
2371#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1)
2372
2373/* RCC_STBYBOOTCR register fields */
2374#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1)
2375#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2)
2376#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4)
2377#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5)
2378#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8)
2379
2380/* RCC_LEGBOOTCR register fields */
2381#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0)
2382
2383/* RCC_BDCR register fields */
2384#define RCC_BDCR_LSEON BIT(0)
2385#define RCC_BDCR_LSEBYP BIT(1)
2386#define RCC_BDCR_LSERDY BIT(2)
2387#define RCC_BDCR_LSEDIGBYP BIT(3)
2388#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
2389#define RCC_BDCR_LSEDRV_SHIFT 4
2390#define RCC_BDCR_LSECSSON BIT(6)
2391#define RCC_BDCR_LSEGFON BIT(7)
2392#define RCC_BDCR_LSECSSD BIT(8)
2393#define RCC_BDCR_LSION BIT(9)
2394#define RCC_BDCR_LSIRDY BIT(10)
2395#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
2396#define RCC_BDCR_RTCSRC_SHIFT 16
2397#define RCC_BDCR_RTCCKEN BIT(20)
2398#define RCC_BDCR_MSIFREQSEL BIT(24)
2399#define RCC_BDCR_C3SYSTICKSEL BIT(25)
2400#define RCC_BDCR_VSWRST BIT(31)
2401#define RCC_BDCR_LSEBYP_BIT 1
2402#define RCC_BDCR_LSEDIGBYP_BIT 3
2403#define RCC_BDCR_LSECSSON_BIT 6
2404#define RCC_BDCR_LSERDY_BIT 2
2405#define RCC_BDCR_LSIRDY_BIT 10
2406
2407#define RCC_BDCR_LSEDRV_SHIFT 4
2408#define RCC_BDCR_LSEDRV_WIDTH 2
2409
2410/* RCC_D3DCR register fields */
Gabriel Fernandezbcd95062022-04-20 10:08:49 +02002411#define RCC_D3DCR_MSION BIT(0)
2412#define RCC_D3DCR_MSIKERON BIT(1)
2413#define RCC_D3DCR_MSIRDY BIT(2)
Yann Gautier740ca302023-06-14 18:00:58 +02002414#define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16)
2415#define RCC_D3DCR_D3PERCKSEL_SHIFT 16
Gabriel Fernandezbcd95062022-04-20 10:08:49 +02002416#define RCC_D3DCR_MSIRDY_BIT 2
Yann Gautier740ca302023-06-14 18:00:58 +02002417
2418/* RCC_D3DSR register fields */
2419#define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0)
2420#define RCC_D3DSR_D3STATE_SHIFT 0
2421
2422/* RCC_RDCR register fields */
2423#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16)
2424#define RCC_RDCR_MRD_SHIFT 16
2425#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24)
2426#define RCC_RDCR_EADLY_SHIFT 24
2427
2428/* RCC_C1MSRDCR register fields */
2429#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0)
2430#define RCC_C1MSRDCR_C1MSRD_SHIFT 0
2431#define RCC_C1MSRDCR_C1MSRST BIT(8)
2432
2433/* RCC_PWRLPDLYCR register fields */
2434#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
2435#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
2436#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24)
2437
2438/* RCC_C1CIESETR register fields */
2439#define RCC_C1CIESETR_LSIRDYIE BIT(0)
2440#define RCC_C1CIESETR_LSERDYIE BIT(1)
2441#define RCC_C1CIESETR_HSIRDYIE BIT(2)
2442#define RCC_C1CIESETR_HSERDYIE BIT(3)
2443#define RCC_C1CIESETR_CSIRDYIE BIT(4)
2444#define RCC_C1CIESETR_PLL1RDYIE BIT(5)
2445#define RCC_C1CIESETR_PLL2RDYIE BIT(6)
2446#define RCC_C1CIESETR_PLL3RDYIE BIT(7)
2447#define RCC_C1CIESETR_PLL4RDYIE BIT(8)
2448#define RCC_C1CIESETR_PLL5RDYIE BIT(9)
2449#define RCC_C1CIESETR_PLL6RDYIE BIT(10)
2450#define RCC_C1CIESETR_PLL7RDYIE BIT(11)
2451#define RCC_C1CIESETR_PLL8RDYIE BIT(12)
2452#define RCC_C1CIESETR_LSECSSIE BIT(16)
2453#define RCC_C1CIESETR_WKUPIE BIT(20)
2454
2455/* RCC_C1CIFCLRR register fields */
2456#define RCC_C1CIFCLRR_LSIRDYF BIT(0)
2457#define RCC_C1CIFCLRR_LSERDYF BIT(1)
2458#define RCC_C1CIFCLRR_HSIRDYF BIT(2)
2459#define RCC_C1CIFCLRR_HSERDYF BIT(3)
2460#define RCC_C1CIFCLRR_CSIRDYF BIT(4)
2461#define RCC_C1CIFCLRR_PLL1RDYF BIT(5)
2462#define RCC_C1CIFCLRR_PLL2RDYF BIT(6)
2463#define RCC_C1CIFCLRR_PLL3RDYF BIT(7)
2464#define RCC_C1CIFCLRR_PLL4RDYF BIT(8)
2465#define RCC_C1CIFCLRR_PLL5RDYF BIT(9)
2466#define RCC_C1CIFCLRR_PLL6RDYF BIT(10)
2467#define RCC_C1CIFCLRR_PLL7RDYF BIT(11)
2468#define RCC_C1CIFCLRR_PLL8RDYF BIT(12)
2469#define RCC_C1CIFCLRR_LSECSSF BIT(16)
2470#define RCC_C1CIFCLRR_WKUPF BIT(20)
2471
2472/* RCC_C2CIESETR register fields */
2473#define RCC_C2CIESETR_LSIRDYIE BIT(0)
2474#define RCC_C2CIESETR_LSERDYIE BIT(1)
2475#define RCC_C2CIESETR_HSIRDYIE BIT(2)
2476#define RCC_C2CIESETR_HSERDYIE BIT(3)
2477#define RCC_C2CIESETR_CSIRDYIE BIT(4)
2478#define RCC_C2CIESETR_PLL1RDYIE BIT(5)
2479#define RCC_C2CIESETR_PLL2RDYIE BIT(6)
2480#define RCC_C2CIESETR_PLL3RDYIE BIT(7)
2481#define RCC_C2CIESETR_PLL4RDYIE BIT(8)
2482#define RCC_C2CIESETR_PLL5RDYIE BIT(9)
2483#define RCC_C2CIESETR_PLL6RDYIE BIT(10)
2484#define RCC_C2CIESETR_PLL7RDYIE BIT(11)
2485#define RCC_C2CIESETR_PLL8RDYIE BIT(12)
2486#define RCC_C2CIESETR_LSECSSIE BIT(16)
2487#define RCC_C2CIESETR_WKUPIE BIT(20)
2488
2489/* RCC_C2CIFCLRR register fields */
2490#define RCC_C2CIFCLRR_LSIRDYF BIT(0)
2491#define RCC_C2CIFCLRR_LSERDYF BIT(1)
2492#define RCC_C2CIFCLRR_HSIRDYF BIT(2)
2493#define RCC_C2CIFCLRR_HSERDYF BIT(3)
2494#define RCC_C2CIFCLRR_CSIRDYF BIT(4)
2495#define RCC_C2CIFCLRR_PLL1RDYF BIT(5)
2496#define RCC_C2CIFCLRR_PLL2RDYF BIT(6)
2497#define RCC_C2CIFCLRR_PLL3RDYF BIT(7)
2498#define RCC_C2CIFCLRR_PLL4RDYF BIT(8)
2499#define RCC_C2CIFCLRR_PLL5RDYF BIT(9)
2500#define RCC_C2CIFCLRR_PLL6RDYF BIT(10)
2501#define RCC_C2CIFCLRR_PLL7RDYF BIT(11)
2502#define RCC_C2CIFCLRR_PLL8RDYF BIT(12)
2503#define RCC_C2CIFCLRR_LSECSSF BIT(16)
2504#define RCC_C2CIFCLRR_WKUPF BIT(20)
2505
2506/* RCC_CxCIESETR register fields */
2507#define RCC_CxCIESETR_LSIRDYIE BIT(0)
2508#define RCC_CxCIESETR_LSERDYIE BIT(1)
2509#define RCC_CxCIESETR_HSIRDYIE BIT(2)
2510#define RCC_CxCIESETR_HSERDYIE BIT(3)
2511#define RCC_CxCIESETR_CSIRDYIE BIT(4)
2512#define RCC_CxCIESETR_SHSIRDYIE BIT(5)
2513#define RCC_CxCIESETR_PLL1RDYIE BIT(6)
2514#define RCC_CxCIESETR_PLL2RDYIE BIT(7)
2515#define RCC_CxCIESETR_PLL3RDYIE BIT(8)
2516#define RCC_CxCIESETR_PLL4RDYIE BIT(9)
2517#define RCC_CxCIESETR_PLL5RDYIE BIT(10)
2518#define RCC_CxCIESETR_PLL6RDYIE BIT(11)
2519#define RCC_CxCIESETR_PLL7RDYIE BIT(12)
2520#define RCC_CxCIESETR_PLL8RDYIE BIT(13)
2521#define RCC_CxCIESETR_LSECSSIE BIT(16)
2522#define RCC_CxCIESETR_WKUPIE BIT(20)
2523
2524/* RCC_CxCIFCLRR register fields */
2525#define RCC_CxCIFCLRR_LSIRDYF BIT(0)
2526#define RCC_CxCIFCLRR_LSERDYF BIT(1)
2527#define RCC_CxCIFCLRR_HSIRDYF BIT(2)
2528#define RCC_CxCIFCLRR_HSERDYF BIT(3)
2529#define RCC_CxCIFCLRR_CSIRDYF BIT(4)
2530#define RCC_CxCIFCLRR_SHSIRDYF BIT(5)
2531#define RCC_CxCIFCLRR_PLL1RDYF BIT(6)
2532#define RCC_CxCIFCLRR_PLL2RDYF BIT(7)
2533#define RCC_CxCIFCLRR_PLL3RDYF BIT(8)
2534#define RCC_CxCIFCLRR_PLL4RDYF BIT(9)
2535#define RCC_CxCIFCLRR_PLL5RDYF BIT(10)
2536#define RCC_CxCIFCLRR_PLL6RDYF BIT(11)
2537#define RCC_CxCIFCLRR_PLL7RDYF BIT(12)
2538#define RCC_CxCIFCLRR_PLL8RDYF BIT(13)
2539#define RCC_CxCIFCLRR_LSECSSF BIT(16)
2540#define RCC_CxCIFCLRR_WKUPF BIT(20)
2541
2542/* RCC_IWDGC1FZSETR register fields */
2543#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0)
2544#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1)
2545
2546/* RCC_IWDGC1FZCLRR register fields */
2547#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0)
2548#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1)
2549
2550/* RCC_IWDGC1CFGSETR register fields */
2551#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0)
2552#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2)
2553#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18)
2554
2555/* RCC_IWDGC1CFGCLRR register fields */
2556#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0)
2557#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2)
2558#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18)
2559
2560/* RCC_IWDGC2FZSETR register fields */
2561#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0)
2562#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1)
2563
2564/* RCC_IWDGC2FZCLRR register fields */
2565#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0)
2566#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1)
2567
2568/* RCC_IWDGC2CFGSETR register fields */
2569#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0)
2570#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2)
2571#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18)
2572
2573/* RCC_IWDGC2CFGCLRR register fields */
2574#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0)
2575#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2)
2576#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18)
2577
2578/* RCC_IWDGC3CFGSETR register fields */
2579#define RCC_IWDGC3CFGSETR_IWDG5_SYSRSTEN BIT(0)
2580
2581/* RCC_IWDGC3CFGCLRR register fields */
2582#define RCC_IWDGC3CFGCLRR_IWDG5_SYSRSTEN BIT(0)
2583
2584/* RCC_C3CFGR register fields */
2585#define RCC_C3CFGR_C3RST BIT(0)
2586#define RCC_C3CFGR_C3EN BIT(1)
2587#define RCC_C3CFGR_C3LPEN BIT(2)
2588#define RCC_C3CFGR_C3AMEN BIT(3)
2589#define RCC_C3CFGR_LPTIM3C3EN BIT(16)
2590#define RCC_C3CFGR_LPTIM4C3EN BIT(17)
2591#define RCC_C3CFGR_LPTIM5C3EN BIT(18)
2592#define RCC_C3CFGR_SPI8C3EN BIT(19)
2593#define RCC_C3CFGR_LPUART1C3EN BIT(20)
2594#define RCC_C3CFGR_I2C8C3EN BIT(21)
2595#define RCC_C3CFGR_ADF1C3EN BIT(23)
2596#define RCC_C3CFGR_GPIOZC3EN BIT(24)
2597#define RCC_C3CFGR_LPDMAC3EN BIT(25)
2598#define RCC_C3CFGR_RTCC3EN BIT(26)
2599#define RCC_C3CFGR_I3C4C3EN BIT(27)
2600
2601/* RCC_MCO1CFGR register fields */
2602#define RCC_MCO1CFGR_MCO1SEL BIT(0)
2603#define RCC_MCO1CFGR_MCO1ON BIT(8)
2604
2605/* RCC_MCO2CFGR register fields */
2606#define RCC_MCO2CFGR_MCO2SEL BIT(0)
2607#define RCC_MCO2CFGR_MCO2ON BIT(8)
2608
2609/* RCC_MCOxCFGR register fields */
2610#define RCC_MCOxCFGR_MCOxSEL BIT(0)
2611#define RCC_MCOxCFGR_MCOxON BIT(8)
2612
2613/* RCC_OCENSETR register fields */
2614#define RCC_OCENSETR_HSION BIT(0)
2615#define RCC_OCENSETR_HSIKERON BIT(1)
2616#define RCC_OCENSETR_HSEDIV2ON BIT(5)
2617#define RCC_OCENSETR_HSEDIV2BYP BIT(6)
2618#define RCC_OCENSETR_HSEDIGBYP BIT(7)
2619#define RCC_OCENSETR_HSEON BIT(8)
2620#define RCC_OCENSETR_HSEKERON BIT(9)
2621#define RCC_OCENSETR_HSEBYP BIT(10)
2622#define RCC_OCENSETR_HSECSSON BIT(11)
2623
2624/* RCC_OCENCLRR register fields */
2625#define RCC_OCENCLRR_HSION BIT(0)
2626#define RCC_OCENCLRR_HSIKERON BIT(1)
2627#define RCC_OCENCLRR_HSEDIV2ON BIT(5)
2628#define RCC_OCENCLRR_HSEDIV2BYP BIT(6)
2629#define RCC_OCENCLRR_HSEDIGBYP BIT(7)
2630#define RCC_OCENCLRR_HSEON BIT(8)
2631#define RCC_OCENCLRR_HSEKERON BIT(9)
2632#define RCC_OCENCLRR_HSEBYP BIT(10)
2633
2634/* RCC_OCRDYR register fields */
2635#define RCC_OCRDYR_HSIRDY BIT(0)
2636#define RCC_OCRDYR_HSERDY BIT(8)
2637#define RCC_OCRDYR_CKREST BIT(25)
2638
2639#define RCC_OCRDYR_HSIRDY_BIT 0
2640#define RCC_OCRDYR_HSERDY_BIT 8
2641
2642/* RCC_HSICFGR register fields */
2643#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
2644#define RCC_HSICFGR_HSITRIM_SHIFT 8
2645#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16)
2646#define RCC_HSICFGR_HSICAL_SHIFT 16
2647
2648/* RCC_CSICFGR register fields */
2649#define RCC_CSICFGR_CSITRIM_MASK GENMASK_32(12, 8)
2650#define RCC_CSICFGR_CSITRIM_SHIFT 8
2651#define RCC_CSICFGR_CSICAL_MASK GENMASK_32(23, 16)
2652#define RCC_CSICFGR_CSICAL_SHIFT 16
2653
2654/* RCC_RTCDIVR register fields */
2655#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0)
2656#define RCC_RTCDIVR_RTCDIV_SHIFT 0
2657
2658/* RCC_APB1DIVR register fields */
2659#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0)
2660#define RCC_APB1DIVR_APB1DIV_SHIFT 0
2661#define RCC_APB1DIVR_APB1DIVRDY BIT(31)
2662
2663/* RCC_APB2DIVR register fields */
2664#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0)
2665#define RCC_APB2DIVR_APB2DIV_SHIFT 0
2666#define RCC_APB2DIVR_APB2DIVRDY BIT(31)
2667
2668/* RCC_APB3DIVR register fields */
2669#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0)
2670#define RCC_APB3DIVR_APB3DIV_SHIFT 0
2671#define RCC_APB3DIVR_APB3DIVRDY BIT(31)
2672
2673/* RCC_APB4DIVR register fields */
2674#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0)
2675#define RCC_APB4DIVR_APB4DIV_SHIFT 0
2676#define RCC_APB4DIVR_APB4DIVRDY BIT(31)
2677
2678/* RCC_APBDBGDIVR register fields */
2679#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0)
2680#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0
2681#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31)
2682
2683/* RCC_APBxDIVR register fields */
2684#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0)
2685#define RCC_APBxDIVR_APBxDIV_SHIFT 0
2686#define RCC_APBxDIVR_APBxDIVRDY BIT(31)
2687
2688/* RCC_TIMG1PRER register fields */
2689#define RCC_TIMG1PRER_TIMG1PRE BIT(0)
2690#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31)
2691
2692/* RCC_TIMG2PRER register fields */
2693#define RCC_TIMG2PRER_TIMG2PRE BIT(0)
2694#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31)
2695
2696/* RCC_TIMGxPRER register fields */
2697#define RCC_TIMGxPRER_TIMGxPRE BIT(0)
2698#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31)
2699
2700/* RCC_LSMCUDIVR register fields */
2701#define RCC_LSMCUDIVR_LSMCUDIV BIT(0)
2702#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31)
2703
2704/* RCC_DDRCPCFGR register fields */
2705#define RCC_DDRCPCFGR_DDRCPRST BIT(0)
2706#define RCC_DDRCPCFGR_DDRCPEN BIT(1)
2707#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2)
2708
2709/* RCC_DDRCAPBCFGR register fields */
2710#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0)
2711#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1)
2712#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2)
2713
2714/* RCC_DDRPHYCAPBCFGR register fields */
2715#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0)
2716#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1)
2717#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2)
2718
2719/* RCC_DDRPHYCCFGR register fields */
2720#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1)
2721
2722/* RCC_DDRCFGR register fields */
2723#define RCC_DDRCFGR_DDRCFGRST BIT(0)
2724#define RCC_DDRCFGR_DDRCFGEN BIT(1)
2725#define RCC_DDRCFGR_DDRCFGLPEN BIT(2)
2726
2727/* RCC_DDRITFCFGR register fields */
2728#define RCC_DDRITFCFGR_DDRRST BIT(0)
2729#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4)
2730#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4
2731#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5)
2732#define RCC_DDRITFCFGR_DDRSHR BIT(8)
2733#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16)
2734
2735/* RCC_SYSRAMCFGR register fields */
2736#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1)
2737#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2)
2738
2739/* RCC_VDERAMCFGR register fields */
2740#define RCC_VDERAMCFGR_VDERAMEN BIT(1)
2741#define RCC_VDERAMCFGR_VDERAMLPEN BIT(2)
2742
2743/* RCC_SRAM1CFGR register fields */
2744#define RCC_SRAM1CFGR_SRAM1EN BIT(1)
2745#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2)
2746
2747/* RCC_SRAM2CFGR register fields */
2748#define RCC_SRAM2CFGR_SRAM2EN BIT(1)
2749#define RCC_SRAM2CFGR_SRAM2LPEN BIT(2)
2750
2751/* RCC_RETRAMCFGR register fields */
2752#define RCC_RETRAMCFGR_RETRAMEN BIT(1)
2753#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2)
2754
2755/* RCC_BKPSRAMCFGR register fields */
2756#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1)
2757#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2)
2758
2759/* RCC_LPSRAM1CFGR register fields */
2760#define RCC_LPSRAM1CFGR_LPSRAM1EN BIT(1)
2761#define RCC_LPSRAM1CFGR_LPSRAM1LPEN BIT(2)
2762#define RCC_LPSRAM1CFGR_LPSRAM1AMEN BIT(3)
2763
2764/* RCC_LPSRAM2CFGR register fields */
2765#define RCC_LPSRAM2CFGR_LPSRAM2EN BIT(1)
2766#define RCC_LPSRAM2CFGR_LPSRAM2LPEN BIT(2)
2767#define RCC_LPSRAM2CFGR_LPSRAM2AMEN BIT(3)
2768
2769/* RCC_LPSRAM3CFGR register fields */
2770#define RCC_LPSRAM3CFGR_LPSRAM3EN BIT(1)
2771#define RCC_LPSRAM3CFGR_LPSRAM3LPEN BIT(2)
2772#define RCC_LPSRAM3CFGR_LPSRAM3AMEN BIT(3)
2773
2774/* RCC_OSPI1CFGR register fields */
2775#define RCC_OSPI1CFGR_OSPI1RST BIT(0)
2776#define RCC_OSPI1CFGR_OSPI1EN BIT(1)
2777#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2)
2778#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8)
2779#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16)
2780
2781/* RCC_OSPI2CFGR register fields */
2782#define RCC_OSPI2CFGR_OSPI2RST BIT(0)
2783#define RCC_OSPI2CFGR_OSPI2EN BIT(1)
2784#define RCC_OSPI2CFGR_OSPI2LPEN BIT(2)
2785#define RCC_OSPI2CFGR_OTFDEC2RST BIT(8)
2786#define RCC_OSPI2CFGR_OSPI2DLLRST BIT(16)
2787
2788/* RCC_OSPIxCFGR register fields */
2789#define RCC_OSPIxCFGR_OSPIxRST BIT(0)
2790#define RCC_OSPIxCFGR_OSPIxEN BIT(1)
2791#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2)
2792#define RCC_OSPIxCFGR_OTFDECxRST BIT(8)
2793#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16)
2794
2795/* RCC_FMCCFGR register fields */
2796#define RCC_FMCCFGR_FMCRST BIT(0)
2797#define RCC_FMCCFGR_FMCEN BIT(1)
2798#define RCC_FMCCFGR_FMCLPEN BIT(2)
2799
2800/* RCC_DBGCFGR register fields */
2801#define RCC_DBGCFGR_DBGEN BIT(8)
2802#define RCC_DBGCFGR_TRACEEN BIT(9)
2803#define RCC_DBGCFGR_DBGRST BIT(12)
2804
2805/* RCC_STM500CFGR register fields */
2806#define RCC_STM500CFGR_STM500EN BIT(1)
2807#define RCC_STM500CFGR_STM500LPEN BIT(2)
2808
2809/* RCC_ETRCFGR register fields */
2810#define RCC_ETRCFGR_ETREN BIT(1)
2811#define RCC_ETRCFGR_ETRLPEN BIT(2)
2812
2813/* RCC_GPIOACFGR register fields */
2814#define RCC_GPIOACFGR_GPIOARST BIT(0)
2815#define RCC_GPIOACFGR_GPIOAEN BIT(1)
2816#define RCC_GPIOACFGR_GPIOALPEN BIT(2)
2817
2818/* RCC_GPIOBCFGR register fields */
2819#define RCC_GPIOBCFGR_GPIOBRST BIT(0)
2820#define RCC_GPIOBCFGR_GPIOBEN BIT(1)
2821#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2)
2822
2823/* RCC_GPIOCCFGR register fields */
2824#define RCC_GPIOCCFGR_GPIOCRST BIT(0)
2825#define RCC_GPIOCCFGR_GPIOCEN BIT(1)
2826#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2)
2827
2828/* RCC_GPIODCFGR register fields */
2829#define RCC_GPIODCFGR_GPIODRST BIT(0)
2830#define RCC_GPIODCFGR_GPIODEN BIT(1)
2831#define RCC_GPIODCFGR_GPIODLPEN BIT(2)
2832
2833/* RCC_GPIOECFGR register fields */
2834#define RCC_GPIOECFGR_GPIOERST BIT(0)
2835#define RCC_GPIOECFGR_GPIOEEN BIT(1)
2836#define RCC_GPIOECFGR_GPIOELPEN BIT(2)
2837
2838/* RCC_GPIOFCFGR register fields */
2839#define RCC_GPIOFCFGR_GPIOFRST BIT(0)
2840#define RCC_GPIOFCFGR_GPIOFEN BIT(1)
2841#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2)
2842
2843/* RCC_GPIOGCFGR register fields */
2844#define RCC_GPIOGCFGR_GPIOGRST BIT(0)
2845#define RCC_GPIOGCFGR_GPIOGEN BIT(1)
2846#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2)
2847
2848/* RCC_GPIOHCFGR register fields */
2849#define RCC_GPIOHCFGR_GPIOHRST BIT(0)
2850#define RCC_GPIOHCFGR_GPIOHEN BIT(1)
2851#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2)
2852
2853/* RCC_GPIOICFGR register fields */
2854#define RCC_GPIOICFGR_GPIOIRST BIT(0)
2855#define RCC_GPIOICFGR_GPIOIEN BIT(1)
2856#define RCC_GPIOICFGR_GPIOILPEN BIT(2)
2857
2858/* RCC_GPIOJCFGR register fields */
2859#define RCC_GPIOJCFGR_GPIOJRST BIT(0)
2860#define RCC_GPIOJCFGR_GPIOJEN BIT(1)
2861#define RCC_GPIOJCFGR_GPIOJLPEN BIT(2)
2862
2863/* RCC_GPIOKCFGR register fields */
2864#define RCC_GPIOKCFGR_GPIOKRST BIT(0)
2865#define RCC_GPIOKCFGR_GPIOKEN BIT(1)
2866#define RCC_GPIOKCFGR_GPIOKLPEN BIT(2)
2867
2868/* RCC_GPIOZCFGR register fields */
2869#define RCC_GPIOZCFGR_GPIOZRST BIT(0)
2870#define RCC_GPIOZCFGR_GPIOZEN BIT(1)
2871#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2)
2872#define RCC_GPIOZCFGR_GPIOZAMEN BIT(3)
2873
2874/* RCC_GPIOxCFGR register fields */
2875#define RCC_GPIOxCFGR_GPIOxRST BIT(0)
2876#define RCC_GPIOxCFGR_GPIOxEN BIT(1)
2877#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2)
2878#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3)
2879
2880/* RCC_HPDMA1CFGR register fields */
2881#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0)
2882#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1)
2883#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2)
2884
2885/* RCC_HPDMA2CFGR register fields */
2886#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0)
2887#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1)
2888#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2)
2889
2890/* RCC_HPDMA3CFGR register fields */
2891#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0)
2892#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1)
2893#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2)
2894
2895/* RCC_HPDMAxCFGR register fields */
2896#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0)
2897#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1)
2898#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2)
2899
2900/* RCC_LPDMACFGR register fields */
2901#define RCC_LPDMACFGR_LPDMARST BIT(0)
2902#define RCC_LPDMACFGR_LPDMAEN BIT(1)
2903#define RCC_LPDMACFGR_LPDMALPEN BIT(2)
2904#define RCC_LPDMACFGR_LPDMAAMEN BIT(3)
2905
2906/* RCC_HSEMCFGR register fields */
2907#define RCC_HSEMCFGR_HSEMRST BIT(0)
2908#define RCC_HSEMCFGR_HSEMEN BIT(1)
2909#define RCC_HSEMCFGR_HSEMLPEN BIT(2)
2910#define RCC_HSEMCFGR_HSEMAMEN BIT(3)
2911
2912/* RCC_IPCC1CFGR register fields */
2913#define RCC_IPCC1CFGR_IPCC1RST BIT(0)
2914#define RCC_IPCC1CFGR_IPCC1EN BIT(1)
2915#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2)
2916
2917/* RCC_IPCC2CFGR register fields */
2918#define RCC_IPCC2CFGR_IPCC2RST BIT(0)
2919#define RCC_IPCC2CFGR_IPCC2EN BIT(1)
2920#define RCC_IPCC2CFGR_IPCC2LPEN BIT(2)
2921#define RCC_IPCC2CFGR_IPCC2AMEN BIT(3)
2922
2923/* RCC_RTCCFGR register fields */
2924#define RCC_RTCCFGR_RTCEN BIT(1)
2925#define RCC_RTCCFGR_RTCLPEN BIT(2)
2926#define RCC_RTCCFGR_RTCAMEN BIT(3)
2927
2928/* RCC_SYSCPU1CFGR register fields */
2929#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1)
2930#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2)
2931
2932/* RCC_BSECCFGR register fields */
2933#define RCC_BSECCFGR_BSECEN BIT(1)
2934#define RCC_BSECCFGR_BSECLPEN BIT(2)
2935
2936/* RCC_IS2MCFGR register fields */
2937#define RCC_IS2MCFGR_IS2MRST BIT(0)
2938#define RCC_IS2MCFGR_IS2MEN BIT(1)
2939#define RCC_IS2MCFGR_IS2MLPEN BIT(2)
2940
2941/* RCC_PLL2CFGR1 register fields */
2942#define RCC_PLL2CFGR1_SSMODRST BIT(0)
2943#define RCC_PLL2CFGR1_PLLEN BIT(8)
2944#define RCC_PLL2CFGR1_PLLRDY BIT(24)
2945#define RCC_PLL2CFGR1_CKREFST BIT(28)
2946
2947/* RCC_PLL2CFGR2 register fields */
2948#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
2949#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0
2950#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16)
2951#define RCC_PLL2CFGR2_FBDIV_SHIFT 16
2952
2953/* RCC_PLL2CFGR3 register fields */
2954#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0)
2955#define RCC_PLL2CFGR3_FRACIN_SHIFT 0
2956#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24)
2957#define RCC_PLL2CFGR3_DACEN BIT(25)
2958#define RCC_PLL2CFGR3_SSCGDIS BIT(26)
2959
2960/* RCC_PLL2CFGR4 register fields */
2961#define RCC_PLL2CFGR4_DSMEN BIT(8)
2962#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9)
2963#define RCC_PLL2CFGR4_BYPASS BIT(10)
2964
2965/* RCC_PLL2CFGR5 register fields */
2966#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
2967#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0
2968#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16)
2969#define RCC_PLL2CFGR5_SPREAD_SHIFT 16
2970
2971/* RCC_PLL2CFGR6 register fields */
2972#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
2973#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0
2974
2975/* RCC_PLL2CFGR7 register fields */
2976#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
2977#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0
2978
2979/* RCC_PLL3CFGR1 register fields */
2980#define RCC_PLL3CFGR1_SSMODRST BIT(0)
2981#define RCC_PLL3CFGR1_PLLEN BIT(8)
2982#define RCC_PLL3CFGR1_PLLRDY BIT(24)
2983#define RCC_PLL3CFGR1_CKREFST BIT(28)
2984
2985/* RCC_PLL3CFGR2 register fields */
2986#define RCC_PLL3CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
2987#define RCC_PLL3CFGR2_FREFDIV_SHIFT 0
2988#define RCC_PLL3CFGR2_FBDIV_MASK GENMASK_32(27, 16)
2989#define RCC_PLL3CFGR2_FBDIV_SHIFT 16
2990
2991/* RCC_PLL3CFGR3 register fields */
2992#define RCC_PLL3CFGR3_FRACIN_MASK GENMASK_32(23, 0)
2993#define RCC_PLL3CFGR3_FRACIN_SHIFT 0
2994#define RCC_PLL3CFGR3_DOWNSPREAD BIT(24)
2995#define RCC_PLL3CFGR3_DACEN BIT(25)
2996#define RCC_PLL3CFGR3_SSCGDIS BIT(26)
2997
2998/* RCC_PLL3CFGR4 register fields */
2999#define RCC_PLL3CFGR4_DSMEN BIT(8)
3000#define RCC_PLL3CFGR4_FOUTPOSTDIVEN BIT(9)
3001#define RCC_PLL3CFGR4_BYPASS BIT(10)
3002
3003/* RCC_PLL3CFGR5 register fields */
3004#define RCC_PLL3CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
3005#define RCC_PLL3CFGR5_DIVVAL_SHIFT 0
3006#define RCC_PLL3CFGR5_SPREAD_MASK GENMASK_32(20, 16)
3007#define RCC_PLL3CFGR5_SPREAD_SHIFT 16
3008
3009/* RCC_PLL3CFGR6 register fields */
3010#define RCC_PLL3CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
3011#define RCC_PLL3CFGR6_POSTDIV1_SHIFT 0
3012
3013/* RCC_PLL3CFGR7 register fields */
3014#define RCC_PLL3CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
3015#define RCC_PLL3CFGR7_POSTDIV2_SHIFT 0
3016
3017/* RCC_PLLxCFGR1 register fields */
3018#define RCC_PLLxCFGR1_SSMODRST BIT(0)
3019#define RCC_PLLxCFGR1_PLLEN BIT(8)
3020#define RCC_PLLxCFGR1_PLLRDY BIT(24)
3021#define RCC_PLLxCFGR1_CKREFST BIT(28)
3022
3023/* RCC_PLLxCFGR2 register fields */
3024#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
3025#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
3026#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
3027#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
3028
3029/* RCC_PLLxCFGR3 register fields */
3030#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
3031#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
3032#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
3033#define RCC_PLLxCFGR3_DACEN BIT(25)
3034#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
3035
3036/* RCC_PLLxCFGR4 register fields */
3037#define RCC_PLLxCFGR4_DSMEN BIT(8)
3038#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
3039#define RCC_PLLxCFGR4_BYPASS BIT(10)
3040
3041/* RCC_PLLxCFGR5 register fields */
3042#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
3043#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
3044#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
3045#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
3046
3047/* RCC_PLLxCFGR6 register fields */
3048#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
3049#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
3050
3051/* RCC_PLLxCFGR7 register fields */
3052#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
3053#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
3054
3055/* RCC_HSIFMONCR register fields */
3056#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0)
3057#define RCC_HSIFMONCR_HSIREF_SHIFT 0
3058#define RCC_HSIFMONCR_HSIMONEN BIT(15)
3059#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16)
3060#define RCC_HSIFMONCR_HSIDEV_SHIFT 16
3061#define RCC_HSIFMONCR_HSIMONIE BIT(30)
3062#define RCC_HSIFMONCR_HSIMONF BIT(31)
3063
3064/* RCC_HSIFVALR register fields */
3065#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0)
3066#define RCC_HSIFVALR_HSIVAL_SHIFT 0
3067
3068/* RCC_TIM1CFGR register fields */
3069#define RCC_TIM1CFGR_TIM1RST BIT(0)
3070#define RCC_TIM1CFGR_TIM1EN BIT(1)
3071#define RCC_TIM1CFGR_TIM1LPEN BIT(2)
3072
3073/* RCC_TIM2CFGR register fields */
3074#define RCC_TIM2CFGR_TIM2RST BIT(0)
3075#define RCC_TIM2CFGR_TIM2EN BIT(1)
3076#define RCC_TIM2CFGR_TIM2LPEN BIT(2)
3077
3078/* RCC_TIM3CFGR register fields */
3079#define RCC_TIM3CFGR_TIM3RST BIT(0)
3080#define RCC_TIM3CFGR_TIM3EN BIT(1)
3081#define RCC_TIM3CFGR_TIM3LPEN BIT(2)
3082
3083/* RCC_TIM4CFGR register fields */
3084#define RCC_TIM4CFGR_TIM4RST BIT(0)
3085#define RCC_TIM4CFGR_TIM4EN BIT(1)
3086#define RCC_TIM4CFGR_TIM4LPEN BIT(2)
3087
3088/* RCC_TIM5CFGR register fields */
3089#define RCC_TIM5CFGR_TIM5RST BIT(0)
3090#define RCC_TIM5CFGR_TIM5EN BIT(1)
3091#define RCC_TIM5CFGR_TIM5LPEN BIT(2)
3092
3093/* RCC_TIM6CFGR register fields */
3094#define RCC_TIM6CFGR_TIM6RST BIT(0)
3095#define RCC_TIM6CFGR_TIM6EN BIT(1)
3096#define RCC_TIM6CFGR_TIM6LPEN BIT(2)
3097
3098/* RCC_TIM7CFGR register fields */
3099#define RCC_TIM7CFGR_TIM7RST BIT(0)
3100#define RCC_TIM7CFGR_TIM7EN BIT(1)
3101#define RCC_TIM7CFGR_TIM7LPEN BIT(2)
3102
3103/* RCC_TIM8CFGR register fields */
3104#define RCC_TIM8CFGR_TIM8RST BIT(0)
3105#define RCC_TIM8CFGR_TIM8EN BIT(1)
3106#define RCC_TIM8CFGR_TIM8LPEN BIT(2)
3107
3108/* RCC_TIM10CFGR register fields */
3109#define RCC_TIM10CFGR_TIM10RST BIT(0)
3110#define RCC_TIM10CFGR_TIM10EN BIT(1)
3111#define RCC_TIM10CFGR_TIM10LPEN BIT(2)
3112
3113/* RCC_TIM11CFGR register fields */
3114#define RCC_TIM11CFGR_TIM11RST BIT(0)
3115#define RCC_TIM11CFGR_TIM11EN BIT(1)
3116#define RCC_TIM11CFGR_TIM11LPEN BIT(2)
3117
3118/* RCC_TIM12CFGR register fields */
3119#define RCC_TIM12CFGR_TIM12RST BIT(0)
3120#define RCC_TIM12CFGR_TIM12EN BIT(1)
3121#define RCC_TIM12CFGR_TIM12LPEN BIT(2)
3122
3123/* RCC_TIM13CFGR register fields */
3124#define RCC_TIM13CFGR_TIM13RST BIT(0)
3125#define RCC_TIM13CFGR_TIM13EN BIT(1)
3126#define RCC_TIM13CFGR_TIM13LPEN BIT(2)
3127
3128/* RCC_TIM14CFGR register fields */
3129#define RCC_TIM14CFGR_TIM14RST BIT(0)
3130#define RCC_TIM14CFGR_TIM14EN BIT(1)
3131#define RCC_TIM14CFGR_TIM14LPEN BIT(2)
3132
3133/* RCC_TIM15CFGR register fields */
3134#define RCC_TIM15CFGR_TIM15RST BIT(0)
3135#define RCC_TIM15CFGR_TIM15EN BIT(1)
3136#define RCC_TIM15CFGR_TIM15LPEN BIT(2)
3137
3138/* RCC_TIM16CFGR register fields */
3139#define RCC_TIM16CFGR_TIM16RST BIT(0)
3140#define RCC_TIM16CFGR_TIM16EN BIT(1)
3141#define RCC_TIM16CFGR_TIM16LPEN BIT(2)
3142
3143/* RCC_TIM17CFGR register fields */
3144#define RCC_TIM17CFGR_TIM17RST BIT(0)
3145#define RCC_TIM17CFGR_TIM17EN BIT(1)
3146#define RCC_TIM17CFGR_TIM17LPEN BIT(2)
3147
3148/* RCC_TIM20CFGR register fields */
3149#define RCC_TIM20CFGR_TIM20RST BIT(0)
3150#define RCC_TIM20CFGR_TIM20EN BIT(1)
3151#define RCC_TIM20CFGR_TIM20LPEN BIT(2)
3152
3153/* RCC_LPTIM1CFGR register fields */
3154#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0)
3155#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1)
3156#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2)
3157
3158/* RCC_LPTIM2CFGR register fields */
3159#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0)
3160#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1)
3161#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2)
3162
3163/* RCC_LPTIM3CFGR register fields */
3164#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0)
3165#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1)
3166#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2)
3167#define RCC_LPTIM3CFGR_LPTIM3AMEN BIT(3)
3168
3169/* RCC_LPTIM4CFGR register fields */
3170#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0)
3171#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1)
3172#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2)
3173#define RCC_LPTIM4CFGR_LPTIM4AMEN BIT(3)
3174
3175/* RCC_LPTIM5CFGR register fields */
3176#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0)
3177#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1)
3178#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2)
3179#define RCC_LPTIM5CFGR_LPTIM5AMEN BIT(3)
3180
3181/* RCC_LPTIMxCFGR register fields */
3182#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0)
3183#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1)
3184#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2)
3185#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3)
3186
3187/* RCC_SPI1CFGR register fields */
3188#define RCC_SPI1CFGR_SPI1RST BIT(0)
3189#define RCC_SPI1CFGR_SPI1EN BIT(1)
3190#define RCC_SPI1CFGR_SPI1LPEN BIT(2)
3191
3192/* RCC_SPI2CFGR register fields */
3193#define RCC_SPI2CFGR_SPI2RST BIT(0)
3194#define RCC_SPI2CFGR_SPI2EN BIT(1)
3195#define RCC_SPI2CFGR_SPI2LPEN BIT(2)
3196
3197/* RCC_SPI3CFGR register fields */
3198#define RCC_SPI3CFGR_SPI3RST BIT(0)
3199#define RCC_SPI3CFGR_SPI3EN BIT(1)
3200#define RCC_SPI3CFGR_SPI3LPEN BIT(2)
3201
3202/* RCC_SPI4CFGR register fields */
3203#define RCC_SPI4CFGR_SPI4RST BIT(0)
3204#define RCC_SPI4CFGR_SPI4EN BIT(1)
3205#define RCC_SPI4CFGR_SPI4LPEN BIT(2)
3206
3207/* RCC_SPI5CFGR register fields */
3208#define RCC_SPI5CFGR_SPI5RST BIT(0)
3209#define RCC_SPI5CFGR_SPI5EN BIT(1)
3210#define RCC_SPI5CFGR_SPI5LPEN BIT(2)
3211
3212/* RCC_SPI6CFGR register fields */
3213#define RCC_SPI6CFGR_SPI6RST BIT(0)
3214#define RCC_SPI6CFGR_SPI6EN BIT(1)
3215#define RCC_SPI6CFGR_SPI6LPEN BIT(2)
3216
3217/* RCC_SPI7CFGR register fields */
3218#define RCC_SPI7CFGR_SPI7RST BIT(0)
3219#define RCC_SPI7CFGR_SPI7EN BIT(1)
3220#define RCC_SPI7CFGR_SPI7LPEN BIT(2)
3221
3222/* RCC_SPI8CFGR register fields */
3223#define RCC_SPI8CFGR_SPI8RST BIT(0)
3224#define RCC_SPI8CFGR_SPI8EN BIT(1)
3225#define RCC_SPI8CFGR_SPI8LPEN BIT(2)
3226#define RCC_SPI8CFGR_SPI8AMEN BIT(3)
3227
3228/* RCC_SPIxCFGR register fields */
3229#define RCC_SPIxCFGR_SPIxRST BIT(0)
3230#define RCC_SPIxCFGR_SPIxEN BIT(1)
3231#define RCC_SPIxCFGR_SPIxLPEN BIT(2)
3232#define RCC_SPIxCFGR_SPIxAMEN BIT(3)
3233
3234/* RCC_SPDIFRXCFGR register fields */
3235#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0)
3236#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1)
3237#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2)
3238
3239/* RCC_USART1CFGR register fields */
3240#define RCC_USART1CFGR_USART1RST BIT(0)
3241#define RCC_USART1CFGR_USART1EN BIT(1)
3242#define RCC_USART1CFGR_USART1LPEN BIT(2)
3243
3244/* RCC_USART2CFGR register fields */
3245#define RCC_USART2CFGR_USART2RST BIT(0)
3246#define RCC_USART2CFGR_USART2EN BIT(1)
3247#define RCC_USART2CFGR_USART2LPEN BIT(2)
3248
3249/* RCC_USART3CFGR register fields */
3250#define RCC_USART3CFGR_USART3RST BIT(0)
3251#define RCC_USART3CFGR_USART3EN BIT(1)
3252#define RCC_USART3CFGR_USART3LPEN BIT(2)
3253
3254/* RCC_UART4CFGR register fields */
3255#define RCC_UART4CFGR_UART4RST BIT(0)
3256#define RCC_UART4CFGR_UART4EN BIT(1)
3257#define RCC_UART4CFGR_UART4LPEN BIT(2)
3258
3259/* RCC_UART5CFGR register fields */
3260#define RCC_UART5CFGR_UART5RST BIT(0)
3261#define RCC_UART5CFGR_UART5EN BIT(1)
3262#define RCC_UART5CFGR_UART5LPEN BIT(2)
3263
3264/* RCC_USART6CFGR register fields */
3265#define RCC_USART6CFGR_USART6RST BIT(0)
3266#define RCC_USART6CFGR_USART6EN BIT(1)
3267#define RCC_USART6CFGR_USART6LPEN BIT(2)
3268
3269/* RCC_UART7CFGR register fields */
3270#define RCC_UART7CFGR_UART7RST BIT(0)
3271#define RCC_UART7CFGR_UART7EN BIT(1)
3272#define RCC_UART7CFGR_UART7LPEN BIT(2)
3273
3274/* RCC_UART8CFGR register fields */
3275#define RCC_UART8CFGR_UART8RST BIT(0)
3276#define RCC_UART8CFGR_UART8EN BIT(1)
3277#define RCC_UART8CFGR_UART8LPEN BIT(2)
3278
3279/* RCC_UART9CFGR register fields */
3280#define RCC_UART9CFGR_UART9RST BIT(0)
3281#define RCC_UART9CFGR_UART9EN BIT(1)
3282#define RCC_UART9CFGR_UART9LPEN BIT(2)
3283
3284/* RCC_USARTxCFGR register fields */
3285#define RCC_USARTxCFGR_USARTxRST BIT(0)
3286#define RCC_USARTxCFGR_USARTxEN BIT(1)
3287#define RCC_USARTxCFGR_USARTxLPEN BIT(2)
3288
3289/* RCC_UARTxCFGR register fields */
3290#define RCC_UARTxCFGR_UARTxRST BIT(0)
3291#define RCC_UARTxCFGR_UARTxEN BIT(1)
3292#define RCC_UARTxCFGR_UARTxLPEN BIT(2)
3293
3294/* RCC_LPUART1CFGR register fields */
3295#define RCC_LPUART1CFGR_LPUART1RST BIT(0)
3296#define RCC_LPUART1CFGR_LPUART1EN BIT(1)
3297#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2)
3298#define RCC_LPUART1CFGR_LPUART1AMEN BIT(3)
3299
3300/* RCC_I2C1CFGR register fields */
3301#define RCC_I2C1CFGR_I2C1RST BIT(0)
3302#define RCC_I2C1CFGR_I2C1EN BIT(1)
3303#define RCC_I2C1CFGR_I2C1LPEN BIT(2)
3304
3305/* RCC_I2C2CFGR register fields */
3306#define RCC_I2C2CFGR_I2C2RST BIT(0)
3307#define RCC_I2C2CFGR_I2C2EN BIT(1)
3308#define RCC_I2C2CFGR_I2C2LPEN BIT(2)
3309
3310/* RCC_I2C3CFGR register fields */
3311#define RCC_I2C3CFGR_I2C3RST BIT(0)
3312#define RCC_I2C3CFGR_I2C3EN BIT(1)
3313#define RCC_I2C3CFGR_I2C3LPEN BIT(2)
3314
3315/* RCC_I2C4CFGR register fields */
3316#define RCC_I2C4CFGR_I2C4RST BIT(0)
3317#define RCC_I2C4CFGR_I2C4EN BIT(1)
3318#define RCC_I2C4CFGR_I2C4LPEN BIT(2)
3319
3320/* RCC_I2C5CFGR register fields */
3321#define RCC_I2C5CFGR_I2C5RST BIT(0)
3322#define RCC_I2C5CFGR_I2C5EN BIT(1)
3323#define RCC_I2C5CFGR_I2C5LPEN BIT(2)
3324
3325/* RCC_I2C6CFGR register fields */
3326#define RCC_I2C6CFGR_I2C6RST BIT(0)
3327#define RCC_I2C6CFGR_I2C6EN BIT(1)
3328#define RCC_I2C6CFGR_I2C6LPEN BIT(2)
3329
3330/* RCC_I2C7CFGR register fields */
3331#define RCC_I2C7CFGR_I2C7RST BIT(0)
3332#define RCC_I2C7CFGR_I2C7EN BIT(1)
3333#define RCC_I2C7CFGR_I2C7LPEN BIT(2)
3334
3335/* RCC_I2C8CFGR register fields */
3336#define RCC_I2C8CFGR_I2C8RST BIT(0)
3337#define RCC_I2C8CFGR_I2C8EN BIT(1)
3338#define RCC_I2C8CFGR_I2C8LPEN BIT(2)
3339#define RCC_I2C8CFGR_I2C8AMEN BIT(3)
3340
3341/* RCC_I2CxCFGR register fields */
3342#define RCC_I2CxCFGR_I2CxRST BIT(0)
3343#define RCC_I2CxCFGR_I2CxEN BIT(1)
3344#define RCC_I2CxCFGR_I2CxLPEN BIT(2)
3345#define RCC_I2CxCFGR_I2CxAMEN BIT(3)
3346
3347/* RCC_SAI1CFGR register fields */
3348#define RCC_SAI1CFGR_SAI1RST BIT(0)
3349#define RCC_SAI1CFGR_SAI1EN BIT(1)
3350#define RCC_SAI1CFGR_SAI1LPEN BIT(2)
3351
3352/* RCC_SAI2CFGR register fields */
3353#define RCC_SAI2CFGR_SAI2RST BIT(0)
3354#define RCC_SAI2CFGR_SAI2EN BIT(1)
3355#define RCC_SAI2CFGR_SAI2LPEN BIT(2)
3356
3357/* RCC_SAI3CFGR register fields */
3358#define RCC_SAI3CFGR_SAI3RST BIT(0)
3359#define RCC_SAI3CFGR_SAI3EN BIT(1)
3360#define RCC_SAI3CFGR_SAI3LPEN BIT(2)
3361
3362/* RCC_SAI4CFGR register fields */
3363#define RCC_SAI4CFGR_SAI4RST BIT(0)
3364#define RCC_SAI4CFGR_SAI4EN BIT(1)
3365#define RCC_SAI4CFGR_SAI4LPEN BIT(2)
3366
3367/* RCC_SAIxCFGR register fields */
3368#define RCC_SAIxCFGR_SAIxRST BIT(0)
3369#define RCC_SAIxCFGR_SAIxEN BIT(1)
3370#define RCC_SAIxCFGR_SAIxLPEN BIT(2)
3371
3372/* RCC_MDF1CFGR register fields */
3373#define RCC_MDF1CFGR_MDF1RST BIT(0)
3374#define RCC_MDF1CFGR_MDF1EN BIT(1)
3375#define RCC_MDF1CFGR_MDF1LPEN BIT(2)
3376
3377/* RCC_ADF1CFGR register fields */
3378#define RCC_ADF1CFGR_ADF1RST BIT(0)
3379#define RCC_ADF1CFGR_ADF1EN BIT(1)
3380#define RCC_ADF1CFGR_ADF1LPEN BIT(2)
3381#define RCC_ADF1CFGR_ADF1AMEN BIT(3)
3382
3383/* RCC_FDCANCFGR register fields */
3384#define RCC_FDCANCFGR_FDCANRST BIT(0)
3385#define RCC_FDCANCFGR_FDCANEN BIT(1)
3386#define RCC_FDCANCFGR_FDCANLPEN BIT(2)
3387
3388/* RCC_HDPCFGR register fields */
3389#define RCC_HDPCFGR_HDPRST BIT(0)
3390#define RCC_HDPCFGR_HDPEN BIT(1)
3391
3392/* RCC_ADC12CFGR register fields */
3393#define RCC_ADC12CFGR_ADC12RST BIT(0)
3394#define RCC_ADC12CFGR_ADC12EN BIT(1)
3395#define RCC_ADC12CFGR_ADC12LPEN BIT(2)
3396#define RCC_ADC12CFGR_ADC12KERSEL BIT(12)
3397
3398/* RCC_ADC3CFGR register fields */
3399#define RCC_ADC3CFGR_ADC3RST BIT(0)
3400#define RCC_ADC3CFGR_ADC3EN BIT(1)
3401#define RCC_ADC3CFGR_ADC3LPEN BIT(2)
3402#define RCC_ADC3CFGR_ADC3KERSEL_MASK GENMASK_32(13, 12)
3403#define RCC_ADC3CFGR_ADC3KERSEL_SHIFT 12
3404
3405/* RCC_ETH1CFGR register fields */
3406#define RCC_ETH1CFGR_ETH1RST BIT(0)
3407#define RCC_ETH1CFGR_ETH1MACEN BIT(1)
3408#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2)
3409#define RCC_ETH1CFGR_ETH1STPEN BIT(4)
3410#define RCC_ETH1CFGR_ETH1EN BIT(5)
3411#define RCC_ETH1CFGR_ETH1LPEN BIT(6)
3412#define RCC_ETH1CFGR_ETH1TXEN BIT(8)
3413#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9)
3414#define RCC_ETH1CFGR_ETH1RXEN BIT(10)
3415#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11)
3416
3417/* RCC_ETH2CFGR register fields */
3418#define RCC_ETH2CFGR_ETH2RST BIT(0)
3419#define RCC_ETH2CFGR_ETH2MACEN BIT(1)
3420#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2)
3421#define RCC_ETH2CFGR_ETH2STPEN BIT(4)
3422#define RCC_ETH2CFGR_ETH2EN BIT(5)
3423#define RCC_ETH2CFGR_ETH2LPEN BIT(6)
3424#define RCC_ETH2CFGR_ETH2TXEN BIT(8)
3425#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9)
3426#define RCC_ETH2CFGR_ETH2RXEN BIT(10)
3427#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11)
3428
3429/* RCC_ETHxCFGR register fields */
3430#define RCC_ETHxCFGR_ETHxRST BIT(0)
3431#define RCC_ETHxCFGR_ETHxMACEN BIT(1)
3432#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2)
3433#define RCC_ETHxCFGR_ETHxSTPEN BIT(4)
3434#define RCC_ETHxCFGR_ETHxEN BIT(5)
3435#define RCC_ETHxCFGR_ETHxLPEN BIT(6)
3436#define RCC_ETHxCFGR_ETHxTXEN BIT(8)
3437#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9)
3438#define RCC_ETHxCFGR_ETHxRXEN BIT(10)
3439#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11)
3440
3441/* RCC_USB2CFGR register fields */
3442#define RCC_USB2CFGR_USB2RST BIT(0)
3443#define RCC_USB2CFGR_USB2EN BIT(1)
3444#define RCC_USB2CFGR_USB2LPEN BIT(2)
3445#define RCC_USB2CFGR_USB2STPEN BIT(4)
3446
3447/* RCC_USB2PHY1CFGR register fields */
3448#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0)
3449#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1)
3450#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2)
3451#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4)
3452#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15)
3453
3454/* RCC_USB2PHY2CFGR register fields */
3455#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0)
3456#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1)
3457#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2)
3458#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4)
3459#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15)
3460
3461/* RCC_USB2PHYxCFGR register fields */
3462#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0)
3463#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1)
3464#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2)
3465#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4)
3466#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15)
3467
Gabriel Fernandezbcd95062022-04-20 10:08:49 +02003468/* RCC_USB3DRCFGR register fields */
3469#define RCC_USB3DRCFGR_USB3DRRST BIT(0)
3470#define RCC_USB3DRCFGR_USB3DREN BIT(1)
3471#define RCC_USB3DRCFGR_USB3DRLPEN BIT(2)
3472#define RCC_USB3DRCFGR_USB3DRSTPEN BIT(4)
Yann Gautier740ca302023-06-14 18:00:58 +02003473
3474/* RCC_USB3PCIEPHYCFGR register fields */
3475#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0)
3476#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYEN BIT(1)
3477#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYLPEN BIT(2)
3478#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYSTPEN BIT(4)
3479#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYCKREFSEL BIT(15)
3480
3481/* RCC_PCIECFGR register fields */
3482#define RCC_PCIECFGR_PCIERST BIT(0)
3483#define RCC_PCIECFGR_PCIEEN BIT(1)
3484#define RCC_PCIECFGR_PCIELPEN BIT(2)
3485#define RCC_PCIECFGR_PCIESTPEN BIT(4)
3486
3487/* RCC_USBTCCFGR register fields */
3488#define RCC_USBTCCFGR_USBTCRST BIT(0)
3489#define RCC_USBTCCFGR_USBTCEN BIT(1)
3490#define RCC_USBTCCFGR_USBTCLPEN BIT(2)
3491
3492/* RCC_ETHSWCFGR register fields */
3493#define RCC_ETHSWCFGR_ETHSWRST BIT(0)
3494#define RCC_ETHSWCFGR_ETHSWMACEN BIT(1)
3495#define RCC_ETHSWCFGR_ETHSWMACLPEN BIT(2)
3496#define RCC_ETHSWCFGR_ETHSWEN BIT(5)
3497#define RCC_ETHSWCFGR_ETHSWLPEN BIT(6)
3498#define RCC_ETHSWCFGR_ETHSWREFEN BIT(21)
3499#define RCC_ETHSWCFGR_ETHSWREFLPEN BIT(22)
3500
3501/* RCC_ETHSWACMCFGR register fields */
3502#define RCC_ETHSWACMCFGR_ETHSWACMEN BIT(1)
3503#define RCC_ETHSWACMCFGR_ETHSWACMLPEN BIT(2)
3504
3505/* RCC_ETHSWACMMSGCFGR register fields */
3506#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGEN BIT(1)
3507#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGLPEN BIT(2)
3508
3509/* RCC_STGENCFGR register fields */
3510#define RCC_STGENCFGR_STGENEN BIT(1)
3511#define RCC_STGENCFGR_STGENLPEN BIT(2)
3512#define RCC_STGENCFGR_STGENSTPEN BIT(4)
3513
3514/* RCC_SDMMC1CFGR register fields */
3515#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0)
3516#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1)
3517#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2)
3518#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16)
3519
3520/* RCC_SDMMC2CFGR register fields */
3521#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0)
3522#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1)
3523#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2)
3524#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16)
3525
3526/* RCC_SDMMC3CFGR register fields */
3527#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0)
3528#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1)
3529#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2)
3530#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16)
3531
3532/* RCC_SDMMCxCFGR register fields */
3533#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0)
3534#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1)
3535#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2)
3536#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16)
3537
3538/* RCC_GPUCFGR register fields */
3539#define RCC_GPUCFGR_GPURST BIT(0)
3540#define RCC_GPUCFGR_GPUEN BIT(1)
3541#define RCC_GPUCFGR_GPULPEN BIT(2)
3542
3543/* RCC_LTDCCFGR register fields */
3544#define RCC_LTDCCFGR_LTDCRST BIT(0)
3545#define RCC_LTDCCFGR_LTDCEN BIT(1)
3546#define RCC_LTDCCFGR_LTDCLPEN BIT(2)
3547
3548/* RCC_DSICFGR register fields */
3549#define RCC_DSICFGR_DSIRST BIT(0)
3550#define RCC_DSICFGR_DSIEN BIT(1)
3551#define RCC_DSICFGR_DSILPEN BIT(2)
3552#define RCC_DSICFGR_DSIBLSEL BIT(12)
3553#define RCC_DSICFGR_DSIPHYCKREFSEL BIT(15)
3554
3555/* RCC_LVDSCFGR register fields */
3556#define RCC_LVDSCFGR_LVDSRST BIT(0)
3557#define RCC_LVDSCFGR_LVDSEN BIT(1)
3558#define RCC_LVDSCFGR_LVDSLPEN BIT(2)
3559#define RCC_LVDSCFGR_LVDSPHYCKREFSEL BIT(15)
3560
3561/* RCC_CSI2CFGR register fields */
3562#define RCC_CSI2CFGR_CSI2RST BIT(0)
3563#define RCC_CSI2CFGR_CSI2EN BIT(1)
3564#define RCC_CSI2CFGR_CSI2LPEN BIT(2)
3565
3566/* RCC_DCMIPPCFGR register fields */
3567#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0)
3568#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1)
3569#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2)
3570
3571/* RCC_CCICFGR register fields */
3572#define RCC_CCICFGR_CCIRST BIT(0)
3573#define RCC_CCICFGR_CCIEN BIT(1)
3574#define RCC_CCICFGR_CCILPEN BIT(2)
3575
3576/* RCC_VDECCFGR register fields */
3577#define RCC_VDECCFGR_VDECRST BIT(0)
3578#define RCC_VDECCFGR_VDECEN BIT(1)
3579#define RCC_VDECCFGR_VDECLPEN BIT(2)
3580
3581/* RCC_VENCCFGR register fields */
3582#define RCC_VENCCFGR_VENCRST BIT(0)
3583#define RCC_VENCCFGR_VENCEN BIT(1)
3584#define RCC_VENCCFGR_VENCLPEN BIT(2)
3585
3586/* RCC_RNGCFGR register fields */
3587#define RCC_RNGCFGR_RNGRST BIT(0)
3588#define RCC_RNGCFGR_RNGEN BIT(1)
3589#define RCC_RNGCFGR_RNGLPEN BIT(2)
3590
3591/* RCC_PKACFGR register fields */
3592#define RCC_PKACFGR_PKARST BIT(0)
3593#define RCC_PKACFGR_PKAEN BIT(1)
3594#define RCC_PKACFGR_PKALPEN BIT(2)
3595
3596/* RCC_SAESCFGR register fields */
3597#define RCC_SAESCFGR_SAESRST BIT(0)
3598#define RCC_SAESCFGR_SAESEN BIT(1)
3599#define RCC_SAESCFGR_SAESLPEN BIT(2)
3600
3601/* RCC_HASHCFGR register fields */
3602#define RCC_HASHCFGR_HASHRST BIT(0)
3603#define RCC_HASHCFGR_HASHEN BIT(1)
3604#define RCC_HASHCFGR_HASHLPEN BIT(2)
3605
3606/* RCC_CRYP1CFGR register fields */
3607#define RCC_CRYP1CFGR_CRYP1RST BIT(0)
3608#define RCC_CRYP1CFGR_CRYP1EN BIT(1)
3609#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2)
3610
3611/* RCC_CRYP2CFGR register fields */
3612#define RCC_CRYP2CFGR_CRYP2RST BIT(0)
3613#define RCC_CRYP2CFGR_CRYP2EN BIT(1)
3614#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2)
3615
3616/* RCC_CRYPxCFGR register fields */
3617#define RCC_CRYPxCFGR_CRYPxRST BIT(0)
3618#define RCC_CRYPxCFGR_CRYPxEN BIT(1)
3619#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2)
3620
3621/* RCC_IWDG1CFGR register fields */
3622#define RCC_IWDG1CFGR_IWDG1EN BIT(1)
3623#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2)
3624
3625/* RCC_IWDG2CFGR register fields */
3626#define RCC_IWDG2CFGR_IWDG2EN BIT(1)
3627#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2)
3628
3629/* RCC_IWDG3CFGR register fields */
3630#define RCC_IWDG3CFGR_IWDG3EN BIT(1)
3631#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2)
3632
3633/* RCC_IWDG4CFGR register fields */
3634#define RCC_IWDG4CFGR_IWDG4EN BIT(1)
3635#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2)
3636
3637/* RCC_IWDGxCFGR register fields */
3638#define RCC_IWDGxCFGR_IWDGxEN BIT(1)
3639#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2)
3640
3641/* RCC_IWDG5CFGR register fields */
3642#define RCC_IWDG5CFGR_IWDG5EN BIT(1)
3643#define RCC_IWDG5CFGR_IWDG5LPEN BIT(2)
3644#define RCC_IWDG5CFGR_IWDG5AMEN BIT(3)
3645
3646/* RCC_WWDG1CFGR register fields */
3647#define RCC_WWDG1CFGR_WWDG1RST BIT(0)
3648#define RCC_WWDG1CFGR_WWDG1EN BIT(1)
3649#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2)
3650
3651/* RCC_WWDG2CFGR register fields */
3652#define RCC_WWDG2CFGR_WWDG2RST BIT(0)
3653#define RCC_WWDG2CFGR_WWDG2EN BIT(1)
3654#define RCC_WWDG2CFGR_WWDG2LPEN BIT(2)
3655#define RCC_WWDG2CFGR_WWDG2AMEN BIT(3)
3656
Yann Gautier740ca302023-06-14 18:00:58 +02003657/* RCC_VREFCFGR register fields */
3658#define RCC_VREFCFGR_VREFRST BIT(0)
3659#define RCC_VREFCFGR_VREFEN BIT(1)
3660#define RCC_VREFCFGR_VREFLPEN BIT(2)
3661
3662/* RCC_TMPSENSCFGR register fields */
3663#define RCC_TMPSENSCFGR_TMPSENSRST BIT(0)
3664#define RCC_TMPSENSCFGR_TMPSENSEN BIT(1)
3665#define RCC_TMPSENSCFGR_TMPSENSLPEN BIT(2)
3666#define RCC_TMPSENSCFGR_TMPSENSKERSEL_MASK GENMASK_32(13, 12)
3667#define RCC_TMPSENSCFGR_TMPSENSKERSEL_SHIFT 12
3668
3669/* RCC_CRCCFGR register fields */
3670#define RCC_CRCCFGR_CRCRST BIT(0)
3671#define RCC_CRCCFGR_CRCEN BIT(1)
3672#define RCC_CRCCFGR_CRCLPEN BIT(2)
3673
3674/* RCC_SERCCFGR register fields */
3675#define RCC_SERCCFGR_SERCRST BIT(0)
3676#define RCC_SERCCFGR_SERCEN BIT(1)
3677#define RCC_SERCCFGR_SERCLPEN BIT(2)
3678
3679/* RCC_OSPIIOMCFGR register fields */
3680#define RCC_OSPIIOMCFGR_OSPIIOMRST BIT(0)
3681#define RCC_OSPIIOMCFGR_OSPIIOMEN BIT(1)
3682#define RCC_OSPIIOMCFGR_OSPIIOMLPEN BIT(2)
3683
3684/* RCC_GICV2MCFGR register fields */
3685#define RCC_GICV2MCFGR_GICV2MEN BIT(1)
3686#define RCC_GICV2MCFGR_GICV2MLPEN BIT(2)
3687
3688/* RCC_I3C1CFGR register fields */
3689#define RCC_I3C1CFGR_I3C1RST BIT(0)
3690#define RCC_I3C1CFGR_I3C1EN BIT(1)
3691#define RCC_I3C1CFGR_I3C1LPEN BIT(2)
3692
3693/* RCC_I3C2CFGR register fields */
3694#define RCC_I3C2CFGR_I3C2RST BIT(0)
3695#define RCC_I3C2CFGR_I3C2EN BIT(1)
3696#define RCC_I3C2CFGR_I3C2LPEN BIT(2)
3697
3698/* RCC_I3C3CFGR register fields */
3699#define RCC_I3C3CFGR_I3C3RST BIT(0)
3700#define RCC_I3C3CFGR_I3C3EN BIT(1)
3701#define RCC_I3C3CFGR_I3C3LPEN BIT(2)
3702
3703/* RCC_I3C4CFGR register fields */
3704#define RCC_I3C4CFGR_I3C4RST BIT(0)
3705#define RCC_I3C4CFGR_I3C4EN BIT(1)
3706#define RCC_I3C4CFGR_I3C4LPEN BIT(2)
3707#define RCC_I3C4CFGR_I3C4AMEN BIT(3)
3708
3709/* RCC_I3CxCFGR register fields */
3710#define RCC_I3CxCFGR_I3CxRST BIT(0)
3711#define RCC_I3CxCFGR_I3CxEN BIT(1)
3712#define RCC_I3CxCFGR_I3CxLPEN BIT(2)
3713#define RCC_I3CxCFGR_I3CxAMEN BIT(3)
3714
3715/* RCC_MUXSELCFGR register fields */
3716#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(1, 0)
3717#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0
3718#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(5, 4)
3719#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4
3720#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(9, 8)
3721#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8
3722#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(13, 12)
3723#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12
3724#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(17, 16)
3725#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16
3726#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20)
3727#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20
3728#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24)
3729#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24
3730#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28)
3731#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28
3732
3733/* RCC_XBAR0CFGR register fields */
3734#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0)
3735#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0
3736#define RCC_XBAR0CFGR_XBAR0EN BIT(6)
3737#define RCC_XBAR0CFGR_XBAR0STS BIT(7)
3738
3739/* RCC_XBAR1CFGR register fields */
3740#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0)
3741#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0
3742#define RCC_XBAR1CFGR_XBAR1EN BIT(6)
3743#define RCC_XBAR1CFGR_XBAR1STS BIT(7)
3744
3745/* RCC_XBAR2CFGR register fields */
3746#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0)
3747#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0
3748#define RCC_XBAR2CFGR_XBAR2EN BIT(6)
3749#define RCC_XBAR2CFGR_XBAR2STS BIT(7)
3750
3751/* RCC_XBAR3CFGR register fields */
3752#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0)
3753#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0
3754#define RCC_XBAR3CFGR_XBAR3EN BIT(6)
3755#define RCC_XBAR3CFGR_XBAR3STS BIT(7)
3756
3757/* RCC_XBAR4CFGR register fields */
3758#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0)
3759#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0
3760#define RCC_XBAR4CFGR_XBAR4EN BIT(6)
3761#define RCC_XBAR4CFGR_XBAR4STS BIT(7)
3762
3763/* RCC_XBAR5CFGR register fields */
3764#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0)
3765#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0
3766#define RCC_XBAR5CFGR_XBAR5EN BIT(6)
3767#define RCC_XBAR5CFGR_XBAR5STS BIT(7)
3768
3769/* RCC_XBAR6CFGR register fields */
3770#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0)
3771#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0
3772#define RCC_XBAR6CFGR_XBAR6EN BIT(6)
3773#define RCC_XBAR6CFGR_XBAR6STS BIT(7)
3774
3775/* RCC_XBAR7CFGR register fields */
3776#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0)
3777#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0
3778#define RCC_XBAR7CFGR_XBAR7EN BIT(6)
3779#define RCC_XBAR7CFGR_XBAR7STS BIT(7)
3780
3781/* RCC_XBAR8CFGR register fields */
3782#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0)
3783#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0
3784#define RCC_XBAR8CFGR_XBAR8EN BIT(6)
3785#define RCC_XBAR8CFGR_XBAR8STS BIT(7)
3786
3787/* RCC_XBAR9CFGR register fields */
3788#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0)
3789#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0
3790#define RCC_XBAR9CFGR_XBAR9EN BIT(6)
3791#define RCC_XBAR9CFGR_XBAR9STS BIT(7)
3792
3793/* RCC_XBAR10CFGR register fields */
3794#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0)
3795#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0
3796#define RCC_XBAR10CFGR_XBAR10EN BIT(6)
3797#define RCC_XBAR10CFGR_XBAR10STS BIT(7)
3798
3799/* RCC_XBAR11CFGR register fields */
3800#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0)
3801#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0
3802#define RCC_XBAR11CFGR_XBAR11EN BIT(6)
3803#define RCC_XBAR11CFGR_XBAR11STS BIT(7)
3804
3805/* RCC_XBAR12CFGR register fields */
3806#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0)
3807#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0
3808#define RCC_XBAR12CFGR_XBAR12EN BIT(6)
3809#define RCC_XBAR12CFGR_XBAR12STS BIT(7)
3810
3811/* RCC_XBAR13CFGR register fields */
3812#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0)
3813#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0
3814#define RCC_XBAR13CFGR_XBAR13EN BIT(6)
3815#define RCC_XBAR13CFGR_XBAR13STS BIT(7)
3816
3817/* RCC_XBAR14CFGR register fields */
3818#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0)
3819#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0
3820#define RCC_XBAR14CFGR_XBAR14EN BIT(6)
3821#define RCC_XBAR14CFGR_XBAR14STS BIT(7)
3822
3823/* RCC_XBAR15CFGR register fields */
3824#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0)
3825#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0
3826#define RCC_XBAR15CFGR_XBAR15EN BIT(6)
3827#define RCC_XBAR15CFGR_XBAR15STS BIT(7)
3828
3829/* RCC_XBAR16CFGR register fields */
3830#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0)
3831#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0
3832#define RCC_XBAR16CFGR_XBAR16EN BIT(6)
3833#define RCC_XBAR16CFGR_XBAR16STS BIT(7)
3834
3835/* RCC_XBAR17CFGR register fields */
3836#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0)
3837#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0
3838#define RCC_XBAR17CFGR_XBAR17EN BIT(6)
3839#define RCC_XBAR17CFGR_XBAR17STS BIT(7)
3840
3841/* RCC_XBAR18CFGR register fields */
3842#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0)
3843#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0
3844#define RCC_XBAR18CFGR_XBAR18EN BIT(6)
3845#define RCC_XBAR18CFGR_XBAR18STS BIT(7)
3846
3847/* RCC_XBAR19CFGR register fields */
3848#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0)
3849#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0
3850#define RCC_XBAR19CFGR_XBAR19EN BIT(6)
3851#define RCC_XBAR19CFGR_XBAR19STS BIT(7)
3852
3853/* RCC_XBAR20CFGR register fields */
3854#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0)
3855#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0
3856#define RCC_XBAR20CFGR_XBAR20EN BIT(6)
3857#define RCC_XBAR20CFGR_XBAR20STS BIT(7)
3858
3859/* RCC_XBAR21CFGR register fields */
3860#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0)
3861#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0
3862#define RCC_XBAR21CFGR_XBAR21EN BIT(6)
3863#define RCC_XBAR21CFGR_XBAR21STS BIT(7)
3864
3865/* RCC_XBAR22CFGR register fields */
3866#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0)
3867#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0
3868#define RCC_XBAR22CFGR_XBAR22EN BIT(6)
3869#define RCC_XBAR22CFGR_XBAR22STS BIT(7)
3870
3871/* RCC_XBAR23CFGR register fields */
3872#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0)
3873#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0
3874#define RCC_XBAR23CFGR_XBAR23EN BIT(6)
3875#define RCC_XBAR23CFGR_XBAR23STS BIT(7)
3876
3877/* RCC_XBAR24CFGR register fields */
3878#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0)
3879#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0
3880#define RCC_XBAR24CFGR_XBAR24EN BIT(6)
3881#define RCC_XBAR24CFGR_XBAR24STS BIT(7)
3882
3883/* RCC_XBAR25CFGR register fields */
3884#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0)
3885#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0
3886#define RCC_XBAR25CFGR_XBAR25EN BIT(6)
3887#define RCC_XBAR25CFGR_XBAR25STS BIT(7)
3888
3889/* RCC_XBAR26CFGR register fields */
3890#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0)
3891#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0
3892#define RCC_XBAR26CFGR_XBAR26EN BIT(6)
3893#define RCC_XBAR26CFGR_XBAR26STS BIT(7)
3894
3895/* RCC_XBAR27CFGR register fields */
3896#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0)
3897#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0
3898#define RCC_XBAR27CFGR_XBAR27EN BIT(6)
3899#define RCC_XBAR27CFGR_XBAR27STS BIT(7)
3900
3901/* RCC_XBAR28CFGR register fields */
3902#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0)
3903#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0
3904#define RCC_XBAR28CFGR_XBAR28EN BIT(6)
3905#define RCC_XBAR28CFGR_XBAR28STS BIT(7)
3906
3907/* RCC_XBAR29CFGR register fields */
3908#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0)
3909#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0
3910#define RCC_XBAR29CFGR_XBAR29EN BIT(6)
3911#define RCC_XBAR29CFGR_XBAR29STS BIT(7)
3912
3913/* RCC_XBAR30CFGR register fields */
3914#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0)
3915#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0
3916#define RCC_XBAR30CFGR_XBAR30EN BIT(6)
3917#define RCC_XBAR30CFGR_XBAR30STS BIT(7)
3918
3919/* RCC_XBAR31CFGR register fields */
3920#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0)
3921#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0
3922#define RCC_XBAR31CFGR_XBAR31EN BIT(6)
3923#define RCC_XBAR31CFGR_XBAR31STS BIT(7)
3924
3925/* RCC_XBAR32CFGR register fields */
3926#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0)
3927#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0
3928#define RCC_XBAR32CFGR_XBAR32EN BIT(6)
3929#define RCC_XBAR32CFGR_XBAR32STS BIT(7)
3930
3931/* RCC_XBAR33CFGR register fields */
3932#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0)
3933#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0
3934#define RCC_XBAR33CFGR_XBAR33EN BIT(6)
3935#define RCC_XBAR33CFGR_XBAR33STS BIT(7)
3936
3937/* RCC_XBAR34CFGR register fields */
3938#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0)
3939#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0
3940#define RCC_XBAR34CFGR_XBAR34EN BIT(6)
3941#define RCC_XBAR34CFGR_XBAR34STS BIT(7)
3942
3943/* RCC_XBAR35CFGR register fields */
3944#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0)
3945#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0
3946#define RCC_XBAR35CFGR_XBAR35EN BIT(6)
3947#define RCC_XBAR35CFGR_XBAR35STS BIT(7)
3948
3949/* RCC_XBAR36CFGR register fields */
3950#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0)
3951#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0
3952#define RCC_XBAR36CFGR_XBAR36EN BIT(6)
3953#define RCC_XBAR36CFGR_XBAR36STS BIT(7)
3954
3955/* RCC_XBAR37CFGR register fields */
3956#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0)
3957#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0
3958#define RCC_XBAR37CFGR_XBAR37EN BIT(6)
3959#define RCC_XBAR37CFGR_XBAR37STS BIT(7)
3960
3961/* RCC_XBAR38CFGR register fields */
3962#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0)
3963#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0
3964#define RCC_XBAR38CFGR_XBAR38EN BIT(6)
3965#define RCC_XBAR38CFGR_XBAR38STS BIT(7)
3966
3967/* RCC_XBAR39CFGR register fields */
3968#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0)
3969#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0
3970#define RCC_XBAR39CFGR_XBAR39EN BIT(6)
3971#define RCC_XBAR39CFGR_XBAR39STS BIT(7)
3972
3973/* RCC_XBAR40CFGR register fields */
3974#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0)
3975#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0
3976#define RCC_XBAR40CFGR_XBAR40EN BIT(6)
3977#define RCC_XBAR40CFGR_XBAR40STS BIT(7)
3978
3979/* RCC_XBAR41CFGR register fields */
3980#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0)
3981#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0
3982#define RCC_XBAR41CFGR_XBAR41EN BIT(6)
3983#define RCC_XBAR41CFGR_XBAR41STS BIT(7)
3984
3985/* RCC_XBAR42CFGR register fields */
3986#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0)
3987#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0
3988#define RCC_XBAR42CFGR_XBAR42EN BIT(6)
3989#define RCC_XBAR42CFGR_XBAR42STS BIT(7)
3990
3991/* RCC_XBAR43CFGR register fields */
3992#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0)
3993#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0
3994#define RCC_XBAR43CFGR_XBAR43EN BIT(6)
3995#define RCC_XBAR43CFGR_XBAR43STS BIT(7)
3996
3997/* RCC_XBAR44CFGR register fields */
3998#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0)
3999#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0
4000#define RCC_XBAR44CFGR_XBAR44EN BIT(6)
4001#define RCC_XBAR44CFGR_XBAR44STS BIT(7)
4002
4003/* RCC_XBAR45CFGR register fields */
4004#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0)
4005#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0
4006#define RCC_XBAR45CFGR_XBAR45EN BIT(6)
4007#define RCC_XBAR45CFGR_XBAR45STS BIT(7)
4008
4009/* RCC_XBAR46CFGR register fields */
4010#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0)
4011#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0
4012#define RCC_XBAR46CFGR_XBAR46EN BIT(6)
4013#define RCC_XBAR46CFGR_XBAR46STS BIT(7)
4014
4015/* RCC_XBAR47CFGR register fields */
4016#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0)
4017#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0
4018#define RCC_XBAR47CFGR_XBAR47EN BIT(6)
4019#define RCC_XBAR47CFGR_XBAR47STS BIT(7)
4020
4021/* RCC_XBAR48CFGR register fields */
4022#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0)
4023#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0
4024#define RCC_XBAR48CFGR_XBAR48EN BIT(6)
4025#define RCC_XBAR48CFGR_XBAR48STS BIT(7)
4026
4027/* RCC_XBAR49CFGR register fields */
4028#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0)
4029#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0
4030#define RCC_XBAR49CFGR_XBAR49EN BIT(6)
4031#define RCC_XBAR49CFGR_XBAR49STS BIT(7)
4032
4033/* RCC_XBAR50CFGR register fields */
4034#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0)
4035#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0
4036#define RCC_XBAR50CFGR_XBAR50EN BIT(6)
4037#define RCC_XBAR50CFGR_XBAR50STS BIT(7)
4038
4039/* RCC_XBAR51CFGR register fields */
4040#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0)
4041#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0
4042#define RCC_XBAR51CFGR_XBAR51EN BIT(6)
4043#define RCC_XBAR51CFGR_XBAR51STS BIT(7)
4044
4045/* RCC_XBAR52CFGR register fields */
4046#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0)
4047#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0
4048#define RCC_XBAR52CFGR_XBAR52EN BIT(6)
4049#define RCC_XBAR52CFGR_XBAR52STS BIT(7)
4050
4051/* RCC_XBAR53CFGR register fields */
4052#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0)
4053#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0
4054#define RCC_XBAR53CFGR_XBAR53EN BIT(6)
4055#define RCC_XBAR53CFGR_XBAR53STS BIT(7)
4056
4057/* RCC_XBAR54CFGR register fields */
4058#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0)
4059#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0
4060#define RCC_XBAR54CFGR_XBAR54EN BIT(6)
4061#define RCC_XBAR54CFGR_XBAR54STS BIT(7)
4062
4063/* RCC_XBAR55CFGR register fields */
4064#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0)
4065#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0
4066#define RCC_XBAR55CFGR_XBAR55EN BIT(6)
4067#define RCC_XBAR55CFGR_XBAR55STS BIT(7)
4068
4069/* RCC_XBAR56CFGR register fields */
4070#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0)
4071#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0
4072#define RCC_XBAR56CFGR_XBAR56EN BIT(6)
4073#define RCC_XBAR56CFGR_XBAR56STS BIT(7)
4074
4075/* RCC_XBAR57CFGR register fields */
4076#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0)
4077#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0
4078#define RCC_XBAR57CFGR_XBAR57EN BIT(6)
4079#define RCC_XBAR57CFGR_XBAR57STS BIT(7)
4080
4081/* RCC_XBAR58CFGR register fields */
4082#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0)
4083#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0
4084#define RCC_XBAR58CFGR_XBAR58EN BIT(6)
4085#define RCC_XBAR58CFGR_XBAR58STS BIT(7)
4086
4087/* RCC_XBAR59CFGR register fields */
4088#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0)
4089#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0
4090#define RCC_XBAR59CFGR_XBAR59EN BIT(6)
4091#define RCC_XBAR59CFGR_XBAR59STS BIT(7)
4092
4093/* RCC_XBAR60CFGR register fields */
4094#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0)
4095#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0
4096#define RCC_XBAR60CFGR_XBAR60EN BIT(6)
4097#define RCC_XBAR60CFGR_XBAR60STS BIT(7)
4098
4099/* RCC_XBAR61CFGR register fields */
4100#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0)
4101#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0
4102#define RCC_XBAR61CFGR_XBAR61EN BIT(6)
4103#define RCC_XBAR61CFGR_XBAR61STS BIT(7)
4104
4105/* RCC_XBAR62CFGR register fields */
4106#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0)
4107#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0
4108#define RCC_XBAR62CFGR_XBAR62EN BIT(6)
4109#define RCC_XBAR62CFGR_XBAR62STS BIT(7)
4110
4111/* RCC_XBAR63CFGR register fields */
4112#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0)
4113#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0
4114#define RCC_XBAR63CFGR_XBAR63EN BIT(6)
4115#define RCC_XBAR63CFGR_XBAR63STS BIT(7)
4116
4117/* RCC_XBARxCFGR register fields */
4118#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0)
4119#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0
4120#define RCC_XBARxCFGR_XBARxEN BIT(6)
4121#define RCC_XBARxCFGR_XBARxSTS BIT(7)
4122
4123/* RCC_PREDIV0CFGR register fields */
4124#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0)
4125#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0
4126
4127/* RCC_PREDIV1CFGR register fields */
4128#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0)
4129#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0
4130
4131/* RCC_PREDIV2CFGR register fields */
4132#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0)
4133#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0
4134
4135/* RCC_PREDIV3CFGR register fields */
4136#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0)
4137#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0
4138
4139/* RCC_PREDIV4CFGR register fields */
4140#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0)
4141#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0
4142
4143/* RCC_PREDIV5CFGR register fields */
4144#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0)
4145#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0
4146
4147/* RCC_PREDIV6CFGR register fields */
4148#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0)
4149#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0
4150
4151/* RCC_PREDIV7CFGR register fields */
4152#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0)
4153#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0
4154
4155/* RCC_PREDIV8CFGR register fields */
4156#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0)
4157#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0
4158
4159/* RCC_PREDIV9CFGR register fields */
4160#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0)
4161#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0
4162
4163/* RCC_PREDIV10CFGR register fields */
4164#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0)
4165#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0
4166
4167/* RCC_PREDIV11CFGR register fields */
4168#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0)
4169#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0
4170
4171/* RCC_PREDIV12CFGR register fields */
4172#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0)
4173#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0
4174
4175/* RCC_PREDIV13CFGR register fields */
4176#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0)
4177#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0
4178
4179/* RCC_PREDIV14CFGR register fields */
4180#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0)
4181#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0
4182
4183/* RCC_PREDIV15CFGR register fields */
4184#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0)
4185#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0
4186
4187/* RCC_PREDIV16CFGR register fields */
4188#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0)
4189#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0
4190
4191/* RCC_PREDIV17CFGR register fields */
4192#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0)
4193#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0
4194
4195/* RCC_PREDIV18CFGR register fields */
4196#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0)
4197#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0
4198
4199/* RCC_PREDIV19CFGR register fields */
4200#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0)
4201#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0
4202
4203/* RCC_PREDIV20CFGR register fields */
4204#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0)
4205#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0
4206
4207/* RCC_PREDIV21CFGR register fields */
4208#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0)
4209#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0
4210
4211/* RCC_PREDIV22CFGR register fields */
4212#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0)
4213#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0
4214
4215/* RCC_PREDIV23CFGR register fields */
4216#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0)
4217#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0
4218
4219/* RCC_PREDIV24CFGR register fields */
4220#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0)
4221#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0
4222
4223/* RCC_PREDIV25CFGR register fields */
4224#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0)
4225#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0
4226
4227/* RCC_PREDIV26CFGR register fields */
4228#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0)
4229#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0
4230
4231/* RCC_PREDIV27CFGR register fields */
4232#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0)
4233#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0
4234
4235/* RCC_PREDIV28CFGR register fields */
4236#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0)
4237#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0
4238
4239/* RCC_PREDIV29CFGR register fields */
4240#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0)
4241#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0
4242
4243/* RCC_PREDIV30CFGR register fields */
4244#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0)
4245#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0
4246
4247/* RCC_PREDIV31CFGR register fields */
4248#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0)
4249#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0
4250
4251/* RCC_PREDIV32CFGR register fields */
4252#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0)
4253#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0
4254
4255/* RCC_PREDIV33CFGR register fields */
4256#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0)
4257#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0
4258
4259/* RCC_PREDIV34CFGR register fields */
4260#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0)
4261#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0
4262
4263/* RCC_PREDIV35CFGR register fields */
4264#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0)
4265#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0
4266
4267/* RCC_PREDIV36CFGR register fields */
4268#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0)
4269#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0
4270
4271/* RCC_PREDIV37CFGR register fields */
4272#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0)
4273#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0
4274
4275/* RCC_PREDIV38CFGR register fields */
4276#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0)
4277#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0
4278
4279/* RCC_PREDIV39CFGR register fields */
4280#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0)
4281#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0
4282
4283/* RCC_PREDIV40CFGR register fields */
4284#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0)
4285#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0
4286
4287/* RCC_PREDIV41CFGR register fields */
4288#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0)
4289#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0
4290
4291/* RCC_PREDIV42CFGR register fields */
4292#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0)
4293#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0
4294
4295/* RCC_PREDIV43CFGR register fields */
4296#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0)
4297#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0
4298
4299/* RCC_PREDIV44CFGR register fields */
4300#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0)
4301#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0
4302
4303/* RCC_PREDIV45CFGR register fields */
4304#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0)
4305#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0
4306
4307/* RCC_PREDIV46CFGR register fields */
4308#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0)
4309#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0
4310
4311/* RCC_PREDIV47CFGR register fields */
4312#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0)
4313#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0
4314
4315/* RCC_PREDIV48CFGR register fields */
4316#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0)
4317#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0
4318
4319/* RCC_PREDIV49CFGR register fields */
4320#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0)
4321#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0
4322
4323/* RCC_PREDIV50CFGR register fields */
4324#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0)
4325#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0
4326
4327/* RCC_PREDIV51CFGR register fields */
4328#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0)
4329#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0
4330
4331/* RCC_PREDIV52CFGR register fields */
4332#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0)
4333#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0
4334
4335/* RCC_PREDIV53CFGR register fields */
4336#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0)
4337#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0
4338
4339/* RCC_PREDIV54CFGR register fields */
4340#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0)
4341#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0
4342
4343/* RCC_PREDIV55CFGR register fields */
4344#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0)
4345#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0
4346
4347/* RCC_PREDIV56CFGR register fields */
4348#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0)
4349#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0
4350
4351/* RCC_PREDIV57CFGR register fields */
4352#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0)
4353#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0
4354
4355/* RCC_PREDIV58CFGR register fields */
4356#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0)
4357#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0
4358
4359/* RCC_PREDIV59CFGR register fields */
4360#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0)
4361#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0
4362
4363/* RCC_PREDIV60CFGR register fields */
4364#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0)
4365#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0
4366
4367/* RCC_PREDIV61CFGR register fields */
4368#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0)
4369#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0
4370
4371/* RCC_PREDIV62CFGR register fields */
4372#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0)
4373#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0
4374
4375/* RCC_PREDIV63CFGR register fields */
4376#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0)
4377#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0
4378
4379/* RCC_PREDIVxCFGR register fields */
4380#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0)
4381#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0
4382
4383/* RCC_FINDIV0CFGR register fields */
4384#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0)
4385#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0
4386#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6)
4387
4388/* RCC_FINDIV1CFGR register fields */
4389#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0)
4390#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0
4391#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6)
4392
4393/* RCC_FINDIV2CFGR register fields */
4394#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0)
4395#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0
4396#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6)
4397
4398/* RCC_FINDIV3CFGR register fields */
4399#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0)
4400#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0
4401#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6)
4402
4403/* RCC_FINDIV4CFGR register fields */
4404#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0)
4405#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0
4406#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6)
4407
4408/* RCC_FINDIV5CFGR register fields */
4409#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0)
4410#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0
4411#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6)
4412
4413/* RCC_FINDIV6CFGR register fields */
4414#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0)
4415#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0
4416#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6)
4417
4418/* RCC_FINDIV7CFGR register fields */
4419#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0)
4420#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0
4421#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6)
4422
4423/* RCC_FINDIV8CFGR register fields */
4424#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0)
4425#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0
4426#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6)
4427
4428/* RCC_FINDIV9CFGR register fields */
4429#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0)
4430#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0
4431#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6)
4432
4433/* RCC_FINDIV10CFGR register fields */
4434#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0)
4435#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0
4436#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6)
4437
4438/* RCC_FINDIV11CFGR register fields */
4439#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0)
4440#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0
4441#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6)
4442
4443/* RCC_FINDIV12CFGR register fields */
4444#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0)
4445#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0
4446#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6)
4447
4448/* RCC_FINDIV13CFGR register fields */
4449#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0)
4450#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0
4451#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6)
4452
4453/* RCC_FINDIV14CFGR register fields */
4454#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0)
4455#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0
4456#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6)
4457
4458/* RCC_FINDIV15CFGR register fields */
4459#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0)
4460#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0
4461#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6)
4462
4463/* RCC_FINDIV16CFGR register fields */
4464#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0)
4465#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0
4466#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6)
4467
4468/* RCC_FINDIV17CFGR register fields */
4469#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0)
4470#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0
4471#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6)
4472
4473/* RCC_FINDIV18CFGR register fields */
4474#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0)
4475#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0
4476#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6)
4477
4478/* RCC_FINDIV19CFGR register fields */
4479#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0)
4480#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0
4481#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6)
4482
4483/* RCC_FINDIV20CFGR register fields */
4484#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0)
4485#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0
4486#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6)
4487
4488/* RCC_FINDIV21CFGR register fields */
4489#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0)
4490#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0
4491#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6)
4492
4493/* RCC_FINDIV22CFGR register fields */
4494#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0)
4495#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0
4496#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6)
4497
4498/* RCC_FINDIV23CFGR register fields */
4499#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0)
4500#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0
4501#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6)
4502
4503/* RCC_FINDIV24CFGR register fields */
4504#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0)
4505#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0
4506#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6)
4507
4508/* RCC_FINDIV25CFGR register fields */
4509#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0)
4510#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0
4511#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6)
4512
4513/* RCC_FINDIV26CFGR register fields */
4514#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0)
4515#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0
4516#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6)
4517
4518/* RCC_FINDIV27CFGR register fields */
4519#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0)
4520#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0
4521#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6)
4522
4523/* RCC_FINDIV28CFGR register fields */
4524#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0)
4525#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0
4526#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6)
4527
4528/* RCC_FINDIV29CFGR register fields */
4529#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0)
4530#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0
4531#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6)
4532
4533/* RCC_FINDIV30CFGR register fields */
4534#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0)
4535#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0
4536#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6)
4537
4538/* RCC_FINDIV31CFGR register fields */
4539#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0)
4540#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0
4541#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6)
4542
4543/* RCC_FINDIV32CFGR register fields */
4544#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0)
4545#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0
4546#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6)
4547
4548/* RCC_FINDIV33CFGR register fields */
4549#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0)
4550#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0
4551#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6)
4552
4553/* RCC_FINDIV34CFGR register fields */
4554#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0)
4555#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0
4556#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6)
4557
4558/* RCC_FINDIV35CFGR register fields */
4559#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0)
4560#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0
4561#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6)
4562
4563/* RCC_FINDIV36CFGR register fields */
4564#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0)
4565#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0
4566#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6)
4567
4568/* RCC_FINDIV37CFGR register fields */
4569#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0)
4570#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0
4571#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6)
4572
4573/* RCC_FINDIV38CFGR register fields */
4574#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0)
4575#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0
4576#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6)
4577
4578/* RCC_FINDIV39CFGR register fields */
4579#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0)
4580#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0
4581#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6)
4582
4583/* RCC_FINDIV40CFGR register fields */
4584#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0)
4585#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0
4586#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6)
4587
4588/* RCC_FINDIV41CFGR register fields */
4589#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0)
4590#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0
4591#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6)
4592
4593/* RCC_FINDIV42CFGR register fields */
4594#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0)
4595#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0
4596#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6)
4597
4598/* RCC_FINDIV43CFGR register fields */
4599#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0)
4600#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0
4601#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6)
4602
4603/* RCC_FINDIV44CFGR register fields */
4604#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0)
4605#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0
4606#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6)
4607
4608/* RCC_FINDIV45CFGR register fields */
4609#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0)
4610#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0
4611#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6)
4612
4613/* RCC_FINDIV46CFGR register fields */
4614#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0)
4615#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0
4616#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6)
4617
4618/* RCC_FINDIV47CFGR register fields */
4619#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0)
4620#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0
4621#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6)
4622
4623/* RCC_FINDIV48CFGR register fields */
4624#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0)
4625#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0
4626#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6)
4627
4628/* RCC_FINDIV49CFGR register fields */
4629#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0)
4630#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0
4631#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6)
4632
4633/* RCC_FINDIV50CFGR register fields */
4634#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0)
4635#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0
4636#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6)
4637
4638/* RCC_FINDIV51CFGR register fields */
4639#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0)
4640#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0
4641#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6)
4642
4643/* RCC_FINDIV52CFGR register fields */
4644#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0)
4645#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0
4646#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6)
4647
4648/* RCC_FINDIV53CFGR register fields */
4649#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0)
4650#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0
4651#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6)
4652
4653/* RCC_FINDIV54CFGR register fields */
4654#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0)
4655#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0
4656#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6)
4657
4658/* RCC_FINDIV55CFGR register fields */
4659#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0)
4660#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0
4661#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6)
4662
4663/* RCC_FINDIV56CFGR register fields */
4664#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0)
4665#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0
4666#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6)
4667
4668/* RCC_FINDIV57CFGR register fields */
4669#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0)
4670#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0
4671#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6)
4672
4673/* RCC_FINDIV58CFGR register fields */
4674#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0)
4675#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0
4676#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6)
4677
4678/* RCC_FINDIV59CFGR register fields */
4679#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0)
4680#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0
4681#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6)
4682
4683/* RCC_FINDIV60CFGR register fields */
4684#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0)
4685#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0
4686#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6)
4687
4688/* RCC_FINDIV61CFGR register fields */
4689#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0)
4690#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0
4691#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6)
4692
4693/* RCC_FINDIV62CFGR register fields */
4694#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0)
4695#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0
4696#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6)
4697
4698/* RCC_FINDIV63CFGR register fields */
4699#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0)
4700#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0
4701#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6)
4702
4703/* RCC_FINDIVxCFGR register fields */
4704#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0)
4705#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0
4706#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6)
4707
4708/* RCC_FCALCOBS0CFGR register fields */
4709#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
4710#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0
4711#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
4712#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8
4713#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15)
4714#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16)
4715#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17)
4716#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18)
4717#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
4718#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22
4719#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25)
4720#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26)
4721
4722/* RCC_FCALCOBS1CFGR register fields */
4723#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
4724#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0
4725#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
4726#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8
4727#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16)
4728#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18)
4729#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
4730#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22
4731#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26)
4732#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27)
4733
4734/* RCC_FCALCREFCFGR register fields */
4735#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0)
4736#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0
4737
4738/* RCC_FCALCCR1 register fields */
4739#define RCC_FCALCCR1_FCALCRUN BIT(0)
4740
4741/* RCC_FCALCCR2 register fields */
4742#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3)
4743#define RCC_FCALCCR2_FCALCMD_SHIFT 3
4744#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11)
4745#define RCC_FCALCCR2_FCALCTWC_SHIFT 11
4746#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17)
4747#define RCC_FCALCCR2_FCALCTYP_SHIFT 17
4748
4749/* RCC_FCALCSR register fields */
4750#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0)
4751#define RCC_FCALCSR_FVAL_SHIFT 0
4752#define RCC_FCALCSR_FCALCSTS BIT(19)
4753
4754/* RCC_PLL4CFGR1 register fields */
4755#define RCC_PLL4CFGR1_SSMODRST BIT(0)
4756#define RCC_PLL4CFGR1_PLLEN BIT(8)
4757#define RCC_PLL4CFGR1_PLLRDY BIT(24)
4758#define RCC_PLL4CFGR1_CKREFST BIT(28)
4759
4760/* RCC_PLL4CFGR2 register fields */
4761#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
4762#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0
4763#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16)
4764#define RCC_PLL4CFGR2_FBDIV_SHIFT 16
4765
4766/* RCC_PLL4CFGR3 register fields */
4767#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0)
4768#define RCC_PLL4CFGR3_FRACIN_SHIFT 0
4769#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24)
4770#define RCC_PLL4CFGR3_DACEN BIT(25)
4771#define RCC_PLL4CFGR3_SSCGDIS BIT(26)
4772
4773/* RCC_PLL4CFGR4 register fields */
4774#define RCC_PLL4CFGR4_DSMEN BIT(8)
4775#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9)
4776#define RCC_PLL4CFGR4_BYPASS BIT(10)
4777
4778/* RCC_PLL4CFGR5 register fields */
4779#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
4780#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0
4781#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16)
4782#define RCC_PLL4CFGR5_SPREAD_SHIFT 16
4783
4784/* RCC_PLL4CFGR6 register fields */
4785#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
4786#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0
4787
4788/* RCC_PLL4CFGR7 register fields */
4789#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
4790#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0
4791
4792/* RCC_PLL5CFGR1 register fields */
4793#define RCC_PLL5CFGR1_SSMODRST BIT(0)
4794#define RCC_PLL5CFGR1_PLLEN BIT(8)
4795#define RCC_PLL5CFGR1_PLLRDY BIT(24)
4796#define RCC_PLL5CFGR1_CKREFST BIT(28)
4797
4798/* RCC_PLL5CFGR2 register fields */
4799#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
4800#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0
4801#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16)
4802#define RCC_PLL5CFGR2_FBDIV_SHIFT 16
4803
4804/* RCC_PLL5CFGR3 register fields */
4805#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0)
4806#define RCC_PLL5CFGR3_FRACIN_SHIFT 0
4807#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24)
4808#define RCC_PLL5CFGR3_DACEN BIT(25)
4809#define RCC_PLL5CFGR3_SSCGDIS BIT(26)
4810
4811/* RCC_PLL5CFGR4 register fields */
4812#define RCC_PLL5CFGR4_DSMEN BIT(8)
4813#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9)
4814#define RCC_PLL5CFGR4_BYPASS BIT(10)
4815
4816/* RCC_PLL5CFGR5 register fields */
4817#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
4818#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0
4819#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16)
4820#define RCC_PLL5CFGR5_SPREAD_SHIFT 16
4821
4822/* RCC_PLL5CFGR6 register fields */
4823#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
4824#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0
4825
4826/* RCC_PLL5CFGR7 register fields */
4827#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
4828#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0
4829
4830/* RCC_PLL6CFGR1 register fields */
4831#define RCC_PLL6CFGR1_SSMODRST BIT(0)
4832#define RCC_PLL6CFGR1_PLLEN BIT(8)
4833#define RCC_PLL6CFGR1_PLLRDY BIT(24)
4834#define RCC_PLL6CFGR1_CKREFST BIT(28)
4835
4836/* RCC_PLL6CFGR2 register fields */
4837#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
4838#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0
4839#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16)
4840#define RCC_PLL6CFGR2_FBDIV_SHIFT 16
4841
4842/* RCC_PLL6CFGR3 register fields */
4843#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0)
4844#define RCC_PLL6CFGR3_FRACIN_SHIFT 0
4845#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24)
4846#define RCC_PLL6CFGR3_DACEN BIT(25)
4847#define RCC_PLL6CFGR3_SSCGDIS BIT(26)
4848
4849/* RCC_PLL6CFGR4 register fields */
4850#define RCC_PLL6CFGR4_DSMEN BIT(8)
4851#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9)
4852#define RCC_PLL6CFGR4_BYPASS BIT(10)
4853
4854/* RCC_PLL6CFGR5 register fields */
4855#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
4856#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0
4857#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16)
4858#define RCC_PLL6CFGR5_SPREAD_SHIFT 16
4859
4860/* RCC_PLL6CFGR6 register fields */
4861#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
4862#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0
4863
4864/* RCC_PLL6CFGR7 register fields */
4865#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
4866#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0
4867
4868/* RCC_PLL7CFGR1 register fields */
4869#define RCC_PLL7CFGR1_SSMODRST BIT(0)
4870#define RCC_PLL7CFGR1_PLLEN BIT(8)
4871#define RCC_PLL7CFGR1_PLLRDY BIT(24)
4872#define RCC_PLL7CFGR1_CKREFST BIT(28)
4873
4874/* RCC_PLL7CFGR2 register fields */
4875#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
4876#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0
4877#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16)
4878#define RCC_PLL7CFGR2_FBDIV_SHIFT 16
4879
4880/* RCC_PLL7CFGR3 register fields */
4881#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0)
4882#define RCC_PLL7CFGR3_FRACIN_SHIFT 0
4883#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24)
4884#define RCC_PLL7CFGR3_DACEN BIT(25)
4885#define RCC_PLL7CFGR3_SSCGDIS BIT(26)
4886
4887/* RCC_PLL7CFGR4 register fields */
4888#define RCC_PLL7CFGR4_DSMEN BIT(8)
4889#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9)
4890#define RCC_PLL7CFGR4_BYPASS BIT(10)
4891
4892/* RCC_PLL7CFGR5 register fields */
4893#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
4894#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0
4895#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16)
4896#define RCC_PLL7CFGR5_SPREAD_SHIFT 16
4897
4898/* RCC_PLL7CFGR6 register fields */
4899#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
4900#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0
4901
4902/* RCC_PLL7CFGR7 register fields */
4903#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
4904#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0
4905
4906/* RCC_PLL8CFGR1 register fields */
4907#define RCC_PLL8CFGR1_SSMODRST BIT(0)
4908#define RCC_PLL8CFGR1_PLLEN BIT(8)
4909#define RCC_PLL8CFGR1_PLLRDY BIT(24)
4910#define RCC_PLL8CFGR1_CKREFST BIT(28)
4911
4912/* RCC_PLL8CFGR2 register fields */
4913#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
4914#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0
4915#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16)
4916#define RCC_PLL8CFGR2_FBDIV_SHIFT 16
4917
4918/* RCC_PLL8CFGR3 register fields */
4919#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0)
4920#define RCC_PLL8CFGR3_FRACIN_SHIFT 0
4921#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24)
4922#define RCC_PLL8CFGR3_DACEN BIT(25)
4923#define RCC_PLL8CFGR3_SSCGDIS BIT(26)
4924
4925/* RCC_PLL8CFGR4 register fields */
4926#define RCC_PLL8CFGR4_DSMEN BIT(8)
4927#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9)
4928#define RCC_PLL8CFGR4_BYPASS BIT(10)
4929
4930/* RCC_PLL8CFGR5 register fields */
4931#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
4932#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0
4933#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16)
4934#define RCC_PLL8CFGR5_SPREAD_SHIFT 16
4935
4936/* RCC_PLL8CFGR6 register fields */
4937#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
4938#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0
4939
4940/* RCC_PLL8CFGR7 register fields */
4941#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
4942#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0
4943
4944/* RCC_PLLxCFGR1 register fields */
4945#define RCC_PLLxCFGR1_SSMODRST BIT(0)
4946#define RCC_PLLxCFGR1_PLLEN BIT(8)
4947#define RCC_PLLxCFGR1_PLLRDY BIT(24)
4948#define RCC_PLLxCFGR1_CKREFST BIT(28)
4949
4950/* RCC_PLLxCFGR2 register fields */
4951#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
4952#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
4953#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
4954#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
4955
4956/* RCC_PLLxCFGR3 register fields */
4957#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
4958#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
4959#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
4960#define RCC_PLLxCFGR3_DACEN BIT(25)
4961#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
4962
4963/* RCC_PLLxCFGR4 register fields */
4964#define RCC_PLLxCFGR4_DSMEN BIT(8)
4965#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
4966#define RCC_PLLxCFGR4_BYPASS BIT(10)
4967
4968/* RCC_PLLxCFGR5 register fields */
4969#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
4970#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
4971#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
4972#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
4973
4974/* RCC_PLLxCFGR6 register fields */
4975#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
4976#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
4977
4978/* RCC_PLLxCFGR7 register fields */
4979#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
4980#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
4981
4982/* RCC_VERR register fields */
4983#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0)
4984#define RCC_VERR_MINREV_SHIFT 0
4985#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4)
4986#define RCC_VERR_MAJREV_SHIFT 4
4987
4988#endif /* STM32MP2_RCC_H */