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developer65014b82015-04-13 14:47:57 +08001/*
Julius Werner1f363212019-05-30 17:34:08 -07002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
developer65014b82015-04-13 14:47:57 +08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
developer65014b82015-04-13 14:47:57 +08005 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00006
developer65014b82015-04-13 14:47:57 +08007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <common/bl_common.h>
10#include <common/debug.h>
Julius Werner1f363212019-05-30 17:34:08 -070011#include <common/desc_image_load.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <drivers/console.h>
13#include <drivers/generic_delay_timer.h>
14#include <lib/mmio.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000015#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/common_def.h>
17#include <plat/common/platform.h>
18
developer65014b82015-04-13 14:47:57 +080019#include <mcucfg.h>
developer65014b82015-04-13 14:47:57 +080020#include <mtcmos.h>
Antonio Nino Diaz42eef852018-09-24 17:15:54 +010021#include <mtk_plat_common.h>
developer65014b82015-04-13 14:47:57 +080022#include <plat_private.h>
developer65014b82015-04-13 14:47:57 +080023#include <spm.h>
24
developer65014b82015-04-13 14:47:57 +080025static entry_point_info_t bl32_ep_info;
26static entry_point_info_t bl33_ep_info;
27
28static void platform_setup_cpu(void)
29{
30 /* turn off all the little core's power except cpu 0 */
31 mtcmos_little_cpu_off();
32
33 /* setup big cores */
34 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res,
35 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
36 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
37 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
38 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
39 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS);
41 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div,
42 MP1_SW_CG_GEN);
43 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl,
44 MP1_L2RSTDISABLE);
45
46 /* set big cores arm64 boot mode */
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg,
48 MP1_CPUCFG_64BIT);
49
50 /* set LITTLE cores arm64 boot mode */
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
52 MP0_CPUCFG_64BIT);
developer53719632015-11-16 14:18:36 +080053
54 /* enable dcm control */
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl,
56 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN |
57 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN |
58 INFRACLK_PSYS_DYNAMIC_CG_EN);
59 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl,
60 L2C_SRAM_DCM_EN);
61 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl,
62 MCU_BUS_DCM_EN);
developer65014b82015-04-13 14:47:57 +080063}
64
developer89ddad12016-03-29 17:42:41 +080065static void platform_setup_sram(void)
66{
67 /* protect BL31 memory from non-secure read/write access */
68 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00);
69 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9);
70}
71
developer65014b82015-04-13 14:47:57 +080072/*******************************************************************************
73 * Return a pointer to the 'entry_point_info' structure of the next image for
74 * the security state specified. BL33 corresponds to the non-secure image type
75 * while BL32 corresponds to the secure image type. A NULL pointer is returned
76 * if the image does not exist.
77 ******************************************************************************/
78entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
79{
80 entry_point_info_t *next_image_info;
81
82 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
Julius Werner1f363212019-05-30 17:34:08 -070083 assert(next_image_info->h.type == PARAM_EP);
developer65014b82015-04-13 14:47:57 +080084
85 /* None of the images on this platform can have 0x0 as the entrypoint */
86 if (next_image_info->pc)
87 return next_image_info;
88 else
89 return NULL;
90}
91
92/*******************************************************************************
93 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
John Tsichritzisd653d332018-09-14 10:34:57 +010094 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
developer65014b82015-04-13 14:47:57 +080095 * are lost (potentially). This needs to be done before the MMU is initialized
96 * so that the memory layout can be used while creating page tables.
97 * BL2 has flushed this information to memory, so we are guaranteed to pick up
98 * good data.
99 ******************************************************************************/
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100100void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
101 u_register_t arg2, u_register_t arg3)
developer65014b82015-04-13 14:47:57 +0800102{
103 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
104
105 VERBOSE("bl31_setup\n");
106
Julius Werner1f363212019-05-30 17:34:08 -0700107 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
developer65014b82015-04-13 14:47:57 +0800108}
109
110/*******************************************************************************
111 * Perform any BL3-1 platform setup code
112 ******************************************************************************/
113void bl31_platform_setup(void)
114{
115 platform_setup_cpu();
developer89ddad12016-03-29 17:42:41 +0800116 platform_setup_sram();
developer65014b82015-04-13 14:47:57 +0800117
Antonio Nino Diaz02a09af2016-05-05 15:23:56 +0100118 generic_delay_timer_init();
developer65014b82015-04-13 14:47:57 +0800119
120 /* Initialize the gic cpu and distributor interfaces */
Koan-Sin Tan1d2b6392016-04-18 15:17:57 +0800121 plat_arm_gic_driver_init();
122 plat_arm_gic_init();
developer65014b82015-04-13 14:47:57 +0800123
developer65014b82015-04-13 14:47:57 +0800124 /* Initialize spm at boot time */
125 spm_boot_init();
126}
127
128/*******************************************************************************
129 * Perform the very early platform specific architectural setup here. At the
130 * moment this is only intializes the mmu in a quick and dirty way.
131 ******************************************************************************/
132void bl31_plat_arch_setup(void)
133{
134 plat_cci_init();
135 plat_cci_enable();
136
Joel Hutton5cc3bc82018-03-21 11:40:57 +0000137 plat_configure_mmu_el3(BL_CODE_BASE,
138 BL_COHERENT_RAM_END - BL_CODE_BASE,
139 BL_CODE_BASE,
140 BL_CODE_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900141 BL_COHERENT_RAM_BASE,
142 BL_COHERENT_RAM_END);
developer65014b82015-04-13 14:47:57 +0800143}
144