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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Ravi Patel2f34d362021-04-15 05:55:19 -07002 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
Soren Brinkmann76fcae32016-03-06 20:16:27 -08007#include <assert.h>
Isla Mitchelle3631462017-07-14 10:46:32 +01008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch_helpers.h>
11#include <common/debug.h>
12#include <drivers/arm/gicv2.h>
13#include <lib/mmio.h>
14#include <lib/psci/psci.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000015#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/platform.h>
17
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000018#include <plat_private.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -080019#include "pm_api_sys.h"
20#include "pm_client.h"
Soren Brinkmann76fcae32016-03-06 20:16:27 -080021
Venkatesh Yadav Abbarapuc9505352022-05-16 17:29:04 +053022static uintptr_t zynqmp_sec_entry;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080023
Venkatesh Yadav Abbarapuc9505352022-05-16 17:29:04 +053024static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080025{
26 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
27
28 dsb();
29 wfi();
30}
31
Soren Brinkmann76fcae32016-03-06 20:16:27 -080032static int zynqmp_pwr_domain_on(u_register_t mpidr)
33{
34 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
35 const struct pm_proc *proc;
Ravi Patel2f34d362021-04-15 05:55:19 -070036 uint32_t buff[3];
37 enum pm_ret_status ret;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080038
39 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
40
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +053041 if (cpu_id == -1) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -080042 return PSCI_E_INTERN_FAIL;
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +053043 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080044 proc = pm_get_proc(cpu_id);
Ravi Patel2f34d362021-04-15 05:55:19 -070045
46 /* Check the APU proc status before wakeup */
47 ret = pm_get_node_status(proc->node_id, buff);
48 if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) {
49 return PSCI_E_INTERN_FAIL;
50 }
51
Filip Drazicd7d62ce2017-02-07 12:03:56 +010052 /* Clear power down request */
53 pm_client_wakeup(proc);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080054
55 /* Send request to PMU to wake up selected APU CPU core */
Soren Brinkmann17aea222016-05-19 07:20:14 -070056 pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080057
58 return PSCI_E_SUCCESS;
59}
60
Soren Brinkmann76fcae32016-03-06 20:16:27 -080061static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
62{
63 unsigned int cpu_id = plat_my_core_pos();
64 const struct pm_proc *proc = pm_get_proc(cpu_id);
65
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +053066 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -080067 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
68 __func__, i, target_state->pwr_domain_state[i]);
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +053069 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080070
71 /* Prevent interrupts from spuriously waking up this cpu */
72 gicv2_cpuif_disable();
73
74 /*
75 * Send request to PMU to power down the appropriate APU CPU
76 * core.
77 * According to PSCI specification, CPU_off function does not
78 * have resume address and CPU core can only be woken up
79 * invoking CPU_on function, during which resume address will
80 * be set.
81 */
Filip Drazic0bd9d0c2016-07-20 17:17:39 +020082 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080083}
84
Soren Brinkmann76fcae32016-03-06 20:16:27 -080085static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
86{
Filip Drazic0bd9d0c2016-07-20 17:17:39 +020087 unsigned int state;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080088 unsigned int cpu_id = plat_my_core_pos();
89 const struct pm_proc *proc = pm_get_proc(cpu_id);
90
91 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
92 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
93 __func__, i, target_state->pwr_domain_state[i]);
94
Filip Drazic0bd9d0c2016-07-20 17:17:39 +020095 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
96 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
97
Soren Brinkmann76fcae32016-03-06 20:16:27 -080098 /* Send request to PMU to suspend this core */
Filip Drazic0bd9d0c2016-07-20 17:17:39 +020099 pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800100
101 /* APU is to be turned off */
102 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800103 /* disable coherency */
104 plat_arm_interconnect_exit_coherency();
105 }
106}
107
108static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
109{
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530110 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800111 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
112 __func__, i, target_state->pwr_domain_state[i]);
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530113 }
Siva Durga Prasad Paladugu60bfbc92018-09-24 22:51:49 -0700114 plat_arm_gic_pcpu_init();
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800115 gicv2_cpuif_enable();
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800116}
117
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800118static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
119{
120 unsigned int cpu_id = plat_my_core_pos();
121 const struct pm_proc *proc = pm_get_proc(cpu_id);
122
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530123 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800124 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
125 __func__, i, target_state->pwr_domain_state[i]);
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530126 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800127
128 /* Clear the APU power control register for this cpu */
129 pm_client_wakeup(proc);
130
131 /* enable coherency */
132 plat_arm_interconnect_enter_coherency();
Soren Brinkmann3b6ebcb2016-02-18 21:16:35 -0800133 /* APU was turned off */
134 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
135 plat_arm_gic_init();
136 } else {
137 gicv2_cpuif_enable();
138 gicv2_pcpu_distif_init();
139 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800140}
141
142/*******************************************************************************
143 * ZynqMP handlers to shutdown/reboot the system
144 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800145
146static void __dead2 zynqmp_system_off(void)
147{
148 /* disable coherency */
149 plat_arm_interconnect_exit_coherency();
150
151 /* Send the power down request to the PMU */
Soren Brinkmann58fbb9b2016-09-02 09:50:54 -0700152 pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
Siva Durga Prasad Paladugu1f80d3f2018-04-30 15:56:10 +0530153 pm_get_shutdown_scope());
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800154
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530155 while (1) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800156 wfi();
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530157 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800158}
159
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800160static void __dead2 zynqmp_system_reset(void)
161{
162 /* disable coherency */
163 plat_arm_interconnect_exit_coherency();
164
165 /* Send the system reset request to the PMU */
Soren Brinkmann58fbb9b2016-09-02 09:50:54 -0700166 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
Siva Durga Prasad Paladugu1f80d3f2018-04-30 15:56:10 +0530167 pm_get_shutdown_scope());
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800168
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530169 while (1) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800170 wfi();
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530171 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800172}
173
Venkatesh Yadav Abbarapuc9505352022-05-16 17:29:04 +0530174static int zynqmp_validate_power_state(unsigned int power_state,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800175 psci_power_state_t *req_state)
176{
177 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
178
Stefan Krsmanovic3779c5c2016-05-09 18:00:47 +0200179 int pstate = psci_get_pstate_type(power_state);
180
181 assert(req_state);
182
183 /* Sanity check the requested state */
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530184 if (pstate == PSTATE_TYPE_STANDBY) {
Stefan Krsmanovic3779c5c2016-05-09 18:00:47 +0200185 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530186 } else {
Stefan Krsmanovic3779c5c2016-05-09 18:00:47 +0200187 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530188 }
Stefan Krsmanovic3779c5c2016-05-09 18:00:47 +0200189 /* We expect the 'state id' to be zero */
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530190 if (psci_get_pstate_id(power_state)) {
Stefan Krsmanovic3779c5c2016-05-09 18:00:47 +0200191 return PSCI_E_INVALID_PARAMS;
Venkatesh Yadav Abbarapu987fad32022-04-29 13:52:00 +0530192 }
Stefan Krsmanovic3779c5c2016-05-09 18:00:47 +0200193
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800194 return PSCI_E_SUCCESS;
195}
196
Venkatesh Yadav Abbarapuc9505352022-05-16 17:29:04 +0530197static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800198{
199 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
200 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
201}
202
203/*******************************************************************************
204 * Export the platform handlers to enable psci to invoke them
205 ******************************************************************************/
206static const struct plat_psci_ops zynqmp_psci_ops = {
207 .cpu_standby = zynqmp_cpu_standby,
208 .pwr_domain_on = zynqmp_pwr_domain_on,
209 .pwr_domain_off = zynqmp_pwr_domain_off,
210 .pwr_domain_suspend = zynqmp_pwr_domain_suspend,
211 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish,
212 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish,
213 .system_off = zynqmp_system_off,
214 .system_reset = zynqmp_system_reset,
215 .validate_power_state = zynqmp_validate_power_state,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800216 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
217};
218
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800219/*******************************************************************************
220 * Export the platform specific power ops.
221 ******************************************************************************/
222int plat_setup_psci_ops(uintptr_t sec_entrypoint,
223 const struct plat_psci_ops **psci_ops)
224{
225 zynqmp_sec_entry = sec_entrypoint;
226
Siva Durga Prasad Paladugu40808bc2018-04-30 19:43:03 +0530227 *psci_ops = &zynqmp_psci_ops;
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800228
229 return 0;
230}