| Loh Tien Hock | 59400a4 | 2019-02-04 16:17:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __S10_RESETMANAGER_H__ |
| 8 | #define __S10_RESETMANAGER_H__ |
| 9 | |
| 10 | #define S10_RSTMGR_PER0MODRST 0xffd11024 |
| 11 | #define S10_RSTMGR_PER1MODRST 0xffd11028 |
| 12 | #define S10_RSTMGR_HDSKEN 0xffd11010 |
| 13 | |
| 14 | #define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001 |
| 15 | #define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002 |
| 16 | #define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004 |
| 17 | #define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 |
| 18 | #define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 |
| 19 | #define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000 |
| 20 | #define S10_RSTMGR_PER0MODRST_DMA 0x00010000 |
| 21 | #define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001 |
| 22 | #define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002 |
| 23 | #define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 |
| 24 | #define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004 |
| 25 | #define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000 |
| 26 | #define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000 |
| 27 | #define S10_RSTMGR_PER0MODRST_NAND 0x00000020 |
| 28 | #define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 |
| 29 | #define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080 |
| 30 | #define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000 |
| 31 | #define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000 |
| 32 | #define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000 |
| 33 | #define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000 |
| 34 | #define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800 |
| 35 | #define S10_RSTMGR_PER0MODRST_USB0 0x00000008 |
| 36 | #define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000 |
| 37 | #define S10_RSTMGR_PER0MODRST_USB1 0x00000010 |
| 38 | |
| 39 | #define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1 |
| 40 | #define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2 |
| 41 | #define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4 |
| 42 | #define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8 |
| 43 | #define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000 |
| 44 | #define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000 |
| 45 | #define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000 |
| 46 | #define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000 |
| 47 | #define S10_RSTMGR_PER1MODRST_I2C0 0x00000100 |
| 48 | #define S10_RSTMGR_PER1MODRST_I2C0 0x00000100 |
| 49 | #define S10_RSTMGR_PER1MODRST_I2C1 0x00000200 |
| 50 | #define S10_RSTMGR_PER1MODRST_I2C1 0x00000200 |
| 51 | #define S10_RSTMGR_PER1MODRST_I2C2 0x00000400 |
| 52 | #define S10_RSTMGR_PER1MODRST_I2C2 0x00000400 |
| 53 | #define S10_RSTMGR_PER1MODRST_I2C3 0x00000800 |
| 54 | #define S10_RSTMGR_PER1MODRST_I2C3 0x00000800 |
| 55 | #define S10_RSTMGR_PER1MODRST_I2C4 0x00001000 |
| 56 | #define S10_RSTMGR_PER1MODRST_I2C4 0x00001000 |
| 57 | #define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 |
| 58 | #define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 |
| 59 | #define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 |
| 60 | #define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 |
| 61 | #define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 |
| 62 | #define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 |
| 63 | #define S10_RSTMGR_PER1MODRST_UART0 0x00010000 |
| 64 | #define S10_RSTMGR_PER1MODRST_UART0 0x00010000 |
| 65 | #define S10_RSTMGR_PER1MODRST_UART1 0x00020000 |
| 66 | #define S10_RSTMGR_PER1MODRST_UART1 0x00020000 |
| 67 | #define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 |
| 68 | #define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 |
| 69 | #define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004 |
| 70 | #define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 |
| 71 | #define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 |
| 72 | |
| 73 | #define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 |
| 74 | #define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000 |
| 75 | #define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000 |
| 76 | #define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000 |
| 77 | #define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000 |
| 78 | #define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000 |
| 79 | #define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000 |
| 80 | #define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000 |
| 81 | #define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000 |
| 82 | |
| 83 | void deassert_peripheral_reset(void); |
| 84 | void config_hps_hs_before_warm_reset(void); |
| 85 | |
| 86 | #endif |
| 87 | |