blob: 6a4cfdfe332dc051acf3faf8228d4e7396996093 [file] [log] [blame]
johpow01a3810e82021-05-18 15:23:31 -05001/*
2 * Copyright (c) 2021, ARM Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CORTEX_A510_H
8#define CORTEX_A510_H
9
10#define CORTEX_A510_MIDR U(0x410FD460)
11
12/*******************************************************************************
13 * CPU Extended Control register specific definitions
14 ******************************************************************************/
15#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
16
17/*******************************************************************************
18 * CPU Power Control register specific definitions
19 ******************************************************************************/
20#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
21#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
22
23#endif /* CORTEX_A510_H */