blob: 5e2f1da5049cc4edcc9050a4ecba7fe368786162 [file] [log] [blame]
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arch.h>
11#include <common_def.h>
12#include <tbbr_img_def.h>
13#include <utils_def.h>
14
15#include "../rpi3_hw.h"
16
17/* Special value used to verify platform parameters from BL2 to BL31 */
18#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
19
20#define PLATFORM_STACK_SIZE ULL(0x1000)
21
22#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
23#define PLATFORM_CLUSTER_COUNT U(1)
24#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
25#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
26
27#define RPI3_PRIMARY_CPU U(0)
28
29#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
30#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
31 PLATFORM_CORE_COUNT)
32
33#define PLAT_MAX_RET_STATE U(1)
34#define PLAT_MAX_OFF_STATE U(2)
35
36/* Local power state for power domains in Run state. */
37#define PLAT_LOCAL_STATE_RUN U(0)
38/* Local power state for retention. Valid only for CPU power domains */
39#define PLAT_LOCAL_STATE_RET U(1)
40/*
41 * Local power state for OFF/power-down. Valid for CPU and cluster power
42 * domains.
43 */
44#define PLAT_LOCAL_STATE_OFF U(2)
45
46/*
47 * Macros used to parse state information from State-ID if it is using the
48 * recommended encoding for State-ID.
49 */
50#define PLAT_LOCAL_PSTATE_WIDTH U(4)
51#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
52
53/*
54 * Some data must be aligned on the biggest cache line size in the platform.
55 * This is known only to the platform as it might have a combination of
56 * integrated and external caches.
57 */
58#define CACHE_WRITEBACK_SHIFT U(6)
59#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
60
61/*
62 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and
63 * secure DRAM. Note that this is all actually DRAM with different names,
64 * there is no Secure RAM in the Raspberry Pi 3.
65 */
66#define SEC_ROM_BASE ULL(0x00000000)
67#define SEC_ROM_SIZE ULL(0x00010000)
68
69/* FIP placed after ROM to append it to BL1 with very little padding. */
70#define PLAT_RPI3_FIP_BASE ULL(0x00010000)
71#define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001F0000)
72
73/* We have 16M of memory reserved at at 256M */
74#define SEC_SRAM_BASE ULL(0x10000000)
75#define SEC_SRAM_SIZE ULL(0x00100000)
76
77#define SEC_DRAM0_BASE ULL(0x10100000)
78#define SEC_DRAM0_SIZE ULL(0x00200000)
79
80#define NS_DRAM0_BASE ULL(0x10300000)
81#define NS_DRAM0_SIZE ULL(0x00D00000)
82/* End of reserved memory */
83
84/*
85 * BL33 entrypoint.
86 */
87#define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE
88#define PLAT_RPI3_NS_IMAGE_MAX_SIZE NS_DRAM0_SIZE
89
90/*
91 * I/O registers.
92 */
93#define DEVICE0_BASE RPI3_IO_BASE
94#define DEVICE0_SIZE RPI3_IO_SIZE
95
96/*
97 * Arm TF lives in SRAM, partition it here
98 */
99#define SHARED_RAM_BASE SEC_SRAM_BASE
100#define SHARED_RAM_SIZE ULL(0x00001000)
101
102#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
103#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
104
105/*
106 * Mailbox to control the secondary cores.All secondary cores are held in a wait
107 * loop in cold boot. To release them perform the following steps (plus any
108 * additional barriers that may be needed):
109 *
110 * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
111 * *entrypoint = ADDRESS_TO_JUMP_TO;
112 *
113 * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
114 * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
115 *
116 * sev();
117 */
118#define PLAT_RPI3_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
119
120#define PLAT_RPI3_TM_ENTRYPOINT PLAT_RPI3_TRUSTED_MAILBOX_BASE
121#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
122
123#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \
124 PLAT_RPI3_TM_ENTRYPOINT_SIZE)
125#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
126#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
127 PLATFORM_CORE_COUNT)
128
129#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
130 PLAT_RPI3_TM_HOLD_SIZE)
131
132#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
133#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
134
135/*
136 * BL1 specific defines.
137 *
138 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
139 * addresses.
140 *
141 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
142 * the current BL1 RW debug size plus a little space for growth.
143 */
144#define PLAT_MAX_BL1_RW_SIZE ULL(0x12000)
145
146#define BL1_RO_BASE SEC_ROM_BASE
147#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
148#define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE)
149#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
150
151/*
152 * BL2 specific defines.
153 *
154 * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug
155 * size plus a little space for growth.
156 */
157#define PLAT_MAX_BL2_SIZE ULL(0x2C000)
158
159#define BL2_BASE (BL2_LIMIT - PLAT_MAX_BL2_SIZE)
160#define BL2_LIMIT BL31_BASE
161
162/*
163 * BL31 specific defines.
164 *
165 * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
166 * current BL31 debug size plus a little space for growth.
167 */
168#define PLAT_MAX_BL31_SIZE ULL(0x20000)
169
170#define BL31_BASE (BL31_LIMIT - PLAT_MAX_BL31_SIZE)
171#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
172#define BL31_PROGBITS_LIMIT BL1_RW_BASE
173
174/*
175 * BL32 specific defines.
176 *
177 * BL32 can execute from Secure SRAM or Secure DRAM.
178 */
179#define BL32_SRAM_BASE BL_RAM_BASE
180#define BL32_SRAM_LIMIT BL31_BASE
181#define BL32_DRAM_BASE SEC_DRAM0_BASE
182#define BL32_DRAM_LIMIT (SEC_DRAM0_BASE + SEC_DRAM0_SIZE)
183
184#define SEC_SRAM_ID 0
185#define SEC_DRAM_ID 1
186
187#if RPI3_BL32_RAM_LOCATION_ID == SEC_SRAM_ID
188# define BL32_MEM_BASE BL_RAM_BASE
189# define BL32_MEM_SIZE BL_RAM_SIZE
190# define BL32_BASE BL32_SRAM_BASE
191# define BL32_LIMIT BL32_SRAM_LIMIT
192#elif RPI3_BL32_RAM_LOCATION_ID == SEC_DRAM_ID
193# define BL32_MEM_BASE SEC_DRAM0_BASE
194# define BL32_MEM_SIZE SEC_DRAM0_SIZE
195# define BL32_BASE BL32_DRAM_BASE
196# define BL32_LIMIT BL32_DRAM_LIMIT
197#else
198# error "Unsupported RPI3_BL32_RAM_LOCATION_ID value"
199#endif
200#define BL32_SIZE (BL32_LIMIT - BL32_BASE)
201
202#ifdef SPD_none
203#undef BL32_BASE
204#endif /* SPD_none */
205
206/*
207 * Other memory-related defines.
208 */
209#define ADDR_SPACE_SIZE (ULL(1) << 32)
210
211#define MAX_MMAP_REGIONS U(8)
212#define MAX_XLAT_TABLES U(4)
213
214#define MAX_IO_DEVICES U(3)
215#define MAX_IO_HANDLES U(4)
216
217/*
218 * Serial-related constants.
219 */
220#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
221#define PLAT_RPI3_UART_CLK_IN_HZ RPI3_MINI_UART_CLK_IN_HZ
222#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
223
224/*
225 * System counter
226 */
227#define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000)
228
229#endif /* __PLATFORM_DEF_H__ */