blob: 31c5a67e04b55f9540cbf70c5f8c76b5f726f61b [file] [log] [blame]
Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta7c88f3f2014-02-18 18:09:12 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7c88f3f2014-02-18 18:09:12 +00005 */
6
Dan Handleyed6ff952014-05-14 17:44:19 +01007#include <platform_def.h>
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +00008#include <xlat_tables_defs.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +00009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000012ENTRY(tsp_entrypoint)
13
Achin Gupta7c88f3f2014-02-18 18:09:12 +000014
15MEMORY {
Sandrine Bailleux5ac3cc92014-05-20 17:22:24 +010016 RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
Achin Gupta7c88f3f2014-02-18 18:09:12 +000017}
18
19
20SECTIONS
21{
22 . = BL32_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000023 ASSERT(. == ALIGN(PAGE_SIZE),
Achin Gupta7c88f3f2014-02-18 18:09:12 +000024 "BL32_BASE address is not aligned on a page boundary.")
25
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010026#if SEPARATE_CODE_AND_RODATA
27 .text . : {
28 __TEXT_START__ = .;
29 *tsp_entrypoint.o(.text*)
30 *(.text*)
31 *(.vectors)
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000032 . = NEXT(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010033 __TEXT_END__ = .;
34 } >RAM
35
36 .rodata . : {
37 __RODATA_START__ = .;
38 *(.rodata*)
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000039 . = NEXT(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010040 __RODATA_END__ = .;
41 } >RAM
42#else
Achin Gupta7c88f3f2014-02-18 18:09:12 +000043 ro . : {
44 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000045 *tsp_entrypoint.o(.text*)
46 *(.text*)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000047 *(.rodata*)
48 *(.vectors)
49 __RO_END_UNALIGNED__ = .;
50 /*
51 * Memory page(s) mapped to this section will be marked as
52 * read-only, executable. No RW data from the next section must
53 * creep in. Ensure the rest of the current memory page is unused.
54 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000055 . = NEXT(PAGE_SIZE);
Achin Gupta7c88f3f2014-02-18 18:09:12 +000056 __RO_END__ = .;
57 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010058#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +000059
Achin Guptae9c4a642015-09-11 16:03:13 +010060 /*
61 * Define a linker symbol to mark start of the RW memory area for this
62 * image.
63 */
64 __RW_START__ = . ;
65
Achin Gupta7c88f3f2014-02-18 18:09:12 +000066 .data . : {
67 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000068 *(.data*)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000069 __DATA_END__ = .;
70 } >RAM
71
Dan Handley4fd2f5c2014-08-04 11:41:20 +010072#ifdef TSP_PROGBITS_LIMIT
73 ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +010074#endif
75
Achin Gupta7c88f3f2014-02-18 18:09:12 +000076 stacks (NOLOAD) : {
77 __STACKS_START__ = .;
78 *(tzfw_normal_stacks)
79 __STACKS_END__ = .;
80 } >RAM
81
82 /*
83 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +000084 * Its base address should be 16-byte aligned for better performance of the
85 * zero-initialization code.
Achin Gupta7c88f3f2014-02-18 18:09:12 +000086 */
87 .bss : ALIGN(16) {
88 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000089 *(SORT_BY_ALIGNMENT(.bss*))
Achin Gupta7c88f3f2014-02-18 18:09:12 +000090 *(COMMON)
91 __BSS_END__ = .;
92 } >RAM
93
94 /*
95 * The xlat_table section is for full, aligned page tables (4K).
96 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000097 * the .bss section. The tables are initialized to zero by the translation
98 * tables library.
Achin Gupta7c88f3f2014-02-18 18:09:12 +000099 */
100 xlat_table (NOLOAD) : {
101 *(xlat_table)
102 } >RAM
103
Soby Mathew2ae20432015-01-08 18:02:44 +0000104#if USE_COHERENT_MEM
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000105 /*
106 * The base address of the coherent memory section must be page-aligned (4K)
107 * to guarantee that the coherent data are stored on their own pages and
108 * are not mixed with normal data. This is required to set up the correct
109 * memory attributes for the coherent data page tables.
110 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000111 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000112 __COHERENT_RAM_START__ = .;
113 *(tzfw_coherent_mem)
114 __COHERENT_RAM_END_UNALIGNED__ = .;
115 /*
116 * Memory page(s) mapped to this section will be marked
117 * as device memory. No other unexpected data must creep in.
118 * Ensure the rest of the current memory page is unused.
119 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000120 . = NEXT(PAGE_SIZE);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000121 __COHERENT_RAM_END__ = .;
122 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000123#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000124
Achin Guptae9c4a642015-09-11 16:03:13 +0100125 /*
126 * Define a linker symbol to mark the end of the RW memory area for this
127 * image.
128 */
129 __RW_END__ = .;
Sandrine Bailleuxe701e302014-05-20 17:28:25 +0100130 __BL32_END__ = .;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000131
132 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000133#if USE_COHERENT_MEM
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000134 __COHERENT_RAM_UNALIGNED_SIZE__ =
135 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000136#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000137
Juan Castillo7d199412015-12-14 09:35:25 +0000138 ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000139}