tony.xie | 54973e7 | 2017-04-24 16:18:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __SOC_H__ |
| 32 | #define __SOC_H__ |
| 33 | |
| 34 | /******************************* stimer ***************************************/ |
| 35 | #define TIMER_LOADE_COUNT0 0x00 |
| 36 | #define TIMER_LOADE_COUNT1 0x04 |
| 37 | #define TIMER_CURRENT_VALUE0 0x08 |
| 38 | #define TIMER_CURRENT_VALUE1 0x0C |
| 39 | #define TIMER_CONTROL_REG 0x10 |
| 40 | #define TIMER_INTSTATUS 0x18 |
| 41 | #define TIMER_EN 0x1 |
| 42 | |
| 43 | extern const unsigned char rockchip_power_domain_tree_desc[]; |
| 44 | |
| 45 | /**************************** read/write **************************************/ |
| 46 | #ifndef BITS_WMSK |
| 47 | #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) |
| 48 | #endif |
| 49 | |
| 50 | /**************************** cru *********************************************/ |
| 51 | enum plls_id { |
| 52 | APLL_ID = 0, |
| 53 | DPLL_ID, |
| 54 | CPLL_ID, |
| 55 | GPLL_ID, |
| 56 | REVERVE, |
| 57 | NPLL_ID, |
| 58 | MAX_PLL, |
| 59 | }; |
| 60 | |
| 61 | #define CRU_CRU_MODE 0x0080 |
| 62 | #define CRU_CRU_MISC 0x0084 |
| 63 | #define CRU_GLB_SRST_FST 0x009c |
| 64 | #define CRU_GLB_SRST_FST_VALUE 0xfdb9 |
| 65 | #define PLL_CONS(id, i) (0x020 * (id) + ((i) * 4)) |
| 66 | #define CRU_CLKSEL_CON(i) (0x100 + ((i) * 4)) |
| 67 | #define CRU_CLKSEL_NUMS 53 |
| 68 | #define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4)) |
| 69 | #define CRU_CLKGATE_NUMS 29 |
| 70 | #define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4)) |
| 71 | #define CRU_SOFTRSTS_NUMS 12 |
| 72 | #define CRU_PLL_CON_NUMS 5 |
| 73 | |
| 74 | /* PLLn_CON1 */ |
| 75 | #define PLL_IS_LOCKED BIT(10) |
| 76 | /* PLLn_CON0 */ |
| 77 | #define PLL_BYPASS BITS_WITH_WMASK(1, 0x1, 15) |
| 78 | #define PLL_NO_BYPASS BITS_WITH_WMASK(0, 0x1, 15) |
| 79 | /* CRU_MODE */ |
| 80 | #define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \ |
| 81 | BITS_WITH_WMASK(0, 0x1, 1) : \ |
| 82 | BITS_WITH_WMASK(0, 0x1, ((id) * 4)) |
| 83 | #define PLL_NORM_MODE(id) ((id) == NPLL_ID) ? \ |
| 84 | BITS_WITH_WMASK(1, 0x1, 1) : \ |
| 85 | BITS_WITH_WMASK(1, 0x1, ((id) * 4)) |
| 86 | |
| 87 | #define CRU_GATEID_CONS(ID) (0x200 + (ID / 16) * 4) |
| 88 | #define CRU_CONS_GATEID(i) (16 * (i)) |
| 89 | #define GATE_ID(reg, bit) ((reg * 16) + bit) |
| 90 | |
| 91 | #define PLL_LOCKED_TIMEOUT 600000U |
| 92 | |
| 93 | #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) |
| 94 | /************************** config regs ***************************************/ |
| 95 | #define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4) |
| 96 | #define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4) |
| 97 | #define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * 4) |
| 98 | #define FIREWALL_DDR_FW_DDR_CON_REG (0x040) |
| 99 | #define GRF_SOC_CON(n) (0x400 + (n) * 4) |
| 100 | #define GRF_SOC_STATUS(n) (0x480 + (n) * 4) |
| 101 | #define GRF_CPU_STATUS(n) (0x520 + (n) * 4) |
| 102 | #define GRF_OS_REG(n) (0x5c8 + (n) * 4) |
| 103 | #define DDRGRF_SOC_CON(n) (0x000 + (n) * 4) |
| 104 | #define DDRGRF_SOC_STATUS(n) (0x100 + (n) * 4) |
| 105 | #define SGRF_SOC_CON(n) (0x000 + (n) * 4) |
| 106 | #define SGRF_DMAC_CON(n) (0x100 + (n) * 4) |
| 107 | #define SGRF_HDCP_KEY_CON(n) (0x280 + (n) * 4) |
| 108 | |
| 109 | #define DDR_PCTL2_PWRCTL 0x30 |
| 110 | /************************** regs func *****************************************/ |
| 111 | #define STIMER_S BIT(23) |
| 112 | #define SGRF_SLV_S_ALL_NS 0x0 |
| 113 | #define SGRF_MST_S_ALL_NS 0xffffffff |
| 114 | #define DMA_IRQ_BOOT_NS 0xffffffff |
| 115 | #define DMA_MANAGER_BOOT_NS 0x80008000 |
| 116 | #define DMA_PERI_CH_NS_15_0 0xffffffff |
| 117 | #define DMA_PERI_CH_NS_19_16 0x000f000f |
| 118 | #define DMA_SOFTRST_REQ 0x01000100 |
| 119 | #define DMA_SOFTRST_RLS 0x01000000 |
| 120 | |
| 121 | #define SELFREF_EN BIT(0) |
| 122 | /************************** cpu ***********************************************/ |
| 123 | #define CPU_BOOT_ADDR_WMASK 0xffff0000 |
| 124 | #define CPU_BOOT_ADDR_ALIGN 16 |
| 125 | |
| 126 | /************************** ddr secure region *********************************/ |
| 127 | #define PLAT_MAX_DDR_CAPACITY_MB 4096 |
| 128 | #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) |
| 129 | |
| 130 | /************************** gpio2_d2 ******************************************/ |
| 131 | #define SWPORTA_DR 0x00 |
| 132 | #define SWPORTA_DDR 0x04 |
| 133 | #define GPIO2_D2 BIT(26) |
| 134 | #define GPIO2_D2_GPIO_MODE 0x30 |
| 135 | #define GRF_GPIO2D_IOMUX 0x34 |
| 136 | |
| 137 | #endif /* __SOC_H__ */ |