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Soby Mathewec8ac1c2016-05-05 14:32:05 +01001/*
Masahiro Yamada0b67e562020-03-09 17:39:48 +09002 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
Soby Mathewec8ac1c2016-05-05 14:32:05 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewec8ac1c2016-05-05 14:32:05 +01005 */
6
7#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Masahiro Yamada0b67e562020-03-09 17:39:48 +09009#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/xlat_tables/xlat_tables_defs.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010011
12OUTPUT_FORMAT(elf32-littlearm)
13OUTPUT_ARCH(arm)
14ENTRY(sp_min_vector_table)
15
16MEMORY {
17 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
18}
19
Heiko Stuebner95ba3552019-04-11 15:26:07 +020020#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT
21#include <plat_sp_min.ld.S>
22#endif
Soby Mathewec8ac1c2016-05-05 14:32:05 +010023
24SECTIONS
25{
26 . = BL32_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000027 ASSERT(. == ALIGN(PAGE_SIZE),
Soby Mathewec8ac1c2016-05-05 14:32:05 +010028 "BL32_BASE address is not aligned on a page boundary.")
29
30#if SEPARATE_CODE_AND_RODATA
31 .text . : {
32 __TEXT_START__ = .;
33 *entrypoint.o(.text*)
34 *(.text*)
Yatharth Kochar06460cd2016-06-30 15:02:31 +010035 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010036 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +010037 __TEXT_END__ = .;
38 } >RAM
39
Roberto Vargas1d04c632018-05-10 11:01:16 +010040 /* .ARM.extab and .ARM.exidx are only added because Clang need them */
41 .ARM.extab . : {
42 *(.ARM.extab* .gnu.linkonce.armextab.*)
43 } >RAM
44
45 .ARM.exidx . : {
46 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
47 } >RAM
48
Soby Mathewec8ac1c2016-05-05 14:32:05 +010049 .rodata . : {
50 __RODATA_START__ = .;
51 *(.rodata*)
52
53 /* Ensure 4-byte alignment for descriptors and ensure inclusion */
54 . = ALIGN(4);
55 __RT_SVC_DESCS_START__ = .;
56 KEEP(*(rt_svc_descs))
57 __RT_SVC_DESCS_END__ = .;
58
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -060059 . = ALIGN(8);
60 __FCONF_POPULATOR_START__ = .;
61 KEEP(*(.fconf_populator))
62 __FCONF_POPULATOR_END__ = .;
63
Bence Szépkúti78dc10c2019-11-07 12:09:24 +010064#if ENABLE_PMF
65 /* Ensure 4-byte alignment for descriptors and ensure inclusion */
66 . = ALIGN(4);
67 __PMF_SVC_DESCS_START__ = .;
68 KEEP(*(pmf_svc_descs))
69 __PMF_SVC_DESCS_END__ = .;
70#endif /* ENABLE_PMF */
71
Soby Mathewec8ac1c2016-05-05 14:32:05 +010072 /*
73 * Ensure 4-byte alignment for cpu_ops so that its fields are also
74 * aligned. Also ensure cpu_ops inclusion.
75 */
76 . = ALIGN(4);
77 __CPU_OPS_START__ = .;
78 KEEP(*(cpu_ops))
79 __CPU_OPS_END__ = .;
80
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010081 /* Place pubsub sections for events */
82 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000083#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010084
Roberto Vargasd93fde32018-04-11 11:53:31 +010085 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +010086 __RODATA_END__ = .;
87 } >RAM
88#else
89 ro . : {
90 __RO_START__ = .;
91 *entrypoint.o(.text*)
92 *(.text*)
93 *(.rodata*)
94
95 /* Ensure 4-byte alignment for descriptors and ensure inclusion */
96 . = ALIGN(4);
97 __RT_SVC_DESCS_START__ = .;
98 KEEP(*(rt_svc_descs))
99 __RT_SVC_DESCS_END__ = .;
100
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600101 . = ALIGN(8);
102 __FCONF_POPULATOR_START__ = .;
103 KEEP(*(.fconf_populator))
104 __FCONF_POPULATOR_END__ = .;
105
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100106 /*
107 * Ensure 4-byte alignment for cpu_ops so that its fields are also
108 * aligned. Also ensure cpu_ops inclusion.
109 */
110 . = ALIGN(4);
111 __CPU_OPS_START__ = .;
112 KEEP(*(cpu_ops))
113 __CPU_OPS_END__ = .;
114
Jeenu Viswambharane3f22002017-09-22 08:32:10 +0100115 /* Place pubsub sections for events */
116 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000117#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +0100118
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100119 *(.vectors)
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100120 __RO_END_UNALIGNED__ = .;
121
122 /*
123 * Memory page(s) mapped to this section will be marked as
124 * read-only, executable. No RW data from the next section must
125 * creep in. Ensure the rest of the current memory block is unused.
126 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100127 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100128 __RO_END__ = .;
129 } >RAM
130#endif
131
132 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
133 "cpu_ops not defined for this platform.")
134 /*
135 * Define a linker symbol to mark start of the RW memory area for this
136 * image.
137 */
138 __RW_START__ = . ;
139
140 .data . : {
141 __DATA_START__ = .;
142 *(.data*)
143 __DATA_END__ = .;
144 } >RAM
145
Soby Mathewbf169232017-11-14 14:10:10 +0000146#ifdef BL32_PROGBITS_LIMIT
147 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
148#endif
149
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100150 stacks (NOLOAD) : {
151 __STACKS_START__ = .;
152 *(tzfw_normal_stacks)
153 __STACKS_END__ = .;
154 } >RAM
155
156 /*
157 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000158 * Its base address should be 8-byte aligned for better performance of the
159 * zero-initialization code.
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100160 */
Douglas Raillard21362a92016-12-02 13:51:54 +0000161 .bss (NOLOAD) : ALIGN(8) {
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100162 __BSS_START__ = .;
163 *(.bss*)
164 *(COMMON)
165#if !USE_COHERENT_MEM
166 /*
167 * Bakery locks are stored in normal .bss memory
168 *
169 * Each lock's data is spread across multiple cache lines, one per CPU,
170 * but multiple locks can share the same cache line.
171 * The compiler will allocate enough memory for one CPU's bakery locks,
172 * the remaining cache lines are allocated by the linker script
173 */
174 . = ALIGN(CACHE_WRITEBACK_GRANULE);
175 __BAKERY_LOCK_START__ = .;
Varun Wadekar77c382c2019-01-30 08:26:20 -0800176 __PERCPU_BAKERY_LOCK_START__ = .;
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100177 *(bakery_lock)
178 . = ALIGN(CACHE_WRITEBACK_GRANULE);
Varun Wadekar77c382c2019-01-30 08:26:20 -0800179 __PERCPU_BAKERY_LOCK_END__ = .;
180 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100181 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
182 __BAKERY_LOCK_END__ = .;
183#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
184 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
185 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
186#endif
187#endif
188
189#if ENABLE_PMF
190 /*
191 * Time-stamps are stored in normal .bss memory
192 *
193 * The compiler will allocate enough memory for one CPU's time-stamps,
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000194 * the remaining memory for other CPUs is allocated by the
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100195 * linker script
196 */
197 . = ALIGN(CACHE_WRITEBACK_GRANULE);
198 __PMF_TIMESTAMP_START__ = .;
199 KEEP(*(pmf_timestamp_array))
200 . = ALIGN(CACHE_WRITEBACK_GRANULE);
201 __PMF_PERCPU_TIMESTAMP_END__ = .;
202 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
203 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
204 __PMF_TIMESTAMP_END__ = .;
205#endif /* ENABLE_PMF */
206
207 __BSS_END__ = .;
208 } >RAM
209
Masahiro Yamada0b67e562020-03-09 17:39:48 +0900210 XLAT_TABLE_SECTION >RAM
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100211
212 __BSS_SIZE__ = SIZEOF(.bss);
213
214#if USE_COHERENT_MEM
215 /*
216 * The base address of the coherent memory section must be page-aligned (4K)
217 * to guarantee that the coherent data are stored on their own pages and
218 * are not mixed with normal data. This is required to set up the correct
219 * memory attributes for the coherent data page tables.
220 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000221 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100222 __COHERENT_RAM_START__ = .;
223 /*
224 * Bakery locks are stored in coherent memory
225 *
226 * Each lock's data is contiguous and fully allocated by the compiler
227 */
228 *(bakery_lock)
229 *(tzfw_coherent_mem)
230 __COHERENT_RAM_END_UNALIGNED__ = .;
231 /*
232 * Memory page(s) mapped to this section will be marked
233 * as device memory. No other unexpected data must creep in.
234 * Ensure the rest of the current memory page is unused.
235 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100236 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100237 __COHERENT_RAM_END__ = .;
238 } >RAM
239
240 __COHERENT_RAM_UNALIGNED_SIZE__ =
241 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
242#endif
243
244 /*
245 * Define a linker symbol to mark end of the RW memory area for this
246 * image.
247 */
248 __RW_END__ = .;
249
250 __BL32_END__ = .;
251}