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developer550bf5e2016-07-11 16:05:23 +08001/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
developer550bf5e2016-07-11 16:05:23 +08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
developer550bf5e2016-07-11 16:05:23 +08005 */
Isla Mitchelle3631462017-07-14 10:46:32 +01006#include <arch_helpers.h>
developer550bf5e2016-07-11 16:05:23 +08007#include <assert.h>
developer550bf5e2016-07-11 16:05:23 +08008#include <bl_common.h>
9#include <cci.h>
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090010#include <common_def.h>
developer550bf5e2016-07-11 16:05:23 +080011#include <console.h>
12#include <context_mgmt.h>
13#include <debug.h>
14#include <generic_delay_timer.h>
15#include <mcucfg.h>
16#include <mmio.h>
developer550bf5e2016-07-11 16:05:23 +080017#include <mt_cpuxgpt.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010018#include <mtk_plat_common.h>
19#include <mtk_sip_svc.h>
developer550bf5e2016-07-11 16:05:23 +080020#include <plat_private.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010021#include <platform.h>
developer550bf5e2016-07-11 16:05:23 +080022#include <string.h>
Joel Hutton5cc3bc82018-03-21 11:40:57 +000023#include <utils_def.h>
developer550bf5e2016-07-11 16:05:23 +080024#include <xlat_tables.h>
Joel Hutton5cc3bc82018-03-21 11:40:57 +000025
developer550bf5e2016-07-11 16:05:23 +080026/*******************************************************************************
27 * Declarations of linker defined symbols which will help us find the layout
28 * of trusted SRAM
29 ******************************************************************************/
developer550bf5e2016-07-11 16:05:23 +080030/*
31 * The next 2 constants identify the extents of the code & RO data region.
32 * These addresses are used by the MMU setup code and therefore they must be
33 * page-aligned. It is the responsibility of the linker script to ensure that
34 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
35 */
Joel Hutton5cc3bc82018-03-21 11:40:57 +000036IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE);
37IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT);
developer550bf5e2016-07-11 16:05:23 +080038
39/*
developer550bf5e2016-07-11 16:05:23 +080040 * Placeholder variables for copying the arguments that have been passed to
41 * BL3-1 from BL2.
42 */
43static entry_point_info_t bl32_image_ep_info;
44static entry_point_info_t bl33_image_ep_info;
45
46static const int cci_map[] = {
47 PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX,
48 PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX
49};
50
51static uint32_t cci_map_length = ARRAY_SIZE(cci_map);
52
53/* Table of regions to map using the MMU. */
54static const mmap_region_t plat_mmap[] = {
55 /* for TF text, RO, RW */
56 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
57 MT_DEVICE | MT_RW | MT_SECURE),
58 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
59 MT_DEVICE | MT_RW | MT_SECURE),
60 MAP_REGION_FLAT(RAM_CONSOLE_BASE & ~(PAGE_SIZE_MASK), RAM_CONSOLE_SIZE,
61 MT_DEVICE | MT_RW | MT_NS),
62 { 0 }
63
64};
65
66/*******************************************************************************
67 * Macro generating the code for the function setting up the pagetables as per
68 * the platform memory map & initialize the mmu, for the given exception level
69 ******************************************************************************/
70#define DEFINE_CONFIGURE_MMU_EL(_el) \
71 void plat_configure_mmu_el ## _el(unsigned long total_base, \
72 unsigned long total_size, \
73 unsigned long ro_start, \
74 unsigned long ro_limit, \
75 unsigned long coh_start, \
76 unsigned long coh_limit) \
77 { \
78 mmap_add_region(total_base, total_base, \
79 total_size, \
80 MT_MEMORY | MT_RW | MT_SECURE); \
81 mmap_add_region(ro_start, ro_start, \
82 ro_limit - ro_start, \
83 MT_MEMORY | MT_RO | MT_SECURE); \
84 mmap_add_region(coh_start, coh_start, \
85 coh_limit - coh_start, \
86 MT_DEVICE | MT_RW | MT_SECURE); \
87 mmap_add(plat_mmap); \
88 init_xlat_tables(); \
89 \
90 enable_mmu_el ## _el(0); \
91 }
92
93/* Define EL3 variants of the function initialising the MMU */
94DEFINE_CONFIGURE_MMU_EL(3)
95
96unsigned int plat_get_syscnt_freq2(void)
97{
98 return SYS_COUNTER_FREQ_IN_TICKS;
99}
100
101void plat_cci_init(void)
102{
103 /* Initialize CCI driver */
104 cci_init(PLAT_MT_CCI_BASE, cci_map, cci_map_length);
105}
106
107void plat_cci_enable(void)
108{
109 /*
110 * Enable CCI coherency for this cluster.
111 * No need for locks as no other cpu is active at the moment.
112 */
113 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
114}
115
116void plat_cci_disable(void)
117{
118 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
119}
120
121
122static void platform_setup_cpu(void)
123{
124 /* setup big cores */
125 mmio_write_32((uintptr_t)&mt6795_mcucfg->mp1_config_res,
126 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
127 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
128 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
129 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
130 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
131 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, MP1_AINACTS);
132 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_clkenm_div,
133 MP1_SW_CG_GEN);
134 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl,
135 MP1_L2RSTDISABLE);
136
137 /* set big cores arm64 boot mode */
138 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_cpucfg,
139 MP1_CPUCFG_64BIT);
140
141 /* set LITTLE cores arm64 boot mode */
142 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_rv_addr[0].rv_addr_hw,
143 MP0_CPUCFG_64BIT);
144}
145
146/*******************************************************************************
147 * Return a pointer to the 'entry_point_info' structure of the next image for
148 * the security state specified. BL33 corresponds to the non-secure image type
149 * while BL32 corresponds to the secure image type. A NULL pointer is returned
150 * if the image does not exist.
151 ******************************************************************************/
152entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
153{
154 entry_point_info_t *next_image_info;
155
156 next_image_info = (type == NON_SECURE) ?
157 &bl33_image_ep_info : &bl32_image_ep_info;
158
159 /* None of the images on this platform can have 0x0 as the entrypoint */
160 if (next_image_info->pc)
161 return next_image_info;
162 else
163 return NULL;
164}
165
166/*******************************************************************************
167 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
168 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
169 * are lost (potentially). This needs to be done before the MMU is initialized
170 * so that the memory layout can be used while creating page tables.
171 * BL2 has flushed this information to memory, so we are guaranteed to pick up
172 * good data.
173 ******************************************************************************/
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100174void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
175 u_register_t arg2, u_register_t arg3)
developer550bf5e2016-07-11 16:05:23 +0800176{
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100177 struct mtk_bl_param_t *pmtk_bl_param = (struct mtk_bl_param_t *)arg0;
developer550bf5e2016-07-11 16:05:23 +0800178 struct atf_arg_t *teearg;
179 unsigned long long normal_base;
180 unsigned long long atf_base;
181
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100182 assert(pmtk_bl_param != NULL);
developer550bf5e2016-07-11 16:05:23 +0800183 /*
184 * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits
185 * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit
186 * to 64 bit state. So we need to clear high 32bit,
187 * which may be random value.
188 */
189 pmtk_bl_param =
190 (struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff);
developer550bf5e2016-07-11 16:05:23 +0800191
192 teearg = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr;
193
194 console_init(teearg->atf_log_port, UART_CLOCK, UART_BAUDRATE);
195 memcpy((void *)&gteearg, (void *)teearg, sizeof(struct atf_arg_t));
196
197 normal_base = 0;
198 /* in ATF boot time, timer for cntpct_el0 is not initialized
199 * so it will not count now.
200 */
201 atf_base = read_cntpct_el0();
202 sched_clock_init(normal_base, atf_base);
203
204 VERBOSE("bl31_setup\n");
205
206 /* Populate entry point information for BL3-2 and BL3-3 */
207 SET_PARAM_HEAD(&bl32_image_ep_info,
208 PARAM_EP,
209 VERSION_1,
210 0);
211 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
212 bl32_image_ep_info.pc = BL32_BASE;
213
214 SET_PARAM_HEAD(&bl33_image_ep_info,
215 PARAM_EP,
216 VERSION_1,
217 0);
218 /*
219 * Tell BL3-1 where the non-trusted software image
220 * is located and the entry state information
221 */
222 /* BL33_START_ADDRESS */
223 bl33_image_ep_info.pc = pmtk_bl_param->bl33_start_addr;
224 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry();
225 bl33_image_ep_info.args.arg4 = pmtk_bl_param->bootarg_loc;
226 bl33_image_ep_info.args.arg5 = pmtk_bl_param->bootarg_size;
227 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
228}
229/*******************************************************************************
230 * Perform any BL3-1 platform setup code
231 ******************************************************************************/
232
233void bl31_platform_setup(void)
234{
235 platform_setup_cpu();
236
237 generic_delay_timer_init();
238
239 plat_mt_gic_driver_init();
240 /* Initialize the gic cpu and distributor interfaces */
241 plat_mt_gic_init();
242
243 /* Topologies are best known to the platform. */
244 mt_setup_topology();
245}
246/*******************************************************************************
247 * Perform the very early platform specific architectural setup here. At the
248 * moment this is only intializes the mmu in a quick and dirty way.
249 * Init MTK propiartary log buffer control field.
250 ******************************************************************************/
251void bl31_plat_arch_setup(void)
252{
253 /* Enable non-secure access to CCI-400 registers */
254 mmio_write_32(CCI400_BASE + CCI_SEC_ACCESS_OFFSET, 0x1);
255
256 plat_cci_init();
257 plat_cci_enable();
258
259 if (gteearg.atf_log_buf_size != 0) {
260 INFO("mmap atf buffer : 0x%x, 0x%x\n\r",
261 gteearg.atf_log_buf_start,
262 gteearg.atf_log_buf_size);
263
264 mmap_add_region(
265 gteearg.atf_log_buf_start &
266 ~(PAGE_SIZE_2MB_MASK),
267 gteearg.atf_log_buf_start &
268 ~(PAGE_SIZE_2MB_MASK),
269 PAGE_SIZE_2MB,
270 MT_DEVICE | MT_RW | MT_NS);
271
272 INFO("mmap atf buffer (force 2MB aligned):0x%x, 0x%x\n",
273 (gteearg.atf_log_buf_start & ~(PAGE_SIZE_2MB_MASK)),
274 PAGE_SIZE_2MB);
275 }
276 /*
277 * add TZRAM_BASE to memory map
278 * then set RO and COHERENT to different attribute
279 */
280 plat_configure_mmu_el3(
281 (TZRAM_BASE & ~(PAGE_SIZE_MASK)),
282 (TZRAM_SIZE & ~(PAGE_SIZE_MASK)),
283 (BL31_RO_BASE & ~(PAGE_SIZE_MASK)),
284 BL31_RO_LIMIT,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900285 BL_COHERENT_RAM_BASE,
286 BL_COHERENT_RAM_END);
developer550bf5e2016-07-11 16:05:23 +0800287 /* Initialize for ATF log buffer */
288 if (gteearg.atf_log_buf_size != 0) {
289 gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
290 gteearg.atf_aee_debug_buf_start =
291 gteearg.atf_log_buf_start +
292 gteearg.atf_log_buf_size - ATF_AEE_BUFFER_SIZE;
293 INFO("ATF log service is registered (0x%x, aee:0x%x)\n",
294 gteearg.atf_log_buf_start,
295 gteearg.atf_aee_debug_buf_start);
296 } else{
297 gteearg.atf_aee_debug_buf_size = 0;
298 gteearg.atf_aee_debug_buf_start = 0;
299 }
300
301 /* Platform code before bl31_main */
302 /* compatible to the earlier chipset */
303
304 /* Show to ATF log buffer & UART */
305 INFO("BL3-1: %s\n", version_string);
306 INFO("BL3-1: %s\n", build_message);
307
308}
309#if 0
310/* MTK Define */
311#define ACTLR_CPUECTLR_BIT (1 << 1)
312
313void enable_ns_access_to_cpuectlr(void)
314{
315 unsigned int next_actlr;
316
317
318 /* ACTLR_EL1 do not implement CUPECTLR */
319 next_actlr = read_actlr_el2();
320 next_actlr |= ACTLR_CPUECTLR_BIT;
321 write_actlr_el2(next_actlr);
322
323 next_actlr = read_actlr_el3();
324 next_actlr |= ACTLR_CPUECTLR_BIT;
325 write_actlr_el3(next_actlr);
326}
327#endif
328/*******************************************************************************
329 * This function prepare boot argument for 64 bit kernel entry
330 ******************************************************************************/
331static entry_point_info_t *bl31_plat_get_next_kernel64_ep_info(void)
332{
333 entry_point_info_t *next_image_info;
developer550bf5e2016-07-11 16:05:23 +0800334 unsigned int mode;
335
developer550bf5e2016-07-11 16:05:23 +0800336 mode = 0;
337
338 /* Kernel image is always non-secured */
339 next_image_info = &bl33_image_ep_info;
340
341 /* Figure out what mode we enter the non-secure world in */
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000342 if (EL_IMPLEMENTED(2)) {
developer550bf5e2016-07-11 16:05:23 +0800343 INFO("Kernel_EL2\n");
344 mode = MODE_EL2;
345 } else{
346 INFO("Kernel_EL1\n");
347 mode = MODE_EL1;
348 }
349
350 INFO("Kernel is 64Bit\n");
351 next_image_info->spsr =
352 SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
353 next_image_info->pc = get_kernel_info_pc();
354 next_image_info->args.arg0 = get_kernel_info_r0();
355 next_image_info->args.arg1 = get_kernel_info_r1();
356
357 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx\n",
358 next_image_info->pc,
359 next_image_info->args.arg0,
360 next_image_info->args.arg1);
361
362
363 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE);
364
365 /* None of the images on this platform can have 0x0 as the entrypoint */
366 if (next_image_info->pc)
367 return next_image_info;
368 else
369 return NULL;
370}
371
372/*******************************************************************************
373 * This function prepare boot argument for 32 bit kernel entry
374 ******************************************************************************/
375static entry_point_info_t *bl31_plat_get_next_kernel32_ep_info(void)
376{
377 entry_point_info_t *next_image_info;
378 unsigned int mode;
379
380 mode = 0;
381
382 /* Kernel image is always non-secured */
383 next_image_info = &bl33_image_ep_info;
384
385 /* Figure out what mode we enter the non-secure world in */
386 mode = MODE32_hyp;
387 /*
388 * TODO: Consider the possibility of specifying the SPSR in
389 * the FIP ToC and allowing the platform to have a say as
390 * well.
391 */
392
393 INFO("Kernel is 32Bit\n");
394 next_image_info->spsr =
395 SPSR_MODE32(mode, SPSR_T_ARM, SPSR_E_LITTLE,
396 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT));
397 next_image_info->pc = get_kernel_info_pc();
398 next_image_info->args.arg0 = get_kernel_info_r0();
399 next_image_info->args.arg1 = get_kernel_info_r1();
400 next_image_info->args.arg2 = get_kernel_info_r2();
401
402 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx, r2=0x%lx\n",
403 next_image_info->pc,
404 next_image_info->args.arg0,
405 next_image_info->args.arg1,
406 next_image_info->args.arg2);
407
408
409 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE);
410
411 /* None of the images on this platform can have 0x0 as the entrypoint */
412 if (next_image_info->pc)
413 return next_image_info;
414 else
415 return NULL;
416}
417
418/*******************************************************************************
419 * This function prepare boot argument for kernel entrypoint
420 ******************************************************************************/
421void bl31_prepare_kernel_entry(uint64_t k32_64)
422{
423 entry_point_info_t *next_image_info;
424 uint32_t image_type;
425
426 /* Determine which image to execute next */
427 /* image_type = bl31_get_next_image_type(); */
428 image_type = NON_SECURE;
429
430 /* Program EL3 registers to enable entry into the next EL */
431 if (k32_64 == 0)
432 next_image_info = bl31_plat_get_next_kernel32_ep_info();
433 else
434 next_image_info = bl31_plat_get_next_kernel64_ep_info();
435
436 assert(next_image_info);
437 assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
438
439 INFO("BL3-1: Preparing for EL3 exit to %s world, Kernel\n",
440 (image_type == SECURE) ? "secure" : "normal");
441 INFO("BL3-1: Next image address = 0x%llx\n",
442 (unsigned long long) next_image_info->pc);
443 INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr);
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100444 cm_init_my_context(next_image_info);
developer550bf5e2016-07-11 16:05:23 +0800445 cm_prepare_el3_exit(image_type);
446}