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Jacky Bai4d93d1d2020-07-02 14:39:58 +08001/*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <stdbool.h>
9
10#include <arch_helpers.h>
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <context.h>
14#include <drivers/console.h>
15#include <drivers/generic_delay_timer.h>
16#include <lib/el3_runtime/context_mgmt.h>
17#include <lib/mmio.h>
18#include <lib/xlat_tables/xlat_tables_v2.h>
19#include <plat/common/platform.h>
20#include <platform_def.h>
21
22#include <imx8_lpuart.h>
Pankaj Gupta862f57a2021-08-04 15:42:51 +053023#include <imx8ulp_caam.h>
Jacky Bai4d93d1d2020-07-02 14:39:58 +080024#include <imx_plat_common.h>
25#include <plat_imx8.h>
26#include <upower_api.h>
Jacky Bai7ec94512023-09-21 14:01:37 +080027#include <xrdc.h>
Jacky Bai4d93d1d2020-07-02 14:39:58 +080028
29#define MAP_BL31_TOTAL \
30 MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE)
31#define MAP_BL31_RO \
32 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
33
34#define MAP_COHERENT_MEM \
35 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), \
36 MT_DEVICE | MT_RW | MT_SECURE)
37
38static const mmap_region_t imx_mmap[] = {
39 DEVICE0_MAP, DEVICE1_MAP, ELE_MAP,
40 SEC_SIM_MAP, SRAM0_MAP,
41 {0}
42};
43
44extern uint32_t upower_init(void);
45extern void imx8ulp_init_scmi_server(void);
46
47static entry_point_info_t bl32_image_ep_info;
48static entry_point_info_t bl33_image_ep_info;
49
50void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
51 u_register_t arg2, u_register_t arg3)
52{
53 static console_t console;
54
Jacky Baic6fb6672023-09-18 22:08:52 +080055 /* config the TPM5 clock */
56 mmio_write_32(IMX_PCC3_BASE + 0xd0, 0x92000000);
57 mmio_write_32(IMX_PCC3_BASE + 0xd0, 0xd2000000);
Jacky Bai4d93d1d2020-07-02 14:39:58 +080058
59 /* enable the GPIO D,E,F non-secure access by default */
60 mmio_write_32(IMX_PCC4_BASE + 0x78, 0xc0000000);
61 mmio_write_32(IMX_PCC4_BASE + 0x7c, 0xc0000000);
62 mmio_write_32(IMX_PCC5_BASE + 0x114, 0xc0000000);
63
64 mmio_write_32(IMX_GPIOE_BASE + 0x10, 0xffffffff);
65 mmio_write_32(IMX_GPIOE_BASE + 0x14, 0x3);
66 mmio_write_32(IMX_GPIOE_BASE + 0x18, 0xffffffff);
67 mmio_write_32(IMX_GPIOE_BASE + 0x1c, 0x3);
68
69 mmio_write_32(IMX_GPIOF_BASE + 0x10, 0xffffffff);
70 mmio_write_32(IMX_GPIOF_BASE + 0x14, 0x3);
71 mmio_write_32(IMX_GPIOF_BASE + 0x18, 0xffffffff);
72 mmio_write_32(IMX_GPIOF_BASE + 0x1c, 0x3);
73
74 mmio_write_32(IMX_GPIOD_BASE + 0x10, 0xffffffff);
75 mmio_write_32(IMX_GPIOD_BASE + 0x14, 0x3);
76 mmio_write_32(IMX_GPIOD_BASE + 0x18, 0xffffffff);
77 mmio_write_32(IMX_GPIOD_BASE + 0x1c, 0x3);
78
79 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
80 IMX_CONSOLE_BAUDRATE, &console);
81
82 /* This console is only used for boot stage */
83 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
84
85 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
86 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry();
87 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
88}
89
90void bl31_plat_arch_setup(void)
91{
92 const mmap_region_t bl_regions[] = {
93 MAP_BL31_TOTAL,
94 MAP_BL31_RO,
95#if USE_COHERENT_MEM
96 MAP_COHERENT_MEM,
97#endif
98 {0},
99 };
100
101 setup_page_tables(bl_regions, imx_mmap);
102 enable_mmu_el3(0);
103
104 /* TODO: Hack, refine this piece, scmi channel free */
105 mmio_write_32(SRAM0_BASE + 0x4, 1);
106}
107
108void bl31_platform_setup(void)
109{
110 /* select the arch timer source */
111 mmio_setbits_32(IMX_SIM1_BASE + 0x30, 0x8000000);
112
113 generic_delay_timer_init();
114
115 plat_gic_driver_init();
116 plat_gic_init();
117
118 imx8ulp_init_scmi_server();
119 upower_init();
Jacky Bai7ec94512023-09-21 14:01:37 +0800120
121 xrdc_apply_apd_config();
122 xrdc_apply_lpav_config();
123 xrdc_enable();
124
Pankaj Gupta862f57a2021-08-04 15:42:51 +0530125 imx8ulp_caam_init();
Jacky Bai4d93d1d2020-07-02 14:39:58 +0800126}
127
128entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
129{
130 if (type == NON_SECURE) {
131 return &bl33_image_ep_info;
132 } else {
133 return &bl32_image_ep_info;
134 }
135}
136
137unsigned int plat_get_syscnt_freq2(void)
138{
139 return COUNTER_FREQUENCY;
140}
141
142void bl31_plat_runtime_setup(void)
143{
144}