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Nishanth Menonf49cf9e2017-09-20 01:32:13 -05001/*
Deepika Bhavnanid51727e2019-12-13 10:53:34 -06002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Nishanth Menonf49cf9e2017-09-20 01:32:13 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef BOARD_DEF_H
8#define BOARD_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Nishanth Menonf49cf9e2017-09-20 01:32:13 -050011
12/* The ports must be in order and contiguous */
Deepika Bhavnanid51727e2019-12-13 10:53:34 -060013#define K3_CLUSTER0_CORE_COUNT U(2)
14#define K3_CLUSTER1_CORE_COUNT U(2)
15#define K3_CLUSTER2_CORE_COUNT U(2)
16#define K3_CLUSTER3_CORE_COUNT U(2)
Nishanth Menonf49cf9e2017-09-20 01:32:13 -050017
18/*
19 * This RAM will be used for the bootloader including code, bss, and stacks.
20 * It may need to be increased if BL31 grows in size.
21 */
22#define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */
23#define SEC_SRAM_SIZE 0x00020000 /* 128k */
24
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010025#define PLAT_MAX_OFF_STATE U(2)
26#define PLAT_MAX_RET_STATE U(1)
Nishanth Menonf49cf9e2017-09-20 01:32:13 -050027
Andrew F. Davis60541b12018-05-24 11:15:42 -050028#define PLAT_PROC_START_ID 32
29#define PLAT_PROC_DEVICE_START_ID 202
Andrew F. Davisf6f33c22019-02-11 16:12:31 -060030#define PLAT_CLUSTER_DEVICE_START_ID 198
Andrew F. Davis60541b12018-05-24 11:15:42 -050031
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010032#endif /* BOARD_DEF_H */