blob: f5f91e3186ba8a39ad8861196d9b34e8bc79d559 [file] [log] [blame]
Samuel Hollandb8566642017-08-12 04:07:39 -05001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <assert.h>
9#include <console.h>
10#include <debug.h>
11#include <generic_delay_timer.h>
12#include <gicv2.h>
13#include <platform.h>
14#include <platform_def.h>
15#include <sunxi_def.h>
16#include <sunxi_mmap.h>
17#include <uart_16550.h>
18
19#include "sunxi_private.h"
20
Amit Singh Tomar2f372242018-06-20 00:44:50 +053021static entry_point_info_t bl32_image_ep_info;
Samuel Hollandb8566642017-08-12 04:07:39 -050022static entry_point_info_t bl33_image_ep_info;
23
24static console_16550_t console;
25
26static const gicv2_driver_data_t sunxi_gic_data = {
27 .gicd_base = SUNXI_GICD_BASE,
28 .gicc_base = SUNXI_GICC_BASE,
29};
30
31void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
32 u_register_t arg2, u_register_t arg3)
33{
34 /* Initialize the debug console as soon as possible */
35 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ,
36 SUNXI_UART0_BAUDRATE, &console);
37
Amit Singh Tomar2f372242018-06-20 00:44:50 +053038#ifdef BL32_BASE
39 /* Populate entry point information for BL32 */
40 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
41 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
42 bl32_image_ep_info.pc = BL32_BASE;
43#endif
44
Samuel Hollandb8566642017-08-12 04:07:39 -050045 /* Populate entry point information for BL33 */
46 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
47 /*
48 * Tell BL31 where the non-trusted software image
49 * is located and the entry state information
50 */
51 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
52 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
53 DISABLE_ALL_EXCEPTIONS);
54 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
Samuel Holland321c0ab2017-08-12 04:07:39 -050055
56 /* Turn off all secondary CPUs */
57 sunxi_disable_secondary_cpus(plat_my_core_pos());
Samuel Hollandb8566642017-08-12 04:07:39 -050058}
59
60void bl31_plat_arch_setup(void)
61{
62 sunxi_configure_mmu_el3(0);
63}
64
65void bl31_platform_setup(void)
66{
67 generic_delay_timer_init();
68
69 /* Configure the interrupt controller */
70 gicv2_driver_init(&sunxi_gic_data);
71 gicv2_distif_init();
72 gicv2_pcpu_distif_init();
73 gicv2_cpuif_enable();
74
Andre Przywara13815472018-06-01 02:01:39 +010075 sunxi_security_setup();
76
Samuel Hollandb8566642017-08-12 04:07:39 -050077 INFO("BL31: Platform setup done\n");
78}
79
80entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
81{
82 assert(sec_state_is_valid(type) != 0);
Amit Singh Tomar2f372242018-06-20 00:44:50 +053083
84 if (type == NON_SECURE)
85 return &bl33_image_ep_info;
86
87 if ((type == SECURE) && bl32_image_ep_info.pc)
88 return &bl32_image_ep_info;
Samuel Hollandb8566642017-08-12 04:07:39 -050089
Amit Singh Tomar2f372242018-06-20 00:44:50 +053090 return NULL;
Samuel Hollandb8566642017-08-12 04:07:39 -050091}