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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Yann Gautier5ae29c02024-01-16 19:39:31 +01002# Copyright (c) 2016-2024, Arm Limited. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Alexei Fedorov132e6652020-12-07 16:38:53 +000022# ARM Architecture feature modifiers: none by default
23ARM_ARCH_FEATURE := none
24
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000025# ARM Architecture major and minor versions: 8.0 by default.
26ARM_ARCH_MAJOR := 8
27ARM_ARCH_MINOR := 0
28
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010029# Base commit to perform code check on
30BASE_COMMIT := origin/master
31
Roberto Vargase0e99462017-10-30 14:43:43 +000032# Execute BL2 at EL3
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060033RESET_TO_BL2 := 0
Roberto Vargase0e99462017-10-30 14:43:43 +000034
Balint Dobszay719ba9c2021-03-26 16:23:18 +010035# Only use SP packages if SP layout JSON is defined
36BL2_ENABLE_SP_LOAD := 0
37
Jiafei Pan43a7bf42018-03-21 07:20:09 +000038# BL2 image is stored in XIP memory, for now, this option is only supported
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060039# when RESET_TO_BL2 is 1.
Jiafei Pan43a7bf42018-03-21 07:20:09 +000040BL2_IN_XIP_MEM := 0
41
Hadi Asyrafi461f8f42019-08-20 15:33:27 +080042# Do dcache invalidate upon BL2 entry at EL3
43BL2_INV_DCACHE := 1
44
Alexei Fedorov90f2e882019-05-24 12:17:09 +010045# Select the branch protection features to use.
46BRANCH_PROTECTION := 0
47
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010048# By default, consider that the platform may release several CPUs out of reset.
49# The platform Makefile is free to override this value.
50COLD_BOOT_SINGLE_CPU := 0
51
Julius Wernerb624ae02017-06-09 15:17:15 -070052# Flag to compile in coreboot support code. Exclude by default. The coreboot
53# Makefile system will set this when compiling TF as part of a coreboot image.
54COREBOOT := 0
55
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010056# For Chain of Trust
57CREATE_KEYS := 1
58
59# Build flag to include AArch32 registers in cpu context save and restore during
60# world switch. This flag must be set to 0 for AArch64-only platforms.
61CTX_INCLUDE_AARCH32_REGS := 1
62
63# Include FP registers in cpu context
64CTX_INCLUDE_FPREGS := 0
65
66# Debug build
67DEBUG := 0
68
Sumit Garg392e4df2019-11-15 10:43:00 +053069# By default disable authenticated decryption support.
70DECRYPTION_SUPPORT := none
71
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010072# Build platform
73DEFAULT_PLAT := fvp
74
Christoph Müllner4f088e42019-04-24 09:45:30 +020075# Disable the generation of the binary image (ELF only).
76DISABLE_BIN_GENERATION := 0
77
Soby Mathew9fe88042018-03-26 12:43:37 +010078# Enable capability to disable authentication dynamically. Only meant for
79# development platforms.
80DYN_DISABLE_AUTH := 0
81
Chris Kay03be39d2021-05-05 13:38:30 +010082# Enable the Maximum Power Mitigation Mechanism on supporting cores.
83ENABLE_MPMM := 0
84
85# Enable MPMM configuration via FCONF.
86ENABLE_MPMM_FCONF := 0
87
Soby Mathew078f1a42018-08-28 11:13:55 +010088# Flag to Enable Position Independant support (PIE)
89ENABLE_PIE := 0
90
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010091# Flag to enable Performance Measurement Framework
92ENABLE_PMF := 0
93
94# Flag to enable PSCI STATs functionality
95ENABLE_PSCI_STAT := 0
96
97# Flag to enable runtime instrumentation using PMF
98ENABLE_RUNTIME_INSTRUMENTATION := 0
99
Douglas Raillard306593d2017-02-24 18:14:15 +0000100# Flag to enable stack corruption protection
101ENABLE_STACK_PROTECTOR := 0
102
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100103# Flag to enable exception handling in EL3
104EL3_EXCEPTION_HANDLING := 0
105
Sumit Gargeec52442019-11-14 16:33:45 +0530106# By default BL31 encryption disabled
107ENCRYPT_BL31 := 0
108
109# By default BL32 encryption disabled
110ENCRYPT_BL32 := 0
111
112# Default dummy firmware encryption key
113ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
114
115# Default dummy nonce for firmware encryption
116ENC_NONCE := 1234567890abcdef12345678
117
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100118# Build flag to treat usage of deprecated platform and framework APIs as error.
119ERROR_DEPRECATED := 0
120
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000121# Fault injection support
122FAULT_INJECTION_SUPPORT := 0
123
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000124# Flag to enable architectural features detection mechanism
125FEATURE_DETECTION := 0
126
Masahiro Yamada4d87eb42016-12-25 13:52:22 +0900127# Byte alignment that each component in FIP is aligned to
128FIP_ALIGN := 0
129
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100130# Default FIP file name
131FIP_NAME := fip.bin
132
133# Default FWU_FIP file name
134FWU_FIP_NAME := fwu_fip.bin
135
Sumit Gargeec52442019-11-14 16:33:45 +0530136# By default firmware encryption with SSK
137FW_ENC_STATUS := 0
138
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100139# For Chain of Trust
140GENERATE_COT := 0
141
AlexeiFedorovc0ca2d72024-05-13 15:35:54 +0100142# Default number of 512 blocks per bitlock
143RME_GPT_BITLOCK_BLOCK := 1
144
AlexeiFedorovbd8b1bb2024-03-13 17:07:03 +0000145# Default maximum size of GPT contiguous block
146RME_GPT_MAX_BLOCK := 2
147
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100148# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
149# default, they are for Secure EL1.
150GICV2_G0_FOR_EL3 := 0
151
Manish Pandey0e3379d2022-10-10 11:43:08 +0100152# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000153# by lower ELs.
Manish Pandey0e3379d2022-10-10 11:43:08 +0100154HANDLE_EA_EL3_FIRST_NS := 0
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000155
Raymond Mao98983392023-07-25 07:53:35 -0700156# Enable Handoff protocol using transfer lists
157TRANSFER_LIST := 0
158
Bipin Ravie53e6ae2023-09-28 13:17:24 -0500159# Enables support for the gcc compiler option "-mharden-sls=all".
160# By default, disables all SLS hardening.
161HARDEN_SLS := 0
162
Alexei Fedorovf11aeb72020-10-06 15:54:12 +0100163# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
164# The default value is sha256.
165HASH_ALG := sha256
166
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000167# Whether system coherency is managed in hardware, without explicit software
168# operations.
169HW_ASSISTED_COHERENCY := 0
170
Varun Wadekar0a46eb12023-04-13 21:06:18 +0100171# Flag to enable trapping of implementation defined sytem registers
172IMPDEF_SYSREG_TRAP := 0
173
Soby Mathew13b16052017-08-31 11:49:32 +0100174# Set the default algorithm for the generation of Trusted Board Boot keys
175KEY_ALG := rsa
176
Leonardo Sandoval849f7af2020-06-18 17:32:55 -0500177# Set the default key size in case KEY_ALG is rsa
178ifeq ($(KEY_ALG),rsa)
179KEY_SIZE := 2048
180endif
181
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000182# Option to build TF with Measured Boot support
183MEASURED_BOOT := 0
184
Tamas Bana4260892023-06-07 13:35:04 +0200185# Option to enable the DICE Protection Environmnet as a Measured Boot backend
186DICE_PROTECTION_ENVIRONMENT :=0
187
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100188# NS timer register save and restore
189NS_TIMER_SWITCH := 0
190
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800191# Include lib/libc in the final image
192OVERRIDE_LIBC := 0
193
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100194# Build PL011 UART driver in minimal generic UART mode
195PL011_GENERIC_UART := 0
196
197# By default, consider that the platform's reset address is not programmable.
198# The platform Makefile is free to override this value.
199PROGRAMMABLE_RESET_ADDRESS := 0
200
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000201# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100202PSCI_EXTENDED_STATE_ID := 0
203
Wing Li1e9b68a2023-01-26 18:33:36 -0800204# Enable PSCI OS-initiated mode support
205PSCI_OS_INIT_MODE := 0
206
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100207# By default, BL1 acts as the reset handler, not BL31
208RESET_TO_BL31 := 0
209
210# For Chain of Trust
211SAVE_KEYS := 0
212
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100213# Software Delegated Exception support
johpow019baade32021-07-08 14:14:00 -0500214SDEI_SUPPORT := 0
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100215
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +0100216# True Random Number firmware Interface support
johpow019baade32021-07-08 14:14:00 -0500217TRNG_SUPPORT := 0
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -0500218
Sona Mathew7fe03522022-11-18 18:05:38 -0600219# Check to see if Errata ABI is supported
220ERRATA_ABI_SUPPORT := 0
221
Sona Mathew5a4c9fc2023-03-14 14:02:03 -0500222# Check to enable Errata ABI for platforms with non-arm interconnect
223ERRATA_NON_ARM_INTERCONNECT := 0
224
Jeremy Linton90cbf522020-11-18 10:12:41 -0600225# SMCCC PCI support
johpow019baade32021-07-08 14:14:00 -0500226SMC_PCI_SUPPORT := 0
Jeremy Linton90cbf522020-11-18 10:12:41 -0600227
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100228# Whether code and read-only data should be put on separate memory pages. The
229# platform Makefile is free to override this value.
230SEPARATE_CODE_AND_RODATA := 0
231
Samuel Holland31a14e12018-10-17 21:40:18 -0500232# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
233# separate memory region, which may be discontiguous from the rest of BL31.
234SEPARATE_NOBITS_REGION := 0
235
Jiafei Pan0824b452022-02-24 10:47:33 +0800236# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory
237# region, platform Makefile is free to override this value.
238SEPARATE_BL2_NOLOAD_REGION := 0
239
Daniel Boulby468f0d72018-09-18 11:45:51 +0100240# If the BL31 image initialisation code is recalimed after use for the secondary
241# cores stack
242RECLAIM_INIT_CODE := 0
243
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100244# SPD choice
245SPD := none
246
Paul Beesleyfe975b42019-09-16 11:29:03 +0000247# Enable the Management Mode (MM)-based Secure Partition Manager implementation
248SPM_MM := 0
Antonio Nino Diaz8cd7ea32018-10-30 11:08:08 +0000249
Marc Bonniciabaac162021-12-01 18:00:40 +0000250# Use the FF-A SPMC implementation in EL3.
251SPMC_AT_EL3 := 0
252
Nishant Sharma9e719112023-06-27 00:36:01 +0100253# Enable SEL0 SP when SPMC is enabled at EL3
254SPMC_AT_EL3_SEL0_SP :=0
255
Max Shvetsove7fd80e2020-02-25 13:55:00 +0000256# Use SPM at S-EL2 as a default config for SPMD
257SPMD_SPM_AT_SEL2 := 1
258
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100259# Flag to introduce an infinite loop in BL1 just before it exits into the next
260# image. This is meant to help debugging the post-BL2 phase.
261SPIN_ON_BL1_EXIT := 0
262
263# Flags to build TF with Trusted Boot support
264TRUSTED_BOARD_BOOT := 0
265
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100266# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100267USE_COHERENT_MEM := 1
268
Olivier Deprezcb4c5622019-09-19 17:46:46 +0200269# Build option to add debugfs support
270USE_DEBUGFS := 0
271
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100272# Build option to fconf based io
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100273ARM_IO_IN_DTB := 0
274
275# Build option to support SDEI through fconf
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500276SDEI_IN_FCONF := 0
277
278# Build option to support Secure Interrupt descriptors through fconf
279SEC_INT_DESC_IN_FCONF := 0
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100280
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100281# Build option to choose whether Trusted Firmware uses library at ROM
282USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100283
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000284# Build option to choose whether the xlat tables of BL images can be read-only.
285# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
286# which is the per BL-image option that actually enables the read-only tables
287# API. The reason for having this additional option is to have a common high
288# level makefile where we can check for incompatible features/build options.
289ALLOW_RO_XLAT_TABLES := 0
290
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100291# Chain of trust.
292COT := tbbr
293
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900294# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100295USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900296
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100297# Build verbosity
298V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100299
300# Whether to enable D-Cache early during warm boot. This is usually
301# applicable for platforms wherein interconnect programming is not
302# required to enable cache coherency after warm reset (eg: single cluster
303# platforms).
304WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100305
Mark Brown64869972022-04-20 18:14:32 +0100306# Default SVE vector length to maximum architected value
307SVE_VECTOR_LEN := 2048
308
Justin Chadwell83e04882019-08-20 11:01:52 +0100309SANITIZE_UB := off
Soby Mathewad042012019-09-25 14:03:41 +0100310
311# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
312# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
313# Default: disabled
314USE_SPINLOCK_CAS := 0
zelalem-aweked5f45272019-11-12 16:20:17 -0600315
316# Enable Link Time Optimization
317ENABLE_LTO := 0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000318
Govindraj Raja0264d6c2022-11-21 13:10:40 +0000319# This option will include EL2 registers in cpu context save and restore during
320# EL2 firmware entry/exit. Internal flag not meant for direct setting.
321# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable
322# CTX_INCLUDE_EL2_REGS.
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000323CTX_INCLUDE_EL2_REGS := 0
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000324
325# Enable Memory tag extension which is supported for architecture greater
326# than Armv8.5-A
327# By default it is set to "no"
328SUPPORT_STACK_MEMTAG := no
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100329
330# Select workaround for AT speculative behaviour.
johpow019baade32021-07-08 14:14:00 -0500331ERRATA_SPECULATIVE_AT := 0
Varun Wadekar92234852020-06-12 10:11:28 -0700332
Manish Pandey7c6fcb42022-09-27 14:30:34 +0100333# Trap RAS error record access from Non secure
334RAS_TRAP_NS_ERR_REC_ACCESS := 0
Manish V Badarkhead339892020-06-29 10:32:53 +0100335
336# Build option to create cot descriptors using fconf
337COT_DESC_IN_DTB := 0
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100338
Juan Pablo Conde3539c742022-10-25 19:41:02 -0400339# Build option to provide OpenSSL directory path
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100340OPENSSL_DIR := /usr
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500341
Salome Thirot0b35da32022-07-14 16:14:15 +0100342# Select the openssl binary provided in OPENSSL_DIR variable
343ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "")
344 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps
345else
346 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin
347endif
348
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500349# Build option to use the SP804 timer instead of the generic one
350USE_SP804_TIMER := 0
Manish V Badarkhe2bb45ff2021-03-16 10:01:27 +0000351
352# Build option to define number of firmware banks, used in firmware update
353# metadata structure.
354NR_OF_FW_BANKS := 2
355
356# Build option to define number of images in firmware bank, used in firmware
357# update metadata structure.
358NR_OF_IMAGES_IN_FW_BANK := 1
Manish V Badarkhe99575e42021-06-25 23:28:59 +0100359
360# Disable Firmware update support by default
361PSA_FWU_SUPPORT := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100362
Sughosh Ganu61905e52024-02-01 12:51:20 +0530363# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT
364# is enabled.
365ifeq ($(PSA_FWU_SUPPORT),1)
366PSA_FWU_METADATA_FW_STORE_DESC := 1
367else
368PSA_FWU_METADATA_FW_STORE_DESC := 0
369endif
370
Manish V Badarkhe191a5fc2022-03-02 12:06:35 +0000371# Dynamic Root of Trust for Measurement support
372DRTM_SUPPORT := 0
Okash Khawaja037b56e2022-11-04 12:38:01 +0000373
374# Check platform if cache management operations should be performed.
375# Disabled by default.
376CONDITIONAL_CMO := 0
Raghu Krishnamurthy7f046c12023-02-25 13:26:10 -0800377
378# By default, disable SPMD Logical partitions
379ENABLE_SPMD_LP := 0
Manish V Badarkhe78e14f82023-09-06 09:08:28 +0100380
381# By default, disable PSA crypto (use MbedTLS legacy crypto API).
382PSA_CRYPTO := 0
Sandrine Bailleuxf57e2032023-10-11 08:38:00 +0200383
384# getc() support from the console(s).
385# Disabled by default because it constitutes an attack vector into TF-A. It
386# should only be enabled if there is a use case for it.
387ENABLE_CONSOLE_GETC := 0
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500388
389# Build option to disable EL2 when it is not used.
390# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2
391# functions must be enabled by platforms if they require it.
392# Disabled by default.
393INIT_UNUSED_NS_EL2 := 0
Arvind Ram Prakash4851b492023-10-06 14:35:21 -0500394
395# Disable including MPAM EL2 registers in context by default since currently
396# it's only enabled for NS world
397CTX_INCLUDE_MPAM_REGS := 0
Juan Pablo Condeb5ec1382023-11-08 16:14:28 -0600398
399# Enable context memory usage reporting during BL31 setup.
400PLATFORM_REPORT_CTX_MEM_USE := 0
Yann Gautier5ae29c02024-01-16 19:39:31 +0100401
402# Enable early console
403EARLY_CONSOLE := 0
Arvind Ram Prakasheaa90192023-12-21 00:25:52 -0600404
405# Allow platforms to save/restore DSU PMU registers over a power cycle.
406# Disabled by default and must be enabled by individual platforms.
407PRESERVE_DSU_PMU_REGS := 0