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Caesar Wang9740bba2016-08-25 08:37:42 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wang9740bba2016-08-25 08:37:42 +08005 */
6
Caesar Wanga8456902016-10-27 01:12:34 +08007#include <dram.h>
Caesar Wang9740bba2016-08-25 08:37:42 +08008#include <plat_private.h>
Xing Zheng22a98712017-02-24 14:56:41 +08009#include <secure.h>
Caesar Wanga8456902016-10-27 01:12:34 +080010#include <soc.h>
11#include <rk3399_def.h>
Caesar Wang9740bba2016-08-25 08:37:42 +080012
Caesar Wanga8456902016-10-27 01:12:34 +080013__sramdata struct rk3399_sdram_params sdram_config;
Caesar Wang9740bba2016-08-25 08:37:42 +080014
Caesar Wanga8456902016-10-27 01:12:34 +080015void dram_init(void)
Caesar Wang9740bba2016-08-25 08:37:42 +080016{
17 uint32_t os_reg2_val, i;
18
Caesar Wanga8456902016-10-27 01:12:34 +080019 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2));
20 sdram_config.dramtype = SYS_REG_DEC_DDRTYPE(os_reg2_val);
21 sdram_config.num_channels = SYS_REG_DEC_NUM_CH(os_reg2_val);
22 sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >>
23 10) & 0x1f;
Caesar Wang9740bba2016-08-25 08:37:42 +080024
Caesar Wanga8456902016-10-27 01:12:34 +080025 for (i = 0; i < 2; i++) {
26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i];
27 struct rk3399_msch_timings *noc = &ch->noc_timings;
Caesar Wang9740bba2016-08-25 08:37:42 +080028
Caesar Wanga8456902016-10-27 01:12:34 +080029 if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i)))
Caesar Wang9740bba2016-08-25 08:37:42 +080030 continue;
31
Caesar Wanga8456902016-10-27 01:12:34 +080032 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i);
33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i);
34 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i);
35 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i);
36 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i);
37 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i);
38 ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i);
39 ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i);
40 ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF);
Caesar Wang9740bba2016-08-25 08:37:42 +080041
Caesar Wanga8456902016-10-27 01:12:34 +080042 noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) +
43 MSCH_DDRTIMINGA0);
44 noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) +
45 MSCH_DDRTIMINGB0);
46 noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) +
47 MSCH_DDRTIMINGC0);
48 noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) +
49 MSCH_DEVTODEV0);
50 noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE);
51 noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0);
Caesar Wang9740bba2016-08-25 08:37:42 +080052 }
Caesar Wang9740bba2016-08-25 08:37:42 +080053}