Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> /* for uint32_t */ |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <lib/mmio.h> |
| 10 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 11 | #include "pfc_init_e3.h" |
| 12 | #include "rcar_def.h" |
| 13 | |
| 14 | /* GPIO base address */ |
| 15 | #define GPIO_BASE (0xE6050000U) |
| 16 | |
| 17 | /* GPIO registers */ |
| 18 | #define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) |
| 19 | #define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) |
| 20 | #define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) |
| 21 | #define GPIO_INDT0 (GPIO_BASE + 0x000CU) |
| 22 | #define GPIO_INTDT0 (GPIO_BASE + 0x0010U) |
| 23 | #define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) |
| 24 | #define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) |
| 25 | #define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) |
| 26 | #define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) |
| 27 | #define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) |
| 28 | #define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) |
| 29 | #define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) |
| 30 | #define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) |
| 31 | #define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) |
| 32 | #define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) |
| 33 | #define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) |
| 34 | #define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) |
| 35 | #define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) |
| 36 | #define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) |
| 37 | #define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) |
| 38 | #define GPIO_INDT1 (GPIO_BASE + 0x100CU) |
| 39 | #define GPIO_INTDT1 (GPIO_BASE + 0x1010U) |
| 40 | #define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) |
| 41 | #define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) |
| 42 | #define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) |
| 43 | #define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) |
| 44 | #define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) |
| 45 | #define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) |
| 46 | #define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) |
| 47 | #define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) |
| 48 | #define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) |
| 49 | #define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) |
| 50 | #define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) |
| 51 | #define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) |
| 52 | #define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) |
| 53 | #define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) |
| 54 | #define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) |
| 55 | #define GPIO_INDT2 (GPIO_BASE + 0x200CU) |
| 56 | #define GPIO_INTDT2 (GPIO_BASE + 0x2010U) |
| 57 | #define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) |
| 58 | #define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) |
| 59 | #define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) |
| 60 | #define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) |
| 61 | #define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) |
| 62 | #define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) |
| 63 | #define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) |
| 64 | #define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) |
| 65 | #define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) |
| 66 | #define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) |
| 67 | #define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) |
| 68 | #define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) |
| 69 | #define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) |
| 70 | #define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) |
| 71 | #define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) |
| 72 | #define GPIO_INDT3 (GPIO_BASE + 0x300CU) |
| 73 | #define GPIO_INTDT3 (GPIO_BASE + 0x3010U) |
| 74 | #define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) |
| 75 | #define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) |
| 76 | #define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) |
| 77 | #define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) |
| 78 | #define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) |
| 79 | #define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) |
| 80 | #define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) |
| 81 | #define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) |
| 82 | #define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) |
| 83 | #define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) |
| 84 | #define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) |
| 85 | #define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) |
| 86 | #define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) |
| 87 | #define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) |
| 88 | #define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) |
| 89 | #define GPIO_INDT4 (GPIO_BASE + 0x400CU) |
| 90 | #define GPIO_INTDT4 (GPIO_BASE + 0x4010U) |
| 91 | #define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) |
| 92 | #define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) |
| 93 | #define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) |
| 94 | #define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) |
| 95 | #define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) |
| 96 | #define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) |
| 97 | #define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) |
| 98 | #define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) |
| 99 | #define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) |
| 100 | #define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) |
| 101 | #define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) |
| 102 | #define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) |
| 103 | #define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) |
| 104 | #define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) |
| 105 | #define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) |
| 106 | #define GPIO_INDT5 (GPIO_BASE + 0x500CU) |
| 107 | #define GPIO_INTDT5 (GPIO_BASE + 0x5010U) |
| 108 | #define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) |
| 109 | #define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) |
| 110 | #define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) |
| 111 | #define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) |
| 112 | #define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) |
| 113 | #define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) |
| 114 | #define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) |
| 115 | #define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) |
| 116 | #define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) |
| 117 | #define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) |
| 118 | #define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) |
| 119 | #define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) |
| 120 | #define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U) |
| 121 | #define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U) |
| 122 | #define GPIO_OUTDT6 (GPIO_BASE + 0x5408U) |
| 123 | #define GPIO_INDT6 (GPIO_BASE + 0x540CU) |
| 124 | #define GPIO_INTDT6 (GPIO_BASE + 0x5410U) |
| 125 | #define GPIO_INTCLR6 (GPIO_BASE + 0x5414U) |
| 126 | #define GPIO_INTMSK6 (GPIO_BASE + 0x5418U) |
| 127 | #define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU) |
| 128 | #define GPIO_POSNEG6 (GPIO_BASE + 0x5420U) |
| 129 | #define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U) |
| 130 | #define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U) |
| 131 | #define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U) |
| 132 | #define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU) |
| 133 | #define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U) |
| 134 | #define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U) |
| 135 | #define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U) |
| 136 | #define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU) |
| 137 | |
| 138 | /* Pin functon base address */ |
| 139 | #define PFC_BASE (0xE6060000U) |
| 140 | |
| 141 | /* Pin functon registers */ |
| 142 | #define PFC_PMMR (PFC_BASE + 0x0000U) |
| 143 | #define PFC_GPSR0 (PFC_BASE + 0x0100U) |
| 144 | #define PFC_GPSR1 (PFC_BASE + 0x0104U) |
| 145 | #define PFC_GPSR2 (PFC_BASE + 0x0108U) |
| 146 | #define PFC_GPSR3 (PFC_BASE + 0x010CU) |
| 147 | #define PFC_GPSR4 (PFC_BASE + 0x0110U) |
| 148 | #define PFC_GPSR5 (PFC_BASE + 0x0114U) |
| 149 | #define PFC_GPSR6 (PFC_BASE + 0x0118U) |
| 150 | #define PFC_IPSR0 (PFC_BASE + 0x0200U) |
| 151 | #define PFC_IPSR1 (PFC_BASE + 0x0204U) |
| 152 | #define PFC_IPSR2 (PFC_BASE + 0x0208U) |
| 153 | #define PFC_IPSR3 (PFC_BASE + 0x020CU) |
| 154 | #define PFC_IPSR4 (PFC_BASE + 0x0210U) |
| 155 | #define PFC_IPSR5 (PFC_BASE + 0x0214U) |
| 156 | #define PFC_IPSR6 (PFC_BASE + 0x0218U) |
| 157 | #define PFC_IPSR7 (PFC_BASE + 0x021CU) |
| 158 | #define PFC_IPSR8 (PFC_BASE + 0x0220U) |
| 159 | #define PFC_IPSR9 (PFC_BASE + 0x0224U) |
| 160 | #define PFC_IPSR10 (PFC_BASE + 0x0228U) |
| 161 | #define PFC_IPSR11 (PFC_BASE + 0x022CU) |
| 162 | #define PFC_IPSR12 (PFC_BASE + 0x0230U) |
| 163 | #define PFC_IPSR13 (PFC_BASE + 0x0234U) |
| 164 | #define PFC_IPSR14 (PFC_BASE + 0x0238U) |
| 165 | #define PFC_IPSR15 (PFC_BASE + 0x023CU) |
| 166 | #define PFC_IOCTRL30 (PFC_BASE + 0x0380U) |
| 167 | #define PFC_IOCTRL32 (PFC_BASE + 0x0388U) |
| 168 | #define PFC_IOCTRL40 (PFC_BASE + 0x03C0U) |
| 169 | #define PFC_PUEN0 (PFC_BASE + 0x0400U) |
| 170 | #define PFC_PUEN1 (PFC_BASE + 0x0404U) |
| 171 | #define PFC_PUEN2 (PFC_BASE + 0x0408U) |
| 172 | #define PFC_PUEN3 (PFC_BASE + 0x040CU) |
| 173 | #define PFC_PUEN4 (PFC_BASE + 0x0410U) |
| 174 | #define PFC_PUEN5 (PFC_BASE + 0x0414U) |
| 175 | #define PFC_PUD0 (PFC_BASE + 0x0440U) |
| 176 | #define PFC_PUD1 (PFC_BASE + 0x0444U) |
| 177 | #define PFC_PUD2 (PFC_BASE + 0x0448U) |
| 178 | #define PFC_PUD3 (PFC_BASE + 0x044CU) |
| 179 | #define PFC_PUD4 (PFC_BASE + 0x0450U) |
| 180 | #define PFC_PUD5 (PFC_BASE + 0x0454U) |
| 181 | #define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) |
| 182 | #define PFC_MOD_SEL1 (PFC_BASE + 0x0504U) |
| 183 | |
| 184 | #define GPSR0_SDA4 ((uint32_t)1U << 17U) |
| 185 | #define GPSR0_SCL4 ((uint32_t)1U << 16U) |
| 186 | #define GPSR0_D15 ((uint32_t)1U << 15U) |
| 187 | #define GPSR0_D14 ((uint32_t)1U << 14U) |
| 188 | #define GPSR0_D13 ((uint32_t)1U << 13U) |
| 189 | #define GPSR0_D12 ((uint32_t)1U << 12U) |
| 190 | #define GPSR0_D11 ((uint32_t)1U << 11U) |
| 191 | #define GPSR0_D10 ((uint32_t)1U << 10U) |
| 192 | #define GPSR0_D9 ((uint32_t)1U << 9U) |
| 193 | #define GPSR0_D8 ((uint32_t)1U << 8U) |
| 194 | #define GPSR0_D7 ((uint32_t)1U << 7U) |
| 195 | #define GPSR0_D6 ((uint32_t)1U << 6U) |
| 196 | #define GPSR0_D5 ((uint32_t)1U << 5U) |
| 197 | #define GPSR0_D4 ((uint32_t)1U << 4U) |
| 198 | #define GPSR0_D3 ((uint32_t)1U << 3U) |
| 199 | #define GPSR0_D2 ((uint32_t)1U << 2U) |
| 200 | #define GPSR0_D1 ((uint32_t)1U << 1U) |
| 201 | #define GPSR0_D0 ((uint32_t)1U << 0U) |
| 202 | #define GPSR1_WE0 ((uint32_t)1U << 22U) |
| 203 | #define GPSR1_CS0 ((uint32_t)1U << 21U) |
| 204 | #define GPSR1_CLKOUT ((uint32_t)1U << 20U) |
| 205 | #define GPSR1_A19 ((uint32_t)1U << 19U) |
| 206 | #define GPSR1_A18 ((uint32_t)1U << 18U) |
| 207 | #define GPSR1_A17 ((uint32_t)1U << 17U) |
| 208 | #define GPSR1_A16 ((uint32_t)1U << 16U) |
| 209 | #define GPSR1_A15 ((uint32_t)1U << 15U) |
| 210 | #define GPSR1_A14 ((uint32_t)1U << 14U) |
| 211 | #define GPSR1_A13 ((uint32_t)1U << 13U) |
| 212 | #define GPSR1_A12 ((uint32_t)1U << 12U) |
| 213 | #define GPSR1_A11 ((uint32_t)1U << 11U) |
| 214 | #define GPSR1_A10 ((uint32_t)1U << 10U) |
| 215 | #define GPSR1_A9 ((uint32_t)1U << 9U) |
| 216 | #define GPSR1_A8 ((uint32_t)1U << 8U) |
| 217 | #define GPSR1_A7 ((uint32_t)1U << 7U) |
| 218 | #define GPSR1_A6 ((uint32_t)1U << 6U) |
| 219 | #define GPSR1_A5 ((uint32_t)1U << 5U) |
| 220 | #define GPSR1_A4 ((uint32_t)1U << 4U) |
| 221 | #define GPSR1_A3 ((uint32_t)1U << 3U) |
| 222 | #define GPSR1_A2 ((uint32_t)1U << 2U) |
| 223 | #define GPSR1_A1 ((uint32_t)1U << 1U) |
| 224 | #define GPSR1_A0 ((uint32_t)1U << 0U) |
| 225 | #define GPSR2_BIT27_REVERCED ((uint32_t)1U << 27U) |
| 226 | #define GPSR2_BIT26_REVERCED ((uint32_t)1U << 26U) |
| 227 | #define GPSR2_EX_WAIT0 ((uint32_t)1U << 25U) |
| 228 | #define GPSR2_RD_WR ((uint32_t)1U << 24U) |
| 229 | #define GPSR2_RD ((uint32_t)1U << 23U) |
| 230 | #define GPSR2_BS ((uint32_t)1U << 22U) |
| 231 | #define GPSR2_AVB_PHY_INT ((uint32_t)1U << 21U) |
| 232 | #define GPSR2_AVB_TXCREFCLK ((uint32_t)1U << 20U) |
| 233 | #define GPSR2_AVB_RD3 ((uint32_t)1U << 19U) |
| 234 | #define GPSR2_AVB_RD2 ((uint32_t)1U << 18U) |
| 235 | #define GPSR2_AVB_RD1 ((uint32_t)1U << 17U) |
| 236 | #define GPSR2_AVB_RD0 ((uint32_t)1U << 16U) |
| 237 | #define GPSR2_AVB_RXC ((uint32_t)1U << 15U) |
| 238 | #define GPSR2_AVB_RX_CTL ((uint32_t)1U << 14U) |
| 239 | #define GPSR2_RPC_RESET ((uint32_t)1U << 13U) |
| 240 | #define GPSR2_RPC_RPC_INT ((uint32_t)1U << 12U) |
| 241 | #define GPSR2_QSPI1_SSL ((uint32_t)1U << 11U) |
| 242 | #define GPSR2_QSPI1_IO3 ((uint32_t)1U << 10U) |
| 243 | #define GPSR2_QSPI1_IO2 ((uint32_t)1U << 9U) |
| 244 | #define GPSR2_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) |
| 245 | #define GPSR2_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) |
| 246 | #define GPSR2_QSPI1_SPCLK ((uint32_t)1U << 6U) |
| 247 | #define GPSR2_QSPI0_SSL ((uint32_t)1U << 5U) |
| 248 | #define GPSR2_QSPI0_IO3 ((uint32_t)1U << 4U) |
| 249 | #define GPSR2_QSPI0_IO2 ((uint32_t)1U << 3U) |
| 250 | #define GPSR2_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) |
| 251 | #define GPSR2_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) |
| 252 | #define GPSR2_QSPI0_SPCLK ((uint32_t)1U << 0U) |
| 253 | #define GPSR3_SD1_WP ((uint32_t)1U << 15U) |
| 254 | #define GPSR3_SD1_CD ((uint32_t)1U << 14U) |
| 255 | #define GPSR3_SD0_WP ((uint32_t)1U << 13U) |
| 256 | #define GPSR3_SD0_CD ((uint32_t)1U << 12U) |
| 257 | #define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U) |
| 258 | #define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U) |
| 259 | #define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U) |
| 260 | #define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U) |
| 261 | #define GPSR3_SD1_CMD ((uint32_t)1U << 7U) |
| 262 | #define GPSR3_SD1_CLK ((uint32_t)1U << 6U) |
| 263 | #define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U) |
| 264 | #define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U) |
| 265 | #define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U) |
| 266 | #define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U) |
| 267 | #define GPSR3_SD0_CMD ((uint32_t)1U << 1U) |
| 268 | #define GPSR3_SD0_CLK ((uint32_t)1U << 0U) |
| 269 | #define GPSR4_SD3_DS ((uint32_t)1U << 10U) |
| 270 | #define GPSR4_SD3_DAT7 ((uint32_t)1U << 9U) |
| 271 | #define GPSR4_SD3_DAT6 ((uint32_t)1U << 8U) |
| 272 | #define GPSR4_SD3_DAT5 ((uint32_t)1U << 7U) |
| 273 | #define GPSR4_SD3_DAT4 ((uint32_t)1U << 6U) |
| 274 | #define GPSR4_SD3_DAT3 ((uint32_t)1U << 5U) |
| 275 | #define GPSR4_SD3_DAT2 ((uint32_t)1U << 4U) |
| 276 | #define GPSR4_SD3_DAT1 ((uint32_t)1U << 3U) |
| 277 | #define GPSR4_SD3_DAT0 ((uint32_t)1U << 2U) |
| 278 | #define GPSR4_SD3_CMD ((uint32_t)1U << 1U) |
| 279 | #define GPSR4_SD3_CLK ((uint32_t)1U << 0U) |
| 280 | #define GPSR5_MLB_DAT ((uint32_t)1U << 19U) |
| 281 | #define GPSR5_MLB_SIG ((uint32_t)1U << 18U) |
| 282 | #define GPSR5_MLB_CLK ((uint32_t)1U << 17U) |
| 283 | #define GPSR5_SSI_SDATA9 ((uint32_t)1U << 16U) |
| 284 | #define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 15U) |
| 285 | #define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 14U) |
| 286 | #define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 13U) |
| 287 | #define GPSR5_MSIOF0_TXD ((uint32_t)1U << 12U) |
| 288 | #define GPSR5_MSIOF0_RXD ((uint32_t)1U << 11U) |
| 289 | #define GPSR5_MSIOF0_SCK ((uint32_t)1U << 10U) |
| 290 | #define GPSR5_RX2_A ((uint32_t)1U << 9U) |
| 291 | #define GPSR5_TX2_A ((uint32_t)1U << 8U) |
| 292 | #define GPSR5_SCK2_A ((uint32_t)1U << 7U) |
| 293 | #define GPSR5_TX1 ((uint32_t)1U << 6U) |
| 294 | #define GPSR5_RX1 ((uint32_t)1U << 5U) |
| 295 | #define GPSR5_RTS0_TANS_A ((uint32_t)1U << 4U) |
| 296 | #define GPSR5_CTS0_A ((uint32_t)1U << 3U) |
| 297 | #define GPSR5_TX0_A ((uint32_t)1U << 2U) |
| 298 | #define GPSR5_RX0_A ((uint32_t)1U << 1U) |
| 299 | #define GPSR5_SCK0_A ((uint32_t)1U << 0U) |
| 300 | #define GPSR6_USB30_PWEN ((uint32_t)1U << 17U) |
| 301 | #define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U) |
| 302 | #define GPSR6_SSI_WS6 ((uint32_t)1U << 15U) |
| 303 | #define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U) |
| 304 | #define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U) |
| 305 | #define GPSR6_SSI_WS5 ((uint32_t)1U << 12U) |
| 306 | #define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U) |
| 307 | #define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U) |
| 308 | #define GPSR6_USB30_OVC ((uint32_t)1U << 9U) |
| 309 | #define GPSR6_AUDIO_CLKA ((uint32_t)1U << 8U) |
| 310 | #define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U) |
| 311 | #define GPSR6_SSI_WS349 ((uint32_t)1U << 6U) |
| 312 | #define GPSR6_SSI_SCK349 ((uint32_t)1U << 5U) |
| 313 | #define GPSR6_SSI_SDATA2 ((uint32_t)1U << 4U) |
| 314 | #define GPSR6_SSI_SDATA1 ((uint32_t)1U << 3U) |
| 315 | #define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U) |
| 316 | #define GPSR6_SSI_WS01239 ((uint32_t)1U << 1U) |
| 317 | #define GPSR6_SSI_SCK01239 ((uint32_t)1U << 0U) |
| 318 | |
| 319 | #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) |
| 320 | #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) |
| 321 | #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) |
| 322 | #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) |
| 323 | #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) |
| 324 | #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) |
| 325 | #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) |
| 326 | #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) |
| 327 | |
| 328 | #define IOCTRL30_MASK (0x0007F000U) |
| 329 | #define POC_SD3_DS_33V ((uint32_t)1U << 29U) |
| 330 | #define POC_SD3_DAT7_33V ((uint32_t)1U << 28U) |
| 331 | #define POC_SD3_DAT6_33V ((uint32_t)1U << 27U) |
| 332 | #define POC_SD3_DAT5_33V ((uint32_t)1U << 26U) |
| 333 | #define POC_SD3_DAT4_33V ((uint32_t)1U << 25U) |
| 334 | #define POC_SD3_DAT3_33V ((uint32_t)1U << 24U) |
| 335 | #define POC_SD3_DAT2_33V ((uint32_t)1U << 23U) |
| 336 | #define POC_SD3_DAT1_33V ((uint32_t)1U << 22U) |
| 337 | #define POC_SD3_DAT0_33V ((uint32_t)1U << 21U) |
| 338 | #define POC_SD3_CMD_33V ((uint32_t)1U << 20U) |
| 339 | #define POC_SD3_CLK_33V ((uint32_t)1U << 19U) |
| 340 | #define POC_SD1_DAT3_33V ((uint32_t)1U << 11U) |
| 341 | #define POC_SD1_DAT2_33V ((uint32_t)1U << 10U) |
| 342 | #define POC_SD1_DAT1_33V ((uint32_t)1U << 9U) |
| 343 | #define POC_SD1_DAT0_33V ((uint32_t)1U << 8U) |
| 344 | #define POC_SD1_CMD_33V ((uint32_t)1U << 7U) |
| 345 | #define POC_SD1_CLK_33V ((uint32_t)1U << 6U) |
| 346 | #define POC_SD0_DAT3_33V ((uint32_t)1U << 5U) |
| 347 | #define POC_SD0_DAT2_33V ((uint32_t)1U << 4U) |
| 348 | #define POC_SD0_DAT1_33V ((uint32_t)1U << 3U) |
| 349 | #define POC_SD0_DAT0_33V ((uint32_t)1U << 2U) |
| 350 | #define POC_SD0_CMD_33V ((uint32_t)1U << 1U) |
| 351 | #define POC_SD0_CLK_33V ((uint32_t)1U << 0U) |
| 352 | |
| 353 | #define IOCTRL32_MASK (0xFFFFFFFEU) |
| 354 | #define POC2_VREF_33V ((uint32_t)1U << 0U) |
| 355 | |
| 356 | #define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U) |
| 357 | #define MOD_SEL0_ADGB_B ((uint32_t)1U << 29U) |
| 358 | #define MOD_SEL0_ADGB_C ((uint32_t)2U << 29U) |
| 359 | #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 28U) |
| 360 | #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 28U) |
| 361 | #define MOD_SEL0_FM_A ((uint32_t)0U << 26U) |
| 362 | #define MOD_SEL0_FM_B ((uint32_t)1U << 26U) |
| 363 | #define MOD_SEL0_FM_C ((uint32_t)2U << 26U) |
| 364 | #define MOD_SEL0_FSO_A ((uint32_t)0U << 25U) |
| 365 | #define MOD_SEL0_FSO_B ((uint32_t)1U << 25U) |
| 366 | #define MOD_SEL0_HSCIF0_A ((uint32_t)0U << 24U) |
| 367 | #define MOD_SEL0_HSCIF0_B ((uint32_t)1U << 24U) |
| 368 | #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 23U) |
| 369 | #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 23U) |
| 370 | #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 22U) |
| 371 | #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 22U) |
| 372 | #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U) |
| 373 | #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U) |
| 374 | #define MOD_SEL0_I2C1_C ((uint32_t)2U << 20U) |
| 375 | #define MOD_SEL0_I2C1_D ((uint32_t)3U << 20U) |
| 376 | #define MOD_SEL0_I2C2_A ((uint32_t)0U << 17U) |
| 377 | #define MOD_SEL0_I2C2_B ((uint32_t)1U << 17U) |
| 378 | #define MOD_SEL0_I2C2_C ((uint32_t)2U << 17U) |
| 379 | #define MOD_SEL0_I2C2_D ((uint32_t)3U << 17U) |
| 380 | #define MOD_SEL0_I2C2_E ((uint32_t)4U << 17U) |
| 381 | #define MOD_SEL0_NDFC_A ((uint32_t)0U << 16U) |
| 382 | #define MOD_SEL0_NDFC_B ((uint32_t)1U << 16U) |
| 383 | #define MOD_SEL0_PWM0_A ((uint32_t)0U << 15U) |
| 384 | #define MOD_SEL0_PWM0_B ((uint32_t)1U << 15U) |
| 385 | #define MOD_SEL0_PWM1_A ((uint32_t)0U << 14U) |
| 386 | #define MOD_SEL0_PWM1_B ((uint32_t)1U << 14U) |
| 387 | #define MOD_SEL0_PWM2_A ((uint32_t)0U << 12U) |
| 388 | #define MOD_SEL0_PWM2_B ((uint32_t)1U << 12U) |
| 389 | #define MOD_SEL0_PWM2_C ((uint32_t)2U << 12U) |
| 390 | #define MOD_SEL0_PWM3_A ((uint32_t)0U << 10U) |
| 391 | #define MOD_SEL0_PWM3_B ((uint32_t)1U << 10U) |
| 392 | #define MOD_SEL0_PWM3_C ((uint32_t)2U << 10U) |
| 393 | #define MOD_SEL0_PWM4_A ((uint32_t)0U << 9U) |
| 394 | #define MOD_SEL0_PWM4_B ((uint32_t)1U << 9U) |
| 395 | #define MOD_SEL0_PWM5_A ((uint32_t)0U << 8U) |
| 396 | #define MOD_SEL0_PWM5_B ((uint32_t)1U << 8U) |
| 397 | #define MOD_SEL0_PWM6_A ((uint32_t)0U << 7U) |
| 398 | #define MOD_SEL0_PWM6_B ((uint32_t)1U << 7U) |
| 399 | #define MOD_SEL0_REMOCON_A ((uint32_t)0U << 5U) |
| 400 | #define MOD_SEL0_REMOCON_B ((uint32_t)1U << 5U) |
| 401 | #define MOD_SEL0_REMOCON_C ((uint32_t)2U << 5U) |
| 402 | #define MOD_SEL0_SCIF_A ((uint32_t)0U << 4U) |
| 403 | #define MOD_SEL0_SCIF_B ((uint32_t)1U << 4U) |
| 404 | #define MOD_SEL0_SCIF0_A ((uint32_t)0U << 3U) |
| 405 | #define MOD_SEL0_SCIF0_B ((uint32_t)1U << 3U) |
| 406 | #define MOD_SEL0_SCIF2_A ((uint32_t)0U << 2U) |
| 407 | #define MOD_SEL0_SCIF2_B ((uint32_t)1U << 2U) |
| 408 | #define MOD_SEL0_SPEED_PULSE_IF_A ((uint32_t)0U << 0U) |
| 409 | #define MOD_SEL0_SPEED_PULSE_IF_B ((uint32_t)1U << 0U) |
| 410 | #define MOD_SEL0_SPEED_PULSE_IF_C ((uint32_t)2U << 0U) |
| 411 | #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 31U) |
| 412 | #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 31U) |
| 413 | #define MOD_SEL1_SSI2_A ((uint32_t)0U << 30U) |
| 414 | #define MOD_SEL1_SSI2_B ((uint32_t)1U << 30U) |
| 415 | #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 29U) |
| 416 | #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 29U) |
| 417 | #define MOD_SEL1_USB20_CH0_A ((uint32_t)0U << 28U) |
| 418 | #define MOD_SEL1_USB20_CH0_B ((uint32_t)1U << 28U) |
| 419 | #define MOD_SEL1_DRIF2_A ((uint32_t)0U << 26U) |
| 420 | #define MOD_SEL1_DRIF2_B ((uint32_t)1U << 26U) |
| 421 | #define MOD_SEL1_DRIF3_A ((uint32_t)0U << 25U) |
| 422 | #define MOD_SEL1_DRIF3_B ((uint32_t)1U << 25U) |
| 423 | #define MOD_SEL1_HSCIF3_A ((uint32_t)0U << 22U) |
| 424 | #define MOD_SEL1_HSCIF3_B ((uint32_t)1U << 22U) |
| 425 | #define MOD_SEL1_HSCIF3_C ((uint32_t)2U << 22U) |
| 426 | #define MOD_SEL1_HSCIF3_D ((uint32_t)3U << 22U) |
| 427 | #define MOD_SEL1_HSCIF3_E ((uint32_t)4U << 22U) |
| 428 | #define MOD_SEL1_HSCIF4_A ((uint32_t)0U << 19U) |
| 429 | #define MOD_SEL1_HSCIF4_B ((uint32_t)1U << 19U) |
| 430 | #define MOD_SEL1_HSCIF4_C ((uint32_t)2U << 19U) |
| 431 | #define MOD_SEL1_HSCIF4_D ((uint32_t)3U << 19U) |
| 432 | #define MOD_SEL1_HSCIF4_E ((uint32_t)4U << 19U) |
| 433 | #define MOD_SEL1_I2C6_A ((uint32_t)0U << 18U) |
| 434 | #define MOD_SEL1_I2C6_B ((uint32_t)1U << 18U) |
| 435 | #define MOD_SEL1_I2C7_A ((uint32_t)0U << 17U) |
| 436 | #define MOD_SEL1_I2C7_B ((uint32_t)1U << 17U) |
| 437 | #define MOD_SEL1_MSIOF2_A ((uint32_t)0U << 16U) |
| 438 | #define MOD_SEL1_MSIOF2_B ((uint32_t)1U << 16U) |
| 439 | #define MOD_SEL1_MSIOF3_A ((uint32_t)0U << 15U) |
| 440 | #define MOD_SEL1_MSIOF3_B ((uint32_t)1U << 15U) |
| 441 | #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) |
| 442 | #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) |
| 443 | #define MOD_SEL1_SCIF3_C ((uint32_t)2U << 13U) |
| 444 | #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 11U) |
| 445 | #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 11U) |
| 446 | #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 11U) |
| 447 | #define MOD_SEL1_SCIF5_A ((uint32_t)0U << 9U) |
| 448 | #define MOD_SEL1_SCIF5_B ((uint32_t)1U << 9U) |
| 449 | #define MOD_SEL1_SCIF5_C ((uint32_t)2U << 9U) |
| 450 | #define MOD_SEL1_VIN4_A ((uint32_t)0U << 8U) |
| 451 | #define MOD_SEL1_VIN4_B ((uint32_t)1U << 8U) |
| 452 | #define MOD_SEL1_VIN5_A ((uint32_t)0U << 7U) |
| 453 | #define MOD_SEL1_VIN5_B ((uint32_t)1U << 7U) |
| 454 | #define MOD_SEL1_ADGC_A ((uint32_t)0U << 5U) |
| 455 | #define MOD_SEL1_ADGC_B ((uint32_t)1U << 5U) |
| 456 | #define MOD_SEL1_ADGC_C ((uint32_t)2U << 5U) |
| 457 | #define MOD_SEL1_SSI9_A ((uint32_t)0U << 4U) |
| 458 | #define MOD_SEL1_SSI9_B ((uint32_t)1U << 4U) |
| 459 | |
| 460 | static void pfc_reg_write(uint32_t addr, uint32_t data); |
| 461 | |
| 462 | static void pfc_reg_write(uint32_t addr, uint32_t data) |
| 463 | { |
| 464 | mmio_write_32(PFC_PMMR, ~data); |
| 465 | mmio_write_32((uintptr_t) addr, data); |
| 466 | } |
| 467 | |
| 468 | void pfc_init_e3(void) |
| 469 | { |
| 470 | uint32_t reg; |
| 471 | |
| 472 | /* initialize module select */ |
| 473 | pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_ADGB_A |
| 474 | | MOD_SEL0_DRIF0_A |
| 475 | | MOD_SEL0_FM_A |
| 476 | | MOD_SEL0_FSO_A |
| 477 | | MOD_SEL0_HSCIF0_A |
| 478 | | MOD_SEL0_HSCIF1_A |
| 479 | | MOD_SEL0_HSCIF2_A |
| 480 | | MOD_SEL0_I2C1_A |
| 481 | | MOD_SEL0_I2C2_A |
| 482 | | MOD_SEL0_NDFC_A |
| 483 | | MOD_SEL0_PWM0_A |
| 484 | | MOD_SEL0_PWM1_A |
| 485 | | MOD_SEL0_PWM2_A |
| 486 | | MOD_SEL0_PWM3_A |
| 487 | | MOD_SEL0_PWM4_A |
| 488 | | MOD_SEL0_PWM5_A |
| 489 | | MOD_SEL0_PWM6_A |
| 490 | | MOD_SEL0_REMOCON_A |
| 491 | | MOD_SEL0_SCIF_A |
| 492 | | MOD_SEL0_SCIF0_A |
| 493 | | MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A); |
| 494 | pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A |
| 495 | | MOD_SEL1_SSI2_A |
| 496 | | MOD_SEL1_TIMER_TMU_A |
| 497 | | MOD_SEL1_USB20_CH0_B |
| 498 | | MOD_SEL1_DRIF2_A |
| 499 | | MOD_SEL1_DRIF3_A |
| 500 | | MOD_SEL1_HSCIF3_A |
| 501 | | MOD_SEL1_HSCIF4_A |
| 502 | | MOD_SEL1_I2C6_A |
| 503 | | MOD_SEL1_I2C7_A |
| 504 | | MOD_SEL1_MSIOF2_A |
| 505 | | MOD_SEL1_MSIOF3_A |
| 506 | | MOD_SEL1_SCIF3_A |
| 507 | | MOD_SEL1_SCIF4_A |
| 508 | | MOD_SEL1_SCIF5_A |
| 509 | | MOD_SEL1_VIN4_A |
| 510 | | MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A); |
| 511 | |
| 512 | /* initialize peripheral function select */ |
| 513 | pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) /* QSPI1_MISO/IO1 */ |
| 514 | |IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */ |
| 515 | |IPSR_20_FUNC(0) /* QSPI1_SPCLK */ |
| 516 | |IPSR_16_FUNC(0) /* QSPI0_IO3 */ |
| 517 | |IPSR_12_FUNC(0) /* QSPI0_IO2 */ |
| 518 | |IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */ |
| 519 | |IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */ |
| 520 | |IPSR_0_FUNC(0)); /* QSPI0_SPCLK */ |
| 521 | pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) /* AVB_RD2 */ |
| 522 | |IPSR_24_FUNC(0) /* AVB_RD1 */ |
| 523 | |IPSR_20_FUNC(0) /* AVB_RD0 */ |
| 524 | |IPSR_16_FUNC(0) /* RPC_RESET# */ |
| 525 | |IPSR_12_FUNC(0) /* RPC_INT# */ |
| 526 | |IPSR_8_FUNC(0) /* QSPI1_SSL */ |
| 527 | |IPSR_4_FUNC(0) /* QSPI1_IO3 */ |
| 528 | |IPSR_0_FUNC(0)); /* QSPI1_IO2 */ |
| 529 | pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1) /* IRQ0 */ |
| 530 | |IPSR_24_FUNC(0) |
| 531 | | IPSR_20_FUNC(0) |
| 532 | | IPSR_16_FUNC(2) /* AVB_LINK */ |
| 533 | |IPSR_12_FUNC(0) |
| 534 | | IPSR_8_FUNC(0) /* AVB_MDC */ |
| 535 | |IPSR_4_FUNC(0) /* AVB_MDIO */ |
| 536 | |IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */ |
| 537 | pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5) /* DU_HSYNC */ |
| 538 | |IPSR_24_FUNC(0) |
| 539 | | IPSR_20_FUNC(0) |
| 540 | | IPSR_16_FUNC(0) |
| 541 | | IPSR_12_FUNC(5) /* DU_DG4 */ |
| 542 | |IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */ |
| 543 | |IPSR_4_FUNC(5) /* DU_DISP */ |
| 544 | |IPSR_0_FUNC(1)); /* IRQ1 */ |
| 545 | pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5) /* DU_DB5 */ |
| 546 | |IPSR_24_FUNC(5) /* DU_DB4 */ |
| 547 | |IPSR_20_FUNC(5) /* DU_DB3 */ |
| 548 | |IPSR_16_FUNC(5) /* DU_DB2 */ |
| 549 | |IPSR_12_FUNC(5) /* DU_DG6 */ |
| 550 | |IPSR_8_FUNC(5) /* DU_VSYNC */ |
| 551 | |IPSR_4_FUNC(5) /* DU_DG5 */ |
| 552 | |IPSR_0_FUNC(5)); /* DU_DG7 */ |
| 553 | pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5) /* DU_DR3 */ |
| 554 | |IPSR_24_FUNC(5) /* DU_DB7 */ |
| 555 | |IPSR_20_FUNC(5) /* DU_DR2 */ |
| 556 | |IPSR_16_FUNC(5) /* DU_DR1 */ |
| 557 | |IPSR_12_FUNC(5) /* DU_DR0 */ |
| 558 | |IPSR_8_FUNC(5) /* DU_DB1 */ |
| 559 | |IPSR_4_FUNC(5) /* DU_DB0 */ |
| 560 | |IPSR_0_FUNC(5)); /* DU_DB6 */ |
| 561 | pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5) /* DU_DG1 */ |
| 562 | |IPSR_24_FUNC(5) /* DU_DG0 */ |
| 563 | |IPSR_20_FUNC(5) /* DU_DR7 */ |
| 564 | |IPSR_16_FUNC(2) /* IRQ5 */ |
| 565 | |IPSR_12_FUNC(5) /* DU_DR6 */ |
| 566 | |IPSR_8_FUNC(5) /* DU_DR5 */ |
| 567 | |IPSR_4_FUNC(0) |
| 568 | | IPSR_0_FUNC(5)); /* DU_DR4 */ |
| 569 | pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) /* SD0_CLK */ |
| 570 | |IPSR_24_FUNC(0) |
| 571 | | IPSR_20_FUNC(5) /* DU_DOTCLKIN0 */ |
| 572 | |IPSR_16_FUNC(5) /* DU_DG3 */ |
| 573 | |IPSR_12_FUNC(0) |
| 574 | | IPSR_8_FUNC(0) |
| 575 | | IPSR_4_FUNC(0) |
| 576 | | IPSR_0_FUNC(5)); /* DU_DG2 */ |
| 577 | pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) /* SD1_DAT0 */ |
| 578 | |IPSR_24_FUNC(0) /* SD1_CMD */ |
| 579 | |IPSR_20_FUNC(0) /* SD1_CLK */ |
| 580 | |IPSR_16_FUNC(0) /* SD0_DAT3 */ |
| 581 | |IPSR_12_FUNC(0) /* SD0_DAT2 */ |
| 582 | |IPSR_8_FUNC(0) /* SD0_DAT1 */ |
| 583 | |IPSR_4_FUNC(0) /* SD0_DAT0 */ |
| 584 | |IPSR_0_FUNC(0)); /* SD0_CMD */ |
| 585 | pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) /* SD3_DAT2 */ |
| 586 | |IPSR_24_FUNC(0) /* SD3_DAT1 */ |
| 587 | |IPSR_20_FUNC(0) /* SD3_DAT0 */ |
| 588 | |IPSR_16_FUNC(0) /* SD3_CMD */ |
| 589 | |IPSR_12_FUNC(0) /* SD3_CLK */ |
| 590 | |IPSR_8_FUNC(0) /* SD1_DAT3 */ |
| 591 | |IPSR_4_FUNC(0) /* SD1_DAT2 */ |
| 592 | |IPSR_0_FUNC(0)); /* SD1_DAT1 */ |
| 593 | pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) /* SD0_WP */ |
| 594 | |IPSR_24_FUNC(0) /* SD0_CD */ |
| 595 | |IPSR_20_FUNC(0) /* SD3_DS */ |
| 596 | |IPSR_16_FUNC(0) /* SD3_DAT7 */ |
| 597 | |IPSR_12_FUNC(0) /* SD3_DAT6 */ |
| 598 | |IPSR_8_FUNC(0) /* SD3_DAT5 */ |
| 599 | |IPSR_4_FUNC(0) /* SD3_DAT4 */ |
| 600 | |IPSR_0_FUNC(0)); /* SD3_DAT3 */ |
| 601 | pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0) |
| 602 | | IPSR_24_FUNC(0) |
| 603 | | IPSR_20_FUNC(2) /* AUDIO_CLKOUT1_A */ |
| 604 | |IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */ |
| 605 | |IPSR_12_FUNC(0) |
| 606 | | IPSR_8_FUNC(0) |
| 607 | | IPSR_4_FUNC(0) /* SD1_WP */ |
| 608 | |IPSR_0_FUNC(0)); /* SD1_CD */ |
| 609 | pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0) |
| 610 | | IPSR_24_FUNC(0) |
| 611 | | IPSR_20_FUNC(0) |
| 612 | | IPSR_16_FUNC(0) |
| 613 | | IPSR_12_FUNC(0) /* RX2_A */ |
| 614 | |IPSR_8_FUNC(0) /* TX2_A */ |
| 615 | |IPSR_4_FUNC(2) /* AUDIO_CLKB_A */ |
| 616 | |IPSR_0_FUNC(0)); |
| 617 | pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0) |
| 618 | | IPSR_24_FUNC(0) |
| 619 | | IPSR_20_FUNC(0) |
| 620 | | IPSR_16_FUNC(0) |
| 621 | | IPSR_12_FUNC(0) |
| 622 | | IPSR_8_FUNC(2) /* AUDIO_CLKC_A */ |
| 623 | |IPSR_4_FUNC(1) /* HTX2_A */ |
| 624 | |IPSR_0_FUNC(1)); /* HRX2_A */ |
| 625 | pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3) /* USB0_PWEN_B */ |
| 626 | |IPSR_24_FUNC(0) /* SSI_SDATA4 */ |
| 627 | |IPSR_20_FUNC(0) /* SSI_SDATA3 */ |
| 628 | |IPSR_16_FUNC(0) /* SSI_WS349 */ |
| 629 | |IPSR_12_FUNC(0) /* SSI_SCK349 */ |
| 630 | |IPSR_8_FUNC(0) |
| 631 | | IPSR_4_FUNC(0) /* SSI_SDATA1 */ |
| 632 | |IPSR_0_FUNC(0)); /* SSI_SDATA0 */ |
| 633 | pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) /* USB30_OVC */ |
| 634 | |IPSR_24_FUNC(0) /* USB30_PWEN */ |
| 635 | |IPSR_20_FUNC(0) /* AUDIO_CLKA */ |
| 636 | |IPSR_16_FUNC(1) /* HRTS2#_A */ |
| 637 | |IPSR_12_FUNC(1) /* HCTS2#_A */ |
| 638 | |IPSR_8_FUNC(0) |
| 639 | | IPSR_4_FUNC(0) |
| 640 | | IPSR_0_FUNC(3)); /* USB0_OVC_B */ |
| 641 | |
| 642 | /* initialize GPIO/perihperal function select */ |
| 643 | pfc_reg_write(PFC_GPSR0, GPSR0_SCL4 |
| 644 | | GPSR0_D15 |
| 645 | | GPSR0_D11 |
| 646 | | GPSR0_D10 |
| 647 | | GPSR0_D9 |
| 648 | | GPSR0_D8 |
| 649 | | GPSR0_D7 |
| 650 | | GPSR0_D6 |
| 651 | | GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0); |
| 652 | pfc_reg_write(PFC_GPSR1, GPSR1_WE0 |
| 653 | | GPSR1_CS0 |
| 654 | | GPSR1_A19 |
| 655 | | GPSR1_A18 |
| 656 | | GPSR1_A17 |
| 657 | | GPSR1_A16 |
| 658 | | GPSR1_A15 |
| 659 | | GPSR1_A14 |
| 660 | | GPSR1_A13 |
| 661 | | GPSR1_A12 |
| 662 | | GPSR1_A11 |
| 663 | | GPSR1_A10 |
| 664 | | GPSR1_A9 |
| 665 | | GPSR1_A8 |
| 666 | | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0); |
| 667 | pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED |
| 668 | | GPSR2_BIT26_REVERCED |
| 669 | | GPSR2_RD |
| 670 | | GPSR2_AVB_PHY_INT |
| 671 | | GPSR2_AVB_TXCREFCLK |
| 672 | | GPSR2_AVB_RD3 |
| 673 | | GPSR2_AVB_RD2 |
| 674 | | GPSR2_AVB_RD1 |
| 675 | | GPSR2_AVB_RD0 |
| 676 | | GPSR2_AVB_RXC |
| 677 | | GPSR2_AVB_RX_CTL |
| 678 | | GPSR2_RPC_RESET |
| 679 | | GPSR2_RPC_RPC_INT |
| 680 | | GPSR2_QSPI1_SSL |
| 681 | | GPSR2_QSPI1_IO3 |
| 682 | | GPSR2_QSPI1_IO2 |
| 683 | | GPSR2_QSPI1_MISO_IO1 |
| 684 | | GPSR2_QSPI1_MOSI_IO0 |
| 685 | | GPSR2_QSPI1_SPCLK |
| 686 | | GPSR2_QSPI0_SSL |
| 687 | | GPSR2_QSPI0_IO3 |
| 688 | | GPSR2_QSPI0_IO2 |
| 689 | | GPSR2_QSPI0_MISO_IO1 |
| 690 | | GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK); |
| 691 | pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP |
| 692 | | GPSR3_SD1_CD |
| 693 | | GPSR3_SD0_WP |
| 694 | | GPSR3_SD0_CD |
| 695 | | GPSR3_SD1_DAT3 |
| 696 | | GPSR3_SD1_DAT2 |
| 697 | | GPSR3_SD1_DAT1 |
| 698 | | GPSR3_SD1_DAT0 |
| 699 | | GPSR3_SD1_CMD |
| 700 | | GPSR3_SD1_CLK |
| 701 | | GPSR3_SD0_DAT3 |
| 702 | | GPSR3_SD0_DAT2 |
| 703 | | GPSR3_SD0_DAT1 |
| 704 | | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK); |
| 705 | pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS |
| 706 | | GPSR4_SD3_DAT7 |
| 707 | | GPSR4_SD3_DAT6 |
| 708 | | GPSR4_SD3_DAT5 |
| 709 | | GPSR4_SD3_DAT4 |
| 710 | | GPSR4_SD3_DAT3 |
| 711 | | GPSR4_SD3_DAT2 |
| 712 | | GPSR4_SD3_DAT1 |
| 713 | | GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK); |
| 714 | pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9 |
| 715 | | GPSR5_MSIOF0_SS2 |
| 716 | | GPSR5_MSIOF0_SS1 |
| 717 | | GPSR5_RX2_A |
| 718 | | GPSR5_TX2_A |
| 719 | | GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A); |
| 720 | pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN |
| 721 | | GPSR6_SSI_SDATA6 |
| 722 | | GPSR6_SSI_WS6 |
| 723 | | GPSR6_SSI_WS5 |
| 724 | | GPSR6_SSI_SCK5 |
| 725 | | GPSR6_SSI_SDATA4 |
| 726 | | GPSR6_USB30_OVC |
| 727 | | GPSR6_AUDIO_CLKA |
| 728 | | GPSR6_SSI_SDATA3 |
| 729 | | GPSR6_SSI_WS349 |
| 730 | | GPSR6_SSI_SCK349 |
| 731 | | GPSR6_SSI_SDATA1 |
| 732 | | GPSR6_SSI_SDATA0 |
| 733 | | GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239); |
| 734 | |
| 735 | /* initialize POC control */ |
| 736 | reg = mmio_read_32(PFC_IOCTRL30); |
| 737 | reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V |
| 738 | | POC_SD1_DAT2_33V |
| 739 | | POC_SD1_DAT1_33V |
| 740 | | POC_SD1_DAT0_33V |
| 741 | | POC_SD1_CMD_33V |
| 742 | | POC_SD1_CLK_33V |
| 743 | | POC_SD0_DAT3_33V |
| 744 | | POC_SD0_DAT2_33V |
| 745 | | POC_SD0_DAT1_33V |
| 746 | | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V); |
| 747 | pfc_reg_write(PFC_IOCTRL30, reg); |
| 748 | reg = mmio_read_32(PFC_IOCTRL32); |
| 749 | reg = (reg & IOCTRL32_MASK); |
| 750 | pfc_reg_write(PFC_IOCTRL32, reg); |
| 751 | |
| 752 | /* initialize LSI pin pull-up/down control */ |
| 753 | pfc_reg_write(PFC_PUD0, 0xFDF80000U); |
| 754 | pfc_reg_write(PFC_PUD1, 0xCE298464U); |
| 755 | pfc_reg_write(PFC_PUD2, 0xA4C380F4U); |
| 756 | pfc_reg_write(PFC_PUD3, 0x0000079FU); |
| 757 | pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU); |
| 758 | pfc_reg_write(PFC_PUD5, 0x40000000U); |
| 759 | |
| 760 | /* initialize LSI pin pull-enable register */ |
| 761 | pfc_reg_write(PFC_PUEN0, 0xFFF00000U); |
| 762 | pfc_reg_write(PFC_PUEN1, 0x00000000U); |
| 763 | pfc_reg_write(PFC_PUEN2, 0x00000004U); |
| 764 | pfc_reg_write(PFC_PUEN3, 0x00000000U); |
| 765 | pfc_reg_write(PFC_PUEN4, 0x07800010U); |
| 766 | pfc_reg_write(PFC_PUEN5, 0x00000000U); |
| 767 | |
| 768 | /* initialize positive/negative logic select */ |
| 769 | mmio_write_32(GPIO_POSNEG0, 0x00000000U); |
| 770 | mmio_write_32(GPIO_POSNEG1, 0x00000000U); |
| 771 | mmio_write_32(GPIO_POSNEG2, 0x00000000U); |
| 772 | mmio_write_32(GPIO_POSNEG3, 0x00000000U); |
| 773 | mmio_write_32(GPIO_POSNEG4, 0x00000000U); |
| 774 | mmio_write_32(GPIO_POSNEG5, 0x00000000U); |
| 775 | mmio_write_32(GPIO_POSNEG6, 0x00000000U); |
| 776 | |
| 777 | /* initialize general IO/interrupt switching */ |
| 778 | mmio_write_32(GPIO_IOINTSEL0, 0x00020000U); |
| 779 | mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); |
| 780 | mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); |
| 781 | mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); |
| 782 | mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); |
| 783 | mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); |
| 784 | mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); |
| 785 | |
| 786 | /* initialize general output register */ |
| 787 | mmio_write_32(GPIO_OUTDT0, 0x00000010U); |
| 788 | mmio_write_32(GPIO_OUTDT1, 0x00100000U); |
| 789 | mmio_write_32(GPIO_OUTDT2, 0x00000000U); |
| 790 | mmio_write_32(GPIO_OUTDT3, 0x00008000U); |
| 791 | mmio_write_32(GPIO_OUTDT5, 0x00060000U); |
| 792 | mmio_write_32(GPIO_OUTDT6, 0x00000000U); |
| 793 | |
| 794 | /* initialize general input/output switching */ |
| 795 | mmio_write_32(GPIO_INOUTSEL0, 0x00000010U); |
| 796 | mmio_write_32(GPIO_INOUTSEL1, 0x00100020U); |
| 797 | mmio_write_32(GPIO_INOUTSEL2, 0x03000000U); |
| 798 | mmio_write_32(GPIO_INOUTSEL3, 0x00008000U); |
| 799 | mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); |
| 800 | mmio_write_32(GPIO_INOUTSEL5, 0x00060000U); |
| 801 | mmio_write_32(GPIO_INOUTSEL6, 0x00004000U); |
| 802 | } |