| Okash Khawaja | f5445fd | 2022-04-21 10:59:34 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2022, Google LLC. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <asm_macros.S> |
| 8 | #include <cortex_x1.h> |
| 9 | #include <cpu_macros.S> |
| 10 | |
| 11 | /* Hardware handled coherency */ |
| 12 | #if HW_ASSISTED_COHERENCY == 0 |
| 13 | #error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 14 | #endif |
| 15 | |
| 16 | /* 64-bit only core */ |
| 17 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 18 | #error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 19 | #endif |
| 20 | |
| 21 | func cortex_x1_reset_func |
| 22 | ret |
| 23 | endfunc cortex_x1_reset_func |
| 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * HW will do the cache maintenance while powering down |
| 27 | * --------------------------------------------- |
| 28 | */ |
| 29 | func cortex_x1_core_pwr_dwn |
| 30 | /* --------------------------------------------- |
| 31 | * Enable CPU power down bit in power control register |
| 32 | * --------------------------------------------- |
| 33 | */ |
| 34 | mrs x0, CORTEX_X1_CPUPWRCTLR_EL1 |
| 35 | orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK |
| 36 | msr CORTEX_X1_CPUPWRCTLR_EL1, x0 |
| 37 | isb |
| 38 | ret |
| 39 | endfunc cortex_x1_core_pwr_dwn |
| 40 | |
| 41 | #if REPORT_ERRATA |
| 42 | /* |
| 43 | * Errata printing function for Cortex X1. Must follow AAPCS. |
| 44 | */ |
| 45 | func cortex_x1_errata_report |
| 46 | ret |
| 47 | endfunc cortex_x1_errata_report |
| 48 | #endif |
| 49 | |
| 50 | /* --------------------------------------------- |
| 51 | * This function provides Cortex X1 specific |
| 52 | * register information for crash reporting. |
| 53 | * It needs to return with x6 pointing to |
| 54 | * a list of register names in ascii and |
| 55 | * x8 - x15 having values of registers to be |
| 56 | * reported. |
| 57 | * --------------------------------------------- |
| 58 | */ |
| 59 | .section .rodata.cortex_x1_regs, "aS" |
| 60 | cortex_x1_regs: /* The ascii list of register names to be reported */ |
| 61 | .asciz "cpuectlr_el1", "" |
| 62 | |
| 63 | func cortex_x1_cpu_reg_dump |
| 64 | adr x6, cortex_x1_regs |
| 65 | mrs x8, CORTEX_X1_CPUECTLR_EL1 |
| 66 | ret |
| 67 | endfunc cortex_x1_cpu_reg_dump |
| 68 | |
| 69 | declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \ |
| 70 | cortex_x1_reset_func, \ |
| 71 | cortex_x1_core_pwr_dwn |