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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <bl_common.h>
32#include <platform.h>
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000033#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35
36 .globl bl31_entrypoint
37
38
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000039 .section .text, "ax"; .align 3
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41 /* -----------------------------------------------------
42 * bl31_entrypoint() is the cold boot entrypoint,
43 * executed only by the primary cpu.
44 * -----------------------------------------------------
45 */
46
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +000047bl31_entrypoint: ; .type bl31_entrypoint, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +010048 /* ---------------------------------------------
49 * BL2 has populated x0,x3,x4 with the opcode
50 * indicating BL31 should be run, memory layout
51 * of the trusted SRAM available to BL31 and
52 * information about running the non-trusted
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000053 * software already loaded by BL2.
54 * ---------------------------------------------
55 */
56
57 /* ---------------------------------------------
58 * Set the exception vector to something sane.
59 * ---------------------------------------------
60 */
61 adr x1, runtime_exceptions
62 msr vbar_el3, x1
63
Harry Liebel4f603682014-01-14 18:11:48 +000064 /* ---------------------------------------------------------------------
65 * The initial state of the Architectural feature trap register
66 * (CPTR_EL3) is unknown and it must be set to a known state. All
67 * feature traps are disabled. Some bits in this register are marked as
68 * Reserved and should not be modified.
69 *
70 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
71 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
72 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
73 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
74 * access to trace functionality is not supported, this bit is RES0.
75 * CPTR_EL3.TFP: This causes instructions that access the registers
76 * associated with Floating Point and Advanced SIMD execution to trap
77 * to EL3 when executed from any exception level, unless trapped to EL1
78 * or EL2.
79 * ---------------------------------------------------------------------
80 */
81 mrs x1, cptr_el3
82 bic w1, w1, #TCPAC_BIT
83 bic w1, w1, #TTA_BIT
84 bic w1, w1, #TFP_BIT
85 msr cptr_el3, x1
86
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000087 /* ---------------------------------------------
88 * Enable the instruction cache.
89 * ---------------------------------------------
90 */
91 mrs x1, sctlr_el3
92 orr x1, x1, #SCTLR_I_BIT
93 msr sctlr_el3, x1
94
95 isb
96
97 /* ---------------------------------------------
98 * Check the opcodes out of paranoia.
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 * ---------------------------------------------
100 */
101 mov x19, #RUN_IMAGE
102 cmp x0, x19
103 b.ne _panic
104 mov x20, x3
105 mov x21, x4
106
107 /* ---------------------------------------------
108 * This is BL31 which is expected to be executed
109 * only by the primary cpu (at least for now).
110 * So, make sure no secondary has lost its way.
111 * ---------------------------------------------
112 */
113 bl read_mpidr
114 mov x19, x0
115 bl platform_is_primary_cpu
116 cbz x0, _panic
117
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000118 /* ---------------------------------------------
119 * Zero out NOBITS sections. There are 2 of them:
120 * - the .bss section;
121 * - the coherent memory section.
122 * ---------------------------------------------
123 */
124 ldr x0, =__BSS_START__
125 ldr x1, =__BSS_SIZE__
126 bl zeromem16
127
128 ldr x0, =__COHERENT_RAM_START__
129 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
130 bl zeromem16
131
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132 /* --------------------------------------------
133 * Give ourselves a small coherent stack to
134 * ease the pain of initializing the MMU
135 * --------------------------------------------
136 */
137 mov x0, x19
138 bl platform_set_coherent_stack
139
140 /* ---------------------------------------------
141 * Perform platform specific early arch. setup
142 * ---------------------------------------------
143 */
144 mov x0, x20
145 mov x1, x21
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146 bl bl31_early_platform_setup
147 bl bl31_plat_arch_setup
148
149 /* ---------------------------------------------
150 * Give ourselves a stack allocated in Normal
151 * -IS-WBWA memory
152 * ---------------------------------------------
153 */
154 mov x0, x19
155 bl platform_set_stack
156
157 /* ---------------------------------------------
158 * Use SP_EL0 to initialize BL31. It allows us
159 * to jump to the next image without having to
160 * come back here to ensure all of the stack's
161 * been popped out. run_image() is not nice
162 * enough to reset the stack pointer before
163 * handing control to the next stage.
164 * ---------------------------------------------
165 */
166 mov x0, sp
167 msr sp_el0, x0
168 msr spsel, #0
169 isb
170
171 /* ---------------------------------------------
172 * Jump to main function.
173 * ---------------------------------------------
174 */
175 bl bl31_main
176
177_panic:
178 b _panic