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Deepak Pandey9cbacf62018-08-08 10:32:51 +05301/*
John Tsichritzis56369c12019-02-19 13:49:06 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Deepak Pandey9cbacf62018-08-08 10:32:51 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
John Tsichritzis56369c12019-02-19 13:49:06 +00009#include <neoverse_n1.h>
Deepak Pandey9cbacf62018-08-08 10:32:51 +053010#include <cpu_macros.S>
11#include <platform_def.h>
12
13 .globl plat_arm_calc_core_pos
14 .globl plat_reset_handler
15
16 /* -----------------------------------------------------
17 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
18 *
19 * Helper function to calculate the core position.
20 * (ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) +
21 * (CPUId * N1SDP_MAX_PE_PER_CPU) +
22 * ThreadId
23 *
24 * which can be simplified as:
25 *
26 * ((ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) *
27 * N1SDP_MAX_PE_PER_CPU) + ThreadId
28 * ------------------------------------------------------
29 */
30
31func plat_arm_calc_core_pos
32 mov x3, x0
33
34 /*
35 * The MT bit in MPIDR is always set for n1sdp and the
36 * affinity level 0 corresponds to thread affinity level.
37 */
38
39 /* Extract individual affinity fields from MPIDR */
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
43
44 /* Compute linear position */
45 mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
46 madd x1, x2, x4, x1
47 mov x5, #N1SDP_MAX_PE_PER_CPU
48 madd x0, x1, x5, x0
49 ret
50endfunc plat_arm_calc_core_pos
51
52 /* -----------------------------------------------------
53 * void plat_reset_handler(void);
54 *
55 * Determine the CPU MIDR and disable power down bit for
56 * that CPU.
57 * -----------------------------------------------------
58 */
59
60func plat_reset_handler
John Tsichritzis56369c12019-02-19 13:49:06 +000061 jump_if_cpu_midr NEOVERSE_N1_MIDR, N1
Deepak Pandey9cbacf62018-08-08 10:32:51 +053062 ret
63
64 /* -----------------------------------------------------
65 * Disable CPU power down bit in power control register
66 * -----------------------------------------------------
67 */
John Tsichritzis56369c12019-02-19 13:49:06 +000068N1:
69 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
70 bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
71 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
Deepak Pandey9cbacf62018-08-08 10:32:51 +053072 isb
73 ret
74endfunc plat_reset_handler