Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 7 | #include <arch_helpers.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 8 | #include <assert.h> |
| 9 | #include <debug.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 10 | #include <memctrl.h> |
Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 11 | #include <memctrl_v1.h> |
| 12 | #include <mmio.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 13 | #include <string.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 14 | #include <tegra_def.h> |
Douglas Raillard | a8954fc | 2017-01-26 15:54:44 +0000 | [diff] [blame] | 15 | #include <utils.h> |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 16 | #include <xlat_tables_v2.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 17 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 18 | #define TEGRA_GPU_RESET_REG_OFFSET 0x28c |
| 19 | #define GPU_RESET_BIT (1 << 24) |
| 20 | |
| 21 | /* Video Memory base and size (live values) */ |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 22 | static uint64_t video_mem_base; |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 23 | static uint64_t video_mem_size; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * Init SMMU. |
| 27 | */ |
| 28 | void tegra_memctrl_setup(void) |
| 29 | { |
| 30 | /* |
| 31 | * Setup the Memory controller to allow only secure accesses to |
| 32 | * the TZDRAM carveout |
| 33 | */ |
Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 34 | INFO("Tegra Memory Controller (v1)\n"); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 35 | |
| 36 | /* allow translations for all MC engines */ |
| 37 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, |
| 38 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 39 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, |
| 40 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 41 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, |
| 42 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 43 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, |
| 44 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 45 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, |
| 46 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 47 | |
| 48 | tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); |
| 49 | |
| 50 | tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); |
| 51 | tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); |
| 52 | |
| 53 | /* flush PTC and TLB */ |
| 54 | tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); |
| 55 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
| 56 | tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); |
| 57 | |
| 58 | /* enable SMMU */ |
| 59 | tegra_mc_write_32(MC_SMMU_CONFIG_0, |
| 60 | MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); |
| 61 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 62 | |
| 63 | /* video memory carveout */ |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 64 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 65 | (uint32_t)(video_mem_base >> 32)); |
| 66 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base); |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 67 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 71 | * Restore Memory Controller settings after "System Suspend" |
| 72 | */ |
| 73 | void tegra_memctrl_restore_settings(void) |
| 74 | { |
| 75 | tegra_memctrl_setup(); |
| 76 | } |
| 77 | |
| 78 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 79 | * Secure the BL31 DRAM aperture. |
| 80 | * |
| 81 | * phys_base = physical base of TZDRAM aperture |
| 82 | * size_in_bytes = size of aperture in bytes |
| 83 | */ |
| 84 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 85 | { |
| 86 | /* |
| 87 | * Setup the Memory controller to allow only secure accesses to |
| 88 | * the TZDRAM carveout |
| 89 | */ |
| 90 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 91 | |
| 92 | tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); |
| 93 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 94 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 95 | |
Varun Wadekar | 0dc9181 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 96 | /* |
| 97 | * Secure the BL31 TZRAM aperture. |
| 98 | * |
| 99 | * phys_base = physical base of TZRAM aperture |
| 100 | * size_in_bytes = size of aperture in bytes |
| 101 | */ |
| 102 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 103 | { |
| 104 | /* |
| 105 | * The v1 hardware controller does not have any registers |
| 106 | * for setting up the on-chip TZRAM. |
| 107 | */ |
| 108 | } |
| 109 | |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 110 | static void tegra_clear_videomem(uintptr_t non_overlap_area_start, |
| 111 | unsigned long long non_overlap_area_size) |
| 112 | { |
| 113 | /* |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 114 | * Map the NS memory first, clean it and then unmap it. |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 115 | */ |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 116 | mmap_add_dynamic_region(non_overlap_area_start, /* PA */ |
| 117 | non_overlap_area_start, /* VA */ |
| 118 | non_overlap_area_size, /* size */ |
| 119 | MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ |
| 120 | |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 121 | zeromem((void *)non_overlap_area_start, non_overlap_area_size); |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 122 | flush_dcache_range(non_overlap_area_start, non_overlap_area_size); |
| 123 | |
| 124 | mmap_remove_dynamic_region(non_overlap_area_start, |
| 125 | non_overlap_area_size); |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 126 | } |
| 127 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 128 | /* |
| 129 | * Program the Video Memory carveout region |
| 130 | * |
| 131 | * phys_base = physical base of aperture |
| 132 | * size_in_bytes = size of aperture in bytes |
| 133 | */ |
| 134 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 135 | { |
| 136 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); |
| 137 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
| 138 | uint32_t regval; |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 139 | unsigned long long non_overlap_area_size; |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 140 | |
| 141 | /* |
| 142 | * The GPU is the user of the Video Memory region. In order to |
| 143 | * transition to the new memory region smoothly, we program the |
| 144 | * new base/size ONLY if the GPU is in reset mode. |
| 145 | */ |
| 146 | regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); |
| 147 | if ((regval & GPU_RESET_BIT) == 0) { |
| 148 | ERROR("GPU not in reset! Video Memory setup failed\n"); |
| 149 | return; |
| 150 | } |
| 151 | |
| 152 | /* |
| 153 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 154 | * Memory region |
| 155 | */ |
| 156 | INFO("Configuring Video Memory Carveout\n"); |
| 157 | |
| 158 | /* |
| 159 | * Configure Memory Controller directly for the first time. |
| 160 | */ |
| 161 | if (video_mem_base == 0) |
| 162 | goto done; |
| 163 | |
| 164 | /* |
| 165 | * Clear the old regions now being exposed. The following cases |
| 166 | * can occur - |
| 167 | * |
| 168 | * 1. clear whole old region (no overlap with new region) |
| 169 | * 2. clear old sub-region below new base |
| 170 | * 3. clear old sub-region above new end |
| 171 | */ |
| 172 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 173 | |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 174 | if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 175 | tegra_clear_videomem(video_mem_base, video_mem_size << 20); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 176 | } else { |
| 177 | if (video_mem_base < phys_base) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 178 | non_overlap_area_size = phys_base - video_mem_base; |
| 179 | tegra_clear_videomem(video_mem_base, non_overlap_area_size); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 180 | } |
| 181 | if (vmem_end_old > vmem_end_new) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 182 | non_overlap_area_size = vmem_end_old - vmem_end_new; |
| 183 | tegra_clear_videomem(vmem_end_new, non_overlap_area_size); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 184 | } |
| 185 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 186 | |
| 187 | done: |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 188 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32)); |
| 189 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 190 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
| 191 | |
| 192 | /* store new values */ |
| 193 | video_mem_base = phys_base; |
| 194 | video_mem_size = size_in_bytes >> 20; |
| 195 | } |
Varun Wadekar | c92050b | 2017-03-29 14:57:29 -0700 | [diff] [blame] | 196 | |
| 197 | /* |
| 198 | * During boot, USB3 and flash media (SDMMC/SATA) devices need access to |
| 199 | * IRAM. Because these clients connect to the MC and do not have a direct |
| 200 | * path to the IRAM, the MC implements AHB redirection during boot to allow |
| 201 | * path to IRAM. In this mode, accesses to a programmed memory address aperture |
| 202 | * are directed to the AHB bus, allowing access to the IRAM. The AHB aperture |
| 203 | * is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are |
| 204 | * initialized to disable this aperture. |
| 205 | * |
| 206 | * Once bootup is complete, we must program IRAM base to 0xffffffff and |
| 207 | * IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then |
| 208 | * potentially accessible in this address range. These aperture registers |
| 209 | * also have an access_control/lock bit. After disabling the aperture, the |
| 210 | * access_control register should be programmed to lock the registers. |
| 211 | */ |
| 212 | void tegra_memctrl_disable_ahb_redirection(void) |
| 213 | { |
| 214 | /* program the aperture registers */ |
| 215 | tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF); |
| 216 | tegra_mc_write_32(MC_IRAM_TOP_LO, 0); |
| 217 | tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0); |
| 218 | |
| 219 | /* lock the aperture registers */ |
| 220 | tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES); |
| 221 | } |