blob: 2f6f5ea4c6af07fe0a9e7ca941d8fbda39ce23cc [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <console.h>
32#include <platform.h>
33#include <pl011.h>
34
35/*
36 * TODO: Console init functions shoule be in a console.c. This file should
37 * only contain the pl011 accessors.
38 */
39void console_init(void)
40{
41 unsigned int divisor;
42
43 /* Baud Rate */
44
45#if defined(PL011_INTEGER) && defined(PL011_FRACTIONAL)
46 mmio_write_32(PL011_BASE + UARTIBRD, PL011_INTEGER);
47 mmio_write_32(PL011_BASE + UARTFBRD, PL011_FRACTIONAL);
48#else
49 divisor = (PL011_CLK_IN_HZ * 4) / PL011_BAUDRATE;
50 mmio_write_32(PL011_BASE + UARTIBRD, divisor >> 6);
51 mmio_write_32(PL011_BASE + UARTFBRD, divisor & 0x3F);
52#endif
53
54
55 mmio_write_32(PL011_BASE + UARTLCR_H, PL011_LINE_CONTROL);
56
57 /* Clear any pending errors */
58 mmio_write_32(PL011_BASE + UARTECR, 0);
59
60 /* Enable tx, rx, and uart overall */
61 mmio_write_32(PL011_BASE + UARTCR,
62 PL011_UARTCR_RXE | PL011_UARTCR_TXE |
63 PL011_UARTCR_UARTEN);
64}
65
66int console_putc(int c)
67{
68 if (c == '\n') {
69 console_putc('\r');
70 }
71 while ((mmio_read_32(PL011_BASE + UARTFR) & PL011_UARTFR_TXFE)
72 == 0) ;
73 mmio_write_32(PL011_BASE + UARTDR, c);
74 return c;
75}
76
77int console_getc(void)
78{
79 while ((mmio_read_32(PL011_BASE + UARTFR) & PL011_UARTFR_RXFE)
80 != 0) ;
81 return mmio_read_32(PL011_BASE + UARTDR);
82}