blob: 5313fbde2d54edd256f7a0c5abbd27abfee00b0d [file] [log] [blame]
Ryan Harkin03925792015-03-17 14:52:39 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Ryan Harkin03925792015-03-17 14:52:39 +00005 */
6
7#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <drivers/delay_timer.h>
10#include <lib/mmio.h>
Ryan Harkin03925792015-03-17 14:52:39 +000011
12uintptr_t sp804_base_addr;
13
14#define SP804_TIMER1_LOAD (sp804_base_addr + 0x000)
15#define SP804_TIMER1_VALUE (sp804_base_addr + 0x004)
16#define SP804_TIMER1_CONTROL (sp804_base_addr + 0x008)
17#define SP804_TIMER1_BGLOAD (sp804_base_addr + 0x018)
18
19#define TIMER_CTRL_ONESHOT (1 << 0)
20#define TIMER_CTRL_32BIT (1 << 1)
21#define TIMER_CTRL_DIV1 (0 << 2)
22#define TIMER_CTRL_DIV16 (1 << 2)
23#define TIMER_CTRL_DIV256 (2 << 2)
24#define TIMER_CTRL_IE (1 << 5)
25#define TIMER_CTRL_PERIODIC (1 << 6)
26#define TIMER_CTRL_ENABLE (1 << 7)
27
28/********************************************************************
29 * The SP804 timer delay function
30 ********************************************************************/
31uint32_t sp804_get_timer_value(void)
32{
33 return mmio_read_32(SP804_TIMER1_VALUE);
34}
35
36/********************************************************************
37 * Initialize the 1st timer in the SP804 dual timer with a base
38 * address and a timer ops
39 ********************************************************************/
40void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops)
41{
42 assert(base_addr != 0);
43 assert(ops != 0 && ops->get_timer_value == sp804_get_timer_value);
44
45 sp804_base_addr = base_addr;
46 timer_init(ops);
47
48 /* disable timer1 */
49 mmio_write_32(SP804_TIMER1_CONTROL, 0);
50 mmio_write_32(SP804_TIMER1_LOAD, UINT32_MAX);
51 mmio_write_32(SP804_TIMER1_VALUE, UINT32_MAX);
52
53 /* enable as a free running 32-bit counter */
54 mmio_write_32(SP804_TIMER1_CONTROL,
55 TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE);
56}