Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 3 | * Copyright 2025 NXP |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 8 | #ifndef IMX_USDHC_H |
| 9 | #define IMX_USDHC_H |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 10 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <drivers/mmc.h> |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 12 | |
| 13 | typedef struct imx_usdhc_params { |
| 14 | uintptr_t reg_base; |
| 15 | int clk_rate; |
| 16 | int bus_width; |
| 17 | unsigned int flags; |
| 18 | } imx_usdhc_params_t; |
| 19 | |
| 20 | void imx_usdhc_init(imx_usdhc_params_t *params, |
| 21 | struct mmc_device_info *mmc_dev_info); |
| 22 | |
| 23 | /* iMX MMC registers definition */ |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 24 | #define DSADDR 0x000U |
| 25 | #define BLKATT 0x004U |
| 26 | #define CMDARG 0x008U |
| 27 | #define CMDRSP0 0x010U |
| 28 | #define CMDRSP1 0x014U |
| 29 | #define CMDRSP2 0x018U |
| 30 | #define CMDRSP3 0x01cU |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 31 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 32 | #define XFERTYPE 0x00cU |
| 33 | #define XFERTYPE_CMD(x) (((x) & 0x3fU) << 24U) |
| 34 | #define XFERTYPE_CMDTYP_ABORT (3U << 22U) |
| 35 | #define XFERTYPE_DPSEL BIT_32(21U) |
| 36 | #define XFERTYPE_CICEN BIT_32(20U) |
| 37 | #define XFERTYPE_CCCEN BIT_32(19U) |
| 38 | #define XFERTYPE_RSPTYP_136 BIT_32(16U) |
| 39 | #define XFERTYPE_RSPTYP_48 BIT_32(17U) |
| 40 | #define XFERTYPE_RSPTYP_48_BUSY (BIT_32(16U) | BIT_32(17U)) |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 41 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 42 | #define PSTATE 0x024U |
| 43 | #define PSTATE_DAT0 BIT_32(24U) |
| 44 | #define PSTATE_DLA BIT_32(2U) |
| 45 | #define PSTATE_CDIHB BIT_32(1U) |
| 46 | #define PSTATE_CIHB BIT_32(0U) |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 47 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 48 | #define PROTCTRL 0x028U |
| 49 | #define PROTCTRL_LE BIT_32(5U) |
| 50 | #define PROTCTRL_WIDTH_4 BIT_32(1U) |
| 51 | #define PROTCTRL_WIDTH_8 BIT_32(2U) |
| 52 | #define PROTCTRL_WIDTH_MASK 0x6U |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 53 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 54 | #define SYSCTRL 0x02cU |
| 55 | #define SYSCTRL_RSTD BIT_32(26U) |
| 56 | #define SYSCTRL_RSTC BIT_32(25U) |
| 57 | #define SYSCTRL_RSTA BIT_32(24U) |
| 58 | #define SYSCTRL_CLOCK_MASK GENMASK_32(15U, 4U) |
| 59 | #define SYSCTRL_TIMEOUT_MASK GENMASK_32(19U, 16U) |
| 60 | #define SYSCTRL_TIMEOUT(x) ((0xfU & (x)) << 16U) |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 61 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 62 | #define INTSTAT 0x030U |
| 63 | #define INTSTAT_DMAE BIT_32(28U) |
| 64 | #define INTSTAT_DEBE BIT_32(22U) |
| 65 | #define INTSTAT_DCE BIT_32(21U) |
| 66 | #define INTSTAT_DTOE BIT_32(20U) |
| 67 | #define INTSTAT_CIE BIT_32(19U) |
| 68 | #define INTSTAT_CEBE BIT_32(18U) |
| 69 | #define INTSTAT_CCE BIT_32(17U) |
| 70 | #define INTSTAT_DINT BIT_32(3U) |
| 71 | #define INTSTAT_BGE BIT_32(2U) |
| 72 | #define INTSTAT_TC BIT_32(1U) |
| 73 | #define INTSTAT_CC BIT_32(0U) |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 74 | #define CMD_ERR (INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE) |
| 75 | #define DATA_ERR (INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \ |
| 76 | INTSTAT_DTOE) |
| 77 | #define DATA_COMPLETE (INTSTAT_DINT | INTSTAT_TC) |
| 78 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 79 | #define INTSTATEN 0x034U |
| 80 | #define INTSTATEN_DEBE BIT_32(22U) |
| 81 | #define INTSTATEN_DCE BIT_32(21U) |
| 82 | #define INTSTATEN_DTOE BIT_32(20U) |
| 83 | #define INTSTATEN_CIE BIT_32(19U) |
| 84 | #define INTSTATEN_CEBE BIT_32(18U) |
| 85 | #define INTSTATEN_CCE BIT_32(17U) |
| 86 | #define INTSTATEN_CTOE BIT_32(16U) |
| 87 | #define INTSTATEN_CINT BIT_32(8U) |
| 88 | #define INTSTATEN_BRR BIT_32(5U) |
| 89 | #define INTSTATEN_BWR BIT_32(4U) |
| 90 | #define INTSTATEN_DINT BIT_32(3U) |
| 91 | #define INTSTATEN_TC BIT_32(1U) |
| 92 | #define INTSTATEN_CC BIT_32(0U) |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 93 | #define EMMC_INTSTATEN_BITS (INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \ |
| 94 | INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \ |
| 95 | INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \ |
| 96 | INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \ |
| 97 | INTSTATEN_DEBE) |
| 98 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 99 | #define INTSIGEN 0x038U |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 100 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 101 | #define WATERMARKLEV 0x044U |
| 102 | #define WMKLV_RD_MASK GENMASK_32(7U, 0U) |
| 103 | #define WMKLV_WR_MASK GENMASK_32(23U, 16U) |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 104 | #define WMKLV_MASK (WMKLV_RD_MASK | WMKLV_WR_MASK) |
| 105 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 106 | #define MIXCTRL 0x048U |
| 107 | #define MIXCTRL_MSBSEL BIT_32(5U) |
| 108 | #define MIXCTRL_DTDSEL BIT_32(4U) |
| 109 | #define MIXCTRL_DDREN BIT_32(3U) |
| 110 | #define MIXCTRL_AC12EN BIT_32(2U) |
| 111 | #define MIXCTRL_BCEN BIT_32(1U) |
| 112 | #define MIXCTRL_DMAEN BIT_32(0U) |
| 113 | #define MIXCTRL_DATMASK 0x7fU |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 114 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 115 | #define DLLCTRL 0x060U |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 116 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 117 | #define CLKTUNECTRLSTS 0x068U |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 118 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 119 | #define VENDSPEC 0x0c0U |
| 120 | #define VENDSPEC_RSRV1 BIT_32(29U) |
| 121 | #define VENDSPEC_CARD_CLKEN BIT_32(14U) |
| 122 | #define VENDSPEC_PER_CLKEN BIT_32(13U) |
| 123 | #define VENDSPEC_AHB_CLKEN BIT_32(12U) |
| 124 | #define VENDSPEC_IPG_CLKEN BIT_32(11U) |
| 125 | #define VENDSPEC_AC12_CHKBUSY BIT_32(3U) |
| 126 | #define VENDSPEC_EXTDMA BIT_32(0U) |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 127 | #define VENDSPEC_INIT (VENDSPEC_RSRV1 | VENDSPEC_CARD_CLKEN | \ |
| 128 | VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \ |
| 129 | VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \ |
| 130 | VENDSPEC_EXTDMA) |
| 131 | |
Ghennadi Procopciuc | 376534a | 2025-04-04 09:52:42 +0300 | [diff] [blame^] | 132 | #define MMCBOOT 0x0c4U |
Jun Nie | 988e3b6 | 2018-06-28 16:38:02 +0800 | [diff] [blame] | 133 | |
| 134 | #define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set)) |
| 135 | #define mmio_clrbits32(addr, clear) mmio_write_32(addr, mmio_read_32(addr) & ~(clear)) |
| 136 | #define mmio_setbits32(addr, set) mmio_write_32(addr, mmio_read_32(addr) | (set)) |
| 137 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 138 | #endif /* IMX_USDHC_H */ |