Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * ZynqMP system level PM-API functions for pin control. |
| 9 | */ |
| 10 | |
| 11 | #ifndef _PM_API_IOCTL_H_ |
| 12 | #define _PM_API_IOCTL_H_ |
| 13 | |
| 14 | #include "pm_common.h" |
| 15 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 16 | //ioctl id |
| 17 | enum { |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 18 | IOCTL_GET_RPU_OPER_MODE, |
| 19 | IOCTL_SET_RPU_OPER_MODE, |
| 20 | IOCTL_RPU_BOOT_ADDR_CONFIG, |
| 21 | IOCTL_TCM_COMB_CONFIG, |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 22 | IOCTL_SET_TAPDELAY_BYPASS, |
| 23 | IOCTL_SET_SGMII_MODE, |
| 24 | IOCTL_SD_DLL_RESET, |
| 25 | IOCTL_SET_SD_TAPDELAY, |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 26 | /* Ioctl for clock driver */ |
| 27 | IOCTL_SET_PLL_FRAC_MODE, |
| 28 | IOCTL_GET_PLL_FRAC_MODE, |
| 29 | IOCTL_SET_PLL_FRAC_DATA, |
| 30 | IOCTL_GET_PLL_FRAC_DATA, |
Rajan Vaja | 393c0a2 | 2018-01-17 02:39:27 -0800 | [diff] [blame] | 31 | IOCTL_WRITE_GGS, |
| 32 | IOCTL_READ_GGS, |
| 33 | IOCTL_WRITE_PGGS, |
| 34 | IOCTL_READ_PGGS, |
Siva Durga Prasad Paladugu | ed1d5cb | 2018-09-04 17:03:25 +0530 | [diff] [blame] | 35 | /* IOCTL for ULPI reset */ |
| 36 | IOCTL_ULPI_RESET, |
Siva Durga Prasad Paladugu | ac8526f | 2018-09-04 17:12:51 +0530 | [diff] [blame^] | 37 | /* Set healthy bit value */ |
| 38 | IOCTL_SET_BOOT_HEALTH_STATUS, |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 39 | }; |
| 40 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 41 | //RPU operation mode |
| 42 | #define PM_RPU_MODE_LOCKSTEP 0U |
| 43 | #define PM_RPU_MODE_SPLIT 1U |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 44 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 45 | //RPU boot mem |
| 46 | #define PM_RPU_BOOTMEM_LOVEC 0U |
| 47 | #define PM_RPU_BOOTMEM_HIVEC 1U |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 48 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 49 | //RPU tcm mpde |
| 50 | #define PM_RPU_TCM_SPLIT 0U |
| 51 | #define PM_RPU_TCM_COMB 1U |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 52 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 53 | //tap delay signal type |
| 54 | #define PM_TAPDELAY_NAND_DQS_IN 0U |
| 55 | #define PM_TAPDELAY_NAND_DQS_OUT 1U |
| 56 | #define PM_TAPDELAY_QSPI 2U |
| 57 | #define PM_TAPDELAY_MAX 3U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 58 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 59 | //tap delay bypass |
| 60 | #define PM_TAPDELAY_BYPASS_DISABLE 0U |
| 61 | #define PM_TAPDELAY_BYPASS_ENABLE 1U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 62 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 63 | //sgmii mode |
| 64 | #define PM_SGMII_DISABLE 0U |
| 65 | #define PM_SGMII_ENABLE 1U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 66 | |
| 67 | enum tap_delay_type { |
| 68 | PM_TAPDELAY_INPUT, |
| 69 | PM_TAPDELAY_OUTPUT, |
| 70 | }; |
| 71 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 72 | //dll reset type |
| 73 | #define PM_DLL_RESET_ASSERT 0U |
| 74 | #define PM_DLL_RESET_RELEASE 1U |
| 75 | #define PM_DLL_RESET_PULSE 2U |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 76 | |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 77 | enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, |
| 78 | unsigned int ioctl_id, |
| 79 | unsigned int arg1, |
| 80 | unsigned int arg2, |
| 81 | unsigned int *value); |
| 82 | #endif /* _PM_API_IOCTL_H_ */ |