blob: 9623e25f85386e7d563b4e7000d0b5d49707edba [file] [log] [blame]
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05301/*
Varun Wadekar13e7dc42015-12-30 15:15:08 -08002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05303 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __MEMCTRLV2_H__
32#define __MEMCTRLV2_H__
33
34#include <mmio.h>
35#include <tegra_def.h>
36
37/*******************************************************************************
38 * StreamID to indicate no SMMU translations (requests to be steered on the
39 * SMMU bypass path)
40 ******************************************************************************/
41#define MC_STREAM_ID_MAX 0x7F
42
43/*******************************************************************************
44 * Stream ID Override Config registers
45 ******************************************************************************/
46#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0
47#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70
48#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8
49#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0
50#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0
51#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8
52#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138
53#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158
54#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188
55#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
56#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8
57#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
58#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8
59#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220
60#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230
61#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238
62#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250
63#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258
64#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260
65#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268
66#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0
67#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8
68#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0
69#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8
70#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300
71#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308
72#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310
73#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318
74#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320
75#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328
76#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330
77#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338
78#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360
79#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368
80#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390
81#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0
82#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8
83#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0
84#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8
85#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0
86#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8
87#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400
88#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408
89#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420
90#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428
91#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430
92#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438
93#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440
94#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448
95#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460
96#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468
97#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470
98#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478
99#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480
100#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488
101#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490
102#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498
103#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0
104#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8
105#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0
106#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8
107#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0
108#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8
109#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0
110#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8
111#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0
112#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8
113#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0
114#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8
115#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500
116#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508
117#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510
118#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518
119
120/*******************************************************************************
121 * Stream ID Security Config registers
122 ******************************************************************************/
123#define MC_STREAMID_SECURITY_CFG_PTCR 0x4
124#define MC_STREAMID_SECURITY_CFG_AFIR 0x74
125#define MC_STREAMID_SECURITY_CFG_HDAR 0xAC
126#define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4
127#define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4
128#define MC_STREAMID_SECURITY_CFG_SATAR 0xFC
129#define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC
130#define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C
131#define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C
132#define MC_STREAMID_SECURITY_CFG_AFIW 0x18C
133#define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC
134#define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC
135#define MC_STREAMID_SECURITY_CFG_ISPRA 0x224
136#define MC_STREAMID_SECURITY_CFG_ISPWA 0x234
137#define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C
138#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254
139#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C
140#define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264
141#define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C
142#define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4
143#define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC
144#define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4
145#define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC
146#define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304
147#define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C
148#define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314
149#define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C
150#define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324
151#define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C
152#define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334
153#define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C
154#define MC_STREAMID_SECURITY_CFG_VICSRD 0x364
155#define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C
156#define MC_STREAMID_SECURITY_CFG_VIW 0x394
157#define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4
158#define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC
159#define MC_STREAMID_SECURITY_CFG_APER 0x3D4
160#define MC_STREAMID_SECURITY_CFG_APEW 0x3DC
161#define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4
162#define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC
163#define MC_STREAMID_SECURITY_CFG_SESRD 0x404
164#define MC_STREAMID_SECURITY_CFG_SESWR 0x40C
165#define MC_STREAMID_SECURITY_CFG_ETRR 0x424
166#define MC_STREAMID_SECURITY_CFG_ETRW 0x42C
167#define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434
168#define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C
169#define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444
170#define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C
171#define MC_STREAMID_SECURITY_CFG_AXISR 0x464
172#define MC_STREAMID_SECURITY_CFG_AXISW 0x46C
173#define MC_STREAMID_SECURITY_CFG_EQOSR 0x474
174#define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C
175#define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484
176#define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C
177#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494
178#define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C
179#define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4
180#define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC
181#define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4
182#define MC_STREAMID_SECURITY_CFG_AONR 0x4BC
183#define MC_STREAMID_SECURITY_CFG_AONW 0x4C4
184#define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC
185#define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4
186#define MC_STREAMID_SECURITY_CFG_SCER 0x4DC
187#define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4
188#define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC
189#define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4
190#define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC
191#define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504
192#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C
193#define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514
194#define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C
195
196/*******************************************************************************
197 * Memory Controller SMMU Bypass config register
198 ******************************************************************************/
199#define MC_SMMU_BYPASS_CONFIG 0x1820
200#define MC_SMMU_BYPASS_CTRL_MASK 0x3
201#define MC_SMMU_BYPASS_CTRL_SHIFT 0
202#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT)
203#define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT)
204#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT)
205#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT)
206#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31)
207#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
208 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
209
210/*******************************************************************************
Varun Wadekarc9ac3e42016-02-17 15:07:49 -0800211 * Memory Controller transaction override config registers
212 ******************************************************************************/
213#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8
214#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0
215#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000
216#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490
217#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478
218#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8
219#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220
220#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328
221#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360
222#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8
223#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0
224#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460
225#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0
226#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330
227#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470
228#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8
229#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0
230#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318
231#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510
232#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8
233#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390
234#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308
235#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468
236#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260
237#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480
238#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8
239#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8
240#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8
241#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258
242#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438
243#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440
244#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8
245#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448
246#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0
247#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500
248#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0
249#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0
250#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420
251#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408
252#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0
253#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0
254#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430
255#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0
256#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0
257#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518
258#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250
259#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230
260#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400
261#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8
262#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8
263#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138
264#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320
265#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8
266#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8
267#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488
268#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8
269#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8
270#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428
271#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368
272#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158
273#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070
274#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338
275#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300
276#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508
277#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238
278#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498
279#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8
280#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310
281#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268
282#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0
283#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188
284#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
285
286/*******************************************************************************
287 * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
288 * MC_TXN_OVERRIDE_CONFIG_{module} registers
289 ******************************************************************************/
290#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0
291#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1
292#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2
293#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3
294#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3
295
296/*******************************************************************************
297 * Structure to hold the transaction override settings to use to override
298 * client inputs
299 ******************************************************************************/
300typedef struct mc_txn_override_cfg {
301 uint32_t offset;
302 uint8_t cgid_tag;
303} mc_txn_override_cfg_t;
304
305#define mc_make_txn_override_cfg(off, val) \
306 { \
307 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
308 .cgid_tag = MC_TXN_OVERRIDE_ ## val \
309 }
310
311/*******************************************************************************
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530312 * Structure to hold the Stream ID to use to override client inputs
313 ******************************************************************************/
314typedef struct mc_streamid_override_cfg {
315 uint32_t offset;
316 uint8_t stream_id;
317} mc_streamid_override_cfg_t;
318
319/*******************************************************************************
320 * Structure to hold the Stream ID Security Configuration settings
321 ******************************************************************************/
322typedef struct mc_streamid_security_cfg {
323 char *name;
324 uint32_t offset;
325 int override_enable;
326 int override_client_inputs;
327 int override_client_ns_flag;
328} mc_streamid_security_cfg_t;
329
330#define OVERRIDE_DISABLE 1
331#define OVERRIDE_ENABLE 0
332#define CLIENT_FLAG_SECURE 0
333#define CLIENT_FLAG_NON_SECURE 1
334#define CLIENT_INPUTS_OVERRIDE 1
335#define CLIENT_INPUTS_NO_OVERRIDE 0
336
337#define mc_make_sec_cfg(off, ns, ovrrd, access) \
338 { \
339 .name = # off, \
340 .offset = MC_STREAMID_SECURITY_CFG_ ## off, \
341 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \
342 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
343 .override_enable = OVERRIDE_ ## access \
344 }
345
346/*******************************************************************************
347 * TZDRAM carveout configuration registers
348 ******************************************************************************/
349#define MC_SECURITY_CFG0_0 0x70
350#define MC_SECURITY_CFG1_0 0x74
351#define MC_SECURITY_CFG3_0 0x9BC
352
353/*******************************************************************************
354 * Video Memory carveout configuration registers
355 ******************************************************************************/
356#define MC_VIDEO_PROTECT_BASE_HI 0x978
357#define MC_VIDEO_PROTECT_BASE_LO 0x648
358#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
359
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800360/*******************************************************************************
361 * TZRAM carveout configuration registers
362 ******************************************************************************/
363#define MC_TZRAM_BASE 0x1850
364#define MC_TZRAM_END 0x1854
365#define MC_TZRAM_HI_ADDR_BITS 0x1588
366 #define TZRAM_ADDR_HI_BITS_MASK 0x3
367 #define TZRAM_END_HI_BITS_SHIFT 8
368#define MC_TZRAM_REG_CTRL 0x185c
369 #define DISABLE_TZRAM_ACCESS 1
370
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530371static inline uint32_t tegra_mc_read_32(uint32_t off)
372{
373 return mmio_read_32(TEGRA_MC_BASE + off);
374}
375
376static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
377{
378 mmio_write_32(TEGRA_MC_BASE + off, val);
379}
380
381static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
382{
383 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off);
384}
385
386static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
387{
388 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
389}
390
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530391#endif /* __MEMCTRLV2_H__ */