Achin Gupta | 7671789 | 2014-05-09 11:42:56 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <gic_v2.h> |
| 35 | #include <tsp.h> |
| 36 | #include <platform.h> |
| 37 | |
| 38 | /******************************************************************************* |
| 39 | * This function updates the TSP statistics for FIQs handled synchronously i.e |
| 40 | * the ones that have been handed over by the TSPD. It also keeps count of the |
| 41 | * number of times control was passed back to the TSPD after handling an FIQ. |
| 42 | * In the future it will be possible that the TSPD hands over an FIQ to the TSP |
| 43 | * but does not expect it to return execution. This statistic will be useful to |
| 44 | * distinguish between these two models of synchronous FIQ handling. |
| 45 | * The 'elr_el3' parameter contains the address of the instruction in normal |
| 46 | * world where this FIQ was generated. |
| 47 | ******************************************************************************/ |
| 48 | void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3) |
| 49 | { |
| 50 | uint64_t mpidr = read_mpidr(); |
| 51 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 52 | |
| 53 | tsp_stats[linear_id].sync_fiq_count++; |
| 54 | if (type == TSP_HANDLE_FIQ_AND_RETURN) |
| 55 | tsp_stats[linear_id].sync_fiq_ret_count++; |
| 56 | |
| 57 | spin_lock(&console_lock); |
| 58 | printf("TSP: cpu 0x%x sync fiq request from 0x%llx \n\r", |
| 59 | mpidr, elr_el3); |
| 60 | INFO("cpu 0x%x: %d sync fiq requests, %d sync fiq returns\n", |
| 61 | mpidr, |
| 62 | tsp_stats[linear_id].sync_fiq_count, |
| 63 | tsp_stats[linear_id].sync_fiq_ret_count); |
| 64 | spin_unlock(&console_lock); |
| 65 | } |
| 66 | |
| 67 | /******************************************************************************* |
| 68 | * TSP FIQ handler called as a part of both synchronous and asynchronous |
| 69 | * handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1 |
| 70 | * FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC |
| 71 | * architecture version in v2.0 and the secure physical timer interrupt is the |
| 72 | * only S-EL1 interrupt that it needs to handle. |
| 73 | ******************************************************************************/ |
| 74 | int32_t tsp_fiq_handler() |
| 75 | { |
| 76 | uint64_t mpidr = read_mpidr(); |
| 77 | uint32_t linear_id = platform_get_core_pos(mpidr), id; |
| 78 | |
| 79 | /* |
| 80 | * Get the highest priority pending interrupt id and see if it is the |
| 81 | * secure physical generic timer interrupt in which case, handle it. |
| 82 | * Otherwise throw this interrupt at the EL3 firmware. |
| 83 | */ |
| 84 | id = ic_get_pending_interrupt_id(); |
| 85 | |
| 86 | /* TSP can only handle the secure physical timer interrupt */ |
| 87 | if (id != IRQ_SEC_PHY_TIMER) |
| 88 | return TSP_EL3_FIQ; |
| 89 | |
| 90 | /* |
| 91 | * Handle the interrupt. Also sanity check if it has been preempted by |
| 92 | * another secure interrupt through an assertion. |
| 93 | */ |
| 94 | id = ic_acknowledge_interrupt(); |
| 95 | assert(id == IRQ_SEC_PHY_TIMER); |
| 96 | tsp_generic_timer_handler(); |
| 97 | ic_end_of_interrupt(id); |
| 98 | |
| 99 | /* Update the statistics and print some messages */ |
| 100 | tsp_stats[linear_id].fiq_count++; |
| 101 | spin_lock(&console_lock); |
| 102 | printf("TSP: cpu 0x%x handled fiq %d \n\r", |
| 103 | mpidr, id); |
| 104 | INFO("cpu 0x%x: %d fiq requests \n", |
| 105 | mpidr, tsp_stats[linear_id].fiq_count); |
| 106 | spin_unlock(&console_lock); |
| 107 | |
| 108 | return 0; |
| 109 | } |