Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <assert.h> |
Varun Wadekar | 66ff012 | 2016-04-26 11:34:54 -0700 | [diff] [blame] | 32 | #include <bl_common.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 33 | #include <debug.h> |
| 34 | #include <memctrl_v2.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 35 | #include <platform_def.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 36 | #include <smmu.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 37 | #include <string.h> |
| 38 | #include <tegra_private.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 39 | |
| 40 | typedef struct smmu_regs { |
| 41 | uint32_t reg; |
| 42 | uint32_t val; |
| 43 | } smmu_regs_t; |
| 44 | |
| 45 | #define mc_make_sid_override_cfg(name) \ |
| 46 | { \ |
| 47 | .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \ |
| 48 | .val = 0x00000000, \ |
| 49 | } |
| 50 | |
| 51 | #define mc_make_sid_security_cfg(name) \ |
| 52 | { \ |
| 53 | .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_SECURITY_CFG_ ## name, \ |
| 54 | .val = 0x00000000, \ |
| 55 | } |
| 56 | |
| 57 | #define smmu_make_gnsr0_sec_cfg(name) \ |
| 58 | { \ |
| 59 | .reg = TEGRA_SMMU_BASE + SMMU_GNSR0_ ## name, \ |
| 60 | .val = 0x00000000, \ |
| 61 | } |
| 62 | |
| 63 | /* |
| 64 | * On ARM-SMMU, conditional offset to access secure aliases of non-secure registers |
| 65 | * is 0x400. So, add it to register address |
| 66 | */ |
| 67 | #define smmu_make_gnsr0_nsec_cfg(name) \ |
| 68 | { \ |
| 69 | .reg = TEGRA_SMMU_BASE + 0x400 + SMMU_GNSR0_ ## name, \ |
| 70 | .val = 0x00000000, \ |
| 71 | } |
| 72 | |
| 73 | #define smmu_make_gnsr0_smr_cfg(n) \ |
| 74 | { \ |
| 75 | .reg = TEGRA_SMMU_BASE + SMMU_GNSR0_SMR ## n, \ |
| 76 | .val = 0x00000000, \ |
| 77 | } |
| 78 | |
| 79 | #define smmu_make_gnsr0_s2cr_cfg(n) \ |
| 80 | { \ |
| 81 | .reg = TEGRA_SMMU_BASE + SMMU_GNSR0_S2CR ## n, \ |
| 82 | .val = 0x00000000, \ |
| 83 | } |
| 84 | |
| 85 | #define smmu_make_gnsr1_cbar_cfg(n) \ |
| 86 | { \ |
| 87 | .reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \ |
| 88 | .val = 0x00000000, \ |
| 89 | } |
| 90 | |
| 91 | #define smmu_make_gnsr1_cba2r_cfg(n) \ |
| 92 | { \ |
| 93 | .reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \ |
| 94 | .val = 0x00000000, \ |
| 95 | } |
| 96 | |
| 97 | #define make_smmu_cb_cfg(name, n) \ |
| 98 | { \ |
| 99 | .reg = TEGRA_SMMU_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \ |
| 100 | + SMMU_CBn_ ## name, \ |
| 101 | .val = 0x00000000, \ |
| 102 | } |
| 103 | |
| 104 | #define smmu_make_smrg_group(n) \ |
| 105 | smmu_make_gnsr0_smr_cfg(n), \ |
| 106 | smmu_make_gnsr0_s2cr_cfg(n), \ |
| 107 | smmu_make_gnsr1_cbar_cfg(n), \ |
| 108 | smmu_make_gnsr1_cba2r_cfg(n) /* don't put "," here. */ |
| 109 | |
| 110 | #define smmu_make_cb_group(n) \ |
| 111 | make_smmu_cb_cfg(SCTLR, n), \ |
| 112 | make_smmu_cb_cfg(TCR2, n), \ |
| 113 | make_smmu_cb_cfg(TTBR0_LO, n), \ |
| 114 | make_smmu_cb_cfg(TTBR0_HI, n), \ |
| 115 | make_smmu_cb_cfg(TCR, n), \ |
| 116 | make_smmu_cb_cfg(PRRR_MAIR0, n),\ |
| 117 | make_smmu_cb_cfg(FSR, n), \ |
| 118 | make_smmu_cb_cfg(FAR_LO, n), \ |
| 119 | make_smmu_cb_cfg(FAR_HI, n), \ |
| 120 | make_smmu_cb_cfg(FSYNR0, n) /* don't put "," here. */ |
| 121 | |
| 122 | #define smmu_bypass_cfg \ |
| 123 | { \ |
| 124 | .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ |
| 125 | .val = 0x00000000, \ |
| 126 | } |
| 127 | |
| 128 | #define _START_OF_TABLE_ \ |
| 129 | { \ |
| 130 | .reg = 0xCAFE05C7, \ |
| 131 | .val = 0x00000000, \ |
| 132 | } |
| 133 | |
| 134 | #define _END_OF_TABLE_ \ |
| 135 | { \ |
| 136 | .reg = 0xFFFFFFFF, \ |
| 137 | .val = 0xFFFFFFFF, \ |
| 138 | } |
| 139 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 140 | static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = { |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 141 | _START_OF_TABLE_, |
| 142 | mc_make_sid_security_cfg(SCEW), |
| 143 | mc_make_sid_security_cfg(AFIR), |
| 144 | mc_make_sid_security_cfg(NVDISPLAYR1), |
| 145 | mc_make_sid_security_cfg(XUSB_DEVR), |
| 146 | mc_make_sid_security_cfg(VICSRD1), |
| 147 | mc_make_sid_security_cfg(NVENCSWR), |
| 148 | mc_make_sid_security_cfg(TSECSRDB), |
| 149 | mc_make_sid_security_cfg(AXISW), |
| 150 | mc_make_sid_security_cfg(SDMMCWAB), |
| 151 | mc_make_sid_security_cfg(AONDMAW), |
| 152 | mc_make_sid_security_cfg(GPUSWR2), |
| 153 | mc_make_sid_security_cfg(SATAW), |
| 154 | mc_make_sid_security_cfg(UFSHCW), |
| 155 | mc_make_sid_security_cfg(AFIW), |
| 156 | mc_make_sid_security_cfg(SDMMCR), |
| 157 | mc_make_sid_security_cfg(SCEDMAW), |
| 158 | mc_make_sid_security_cfg(UFSHCR), |
| 159 | mc_make_sid_security_cfg(SDMMCWAA), |
| 160 | mc_make_sid_security_cfg(APEDMAW), |
| 161 | mc_make_sid_security_cfg(SESWR), |
| 162 | mc_make_sid_security_cfg(MPCORER), |
| 163 | mc_make_sid_security_cfg(PTCR), |
| 164 | mc_make_sid_security_cfg(BPMPW), |
| 165 | mc_make_sid_security_cfg(ETRW), |
| 166 | mc_make_sid_security_cfg(GPUSRD), |
| 167 | mc_make_sid_security_cfg(VICSWR), |
| 168 | mc_make_sid_security_cfg(SCEDMAR), |
| 169 | mc_make_sid_security_cfg(HDAW), |
| 170 | mc_make_sid_security_cfg(ISPWA), |
| 171 | mc_make_sid_security_cfg(EQOSW), |
| 172 | mc_make_sid_security_cfg(XUSB_HOSTW), |
| 173 | mc_make_sid_security_cfg(TSECSWR), |
| 174 | mc_make_sid_security_cfg(SDMMCRAA), |
| 175 | mc_make_sid_security_cfg(APER), |
| 176 | mc_make_sid_security_cfg(VIW), |
| 177 | mc_make_sid_security_cfg(APEW), |
| 178 | mc_make_sid_security_cfg(AXISR), |
| 179 | mc_make_sid_security_cfg(SDMMCW), |
| 180 | mc_make_sid_security_cfg(BPMPDMAW), |
| 181 | mc_make_sid_security_cfg(ISPRA), |
| 182 | mc_make_sid_security_cfg(NVDECSWR), |
| 183 | mc_make_sid_security_cfg(XUSB_DEVW), |
| 184 | mc_make_sid_security_cfg(NVDECSRD), |
| 185 | mc_make_sid_security_cfg(MPCOREW), |
| 186 | mc_make_sid_security_cfg(NVDISPLAYR), |
| 187 | mc_make_sid_security_cfg(BPMPDMAR), |
| 188 | mc_make_sid_security_cfg(NVJPGSWR), |
| 189 | mc_make_sid_security_cfg(NVDECSRD1), |
| 190 | mc_make_sid_security_cfg(TSECSRD), |
| 191 | mc_make_sid_security_cfg(NVJPGSRD), |
| 192 | mc_make_sid_security_cfg(SDMMCWA), |
| 193 | mc_make_sid_security_cfg(SCER), |
| 194 | mc_make_sid_security_cfg(XUSB_HOSTR), |
| 195 | mc_make_sid_security_cfg(VICSRD), |
| 196 | mc_make_sid_security_cfg(AONDMAR), |
| 197 | mc_make_sid_security_cfg(AONW), |
| 198 | mc_make_sid_security_cfg(SDMMCRA), |
| 199 | mc_make_sid_security_cfg(HOST1XDMAR), |
| 200 | mc_make_sid_security_cfg(EQOSR), |
| 201 | mc_make_sid_security_cfg(SATAR), |
| 202 | mc_make_sid_security_cfg(BPMPR), |
| 203 | mc_make_sid_security_cfg(HDAR), |
| 204 | mc_make_sid_security_cfg(SDMMCRAB), |
| 205 | mc_make_sid_security_cfg(ETRR), |
| 206 | mc_make_sid_security_cfg(AONR), |
| 207 | mc_make_sid_security_cfg(APEDMAR), |
| 208 | mc_make_sid_security_cfg(SESRD), |
| 209 | mc_make_sid_security_cfg(NVENCSRD), |
| 210 | mc_make_sid_security_cfg(GPUSWR), |
| 211 | mc_make_sid_security_cfg(TSECSWRB), |
| 212 | mc_make_sid_security_cfg(ISPWB), |
| 213 | mc_make_sid_security_cfg(GPUSRD2), |
| 214 | mc_make_sid_override_cfg(APER), |
| 215 | mc_make_sid_override_cfg(VICSRD), |
| 216 | mc_make_sid_override_cfg(NVENCSRD), |
| 217 | mc_make_sid_override_cfg(NVJPGSWR), |
| 218 | mc_make_sid_override_cfg(AONW), |
| 219 | mc_make_sid_override_cfg(BPMPR), |
| 220 | mc_make_sid_override_cfg(BPMPW), |
| 221 | mc_make_sid_override_cfg(HDAW), |
| 222 | mc_make_sid_override_cfg(NVDISPLAYR1), |
| 223 | mc_make_sid_override_cfg(APEDMAR), |
| 224 | mc_make_sid_override_cfg(AFIR), |
| 225 | mc_make_sid_override_cfg(AXISR), |
| 226 | mc_make_sid_override_cfg(VICSRD1), |
| 227 | mc_make_sid_override_cfg(TSECSRD), |
| 228 | mc_make_sid_override_cfg(BPMPDMAW), |
| 229 | mc_make_sid_override_cfg(MPCOREW), |
| 230 | mc_make_sid_override_cfg(XUSB_HOSTR), |
| 231 | mc_make_sid_override_cfg(GPUSWR), |
| 232 | mc_make_sid_override_cfg(XUSB_DEVR), |
| 233 | mc_make_sid_override_cfg(UFSHCW), |
| 234 | mc_make_sid_override_cfg(XUSB_HOSTW), |
| 235 | mc_make_sid_override_cfg(SDMMCWAB), |
| 236 | mc_make_sid_override_cfg(SATAW), |
| 237 | mc_make_sid_override_cfg(SCEDMAR), |
| 238 | mc_make_sid_override_cfg(HOST1XDMAR), |
| 239 | mc_make_sid_override_cfg(SDMMCWA), |
| 240 | mc_make_sid_override_cfg(APEDMAW), |
| 241 | mc_make_sid_override_cfg(SESWR), |
| 242 | mc_make_sid_override_cfg(AXISW), |
| 243 | mc_make_sid_override_cfg(AONDMAW), |
| 244 | mc_make_sid_override_cfg(TSECSWRB), |
| 245 | mc_make_sid_override_cfg(MPCORER), |
| 246 | mc_make_sid_override_cfg(ISPWB), |
| 247 | mc_make_sid_override_cfg(AONR), |
| 248 | mc_make_sid_override_cfg(BPMPDMAR), |
| 249 | mc_make_sid_override_cfg(HDAR), |
| 250 | mc_make_sid_override_cfg(SDMMCRA), |
| 251 | mc_make_sid_override_cfg(ETRW), |
| 252 | mc_make_sid_override_cfg(GPUSWR2), |
| 253 | mc_make_sid_override_cfg(EQOSR), |
| 254 | mc_make_sid_override_cfg(TSECSWR), |
| 255 | mc_make_sid_override_cfg(ETRR), |
| 256 | mc_make_sid_override_cfg(NVDECSRD), |
| 257 | mc_make_sid_override_cfg(TSECSRDB), |
| 258 | mc_make_sid_override_cfg(SDMMCRAA), |
| 259 | mc_make_sid_override_cfg(NVDECSRD1), |
| 260 | mc_make_sid_override_cfg(SDMMCR), |
| 261 | mc_make_sid_override_cfg(NVJPGSRD), |
| 262 | mc_make_sid_override_cfg(SCEDMAW), |
| 263 | mc_make_sid_override_cfg(SDMMCWAA), |
| 264 | mc_make_sid_override_cfg(APEW), |
| 265 | mc_make_sid_override_cfg(AONDMAR), |
| 266 | mc_make_sid_override_cfg(PTCR), |
| 267 | mc_make_sid_override_cfg(SCER), |
| 268 | mc_make_sid_override_cfg(ISPRA), |
| 269 | mc_make_sid_override_cfg(ISPWA), |
| 270 | mc_make_sid_override_cfg(VICSWR), |
| 271 | mc_make_sid_override_cfg(SESRD), |
| 272 | mc_make_sid_override_cfg(SDMMCW), |
| 273 | mc_make_sid_override_cfg(SDMMCRAB), |
| 274 | mc_make_sid_override_cfg(EQOSW), |
| 275 | mc_make_sid_override_cfg(GPUSRD2), |
| 276 | mc_make_sid_override_cfg(SCEW), |
| 277 | mc_make_sid_override_cfg(GPUSRD), |
| 278 | mc_make_sid_override_cfg(NVDECSWR), |
| 279 | mc_make_sid_override_cfg(XUSB_DEVW), |
| 280 | mc_make_sid_override_cfg(SATAR), |
| 281 | mc_make_sid_override_cfg(NVDISPLAYR), |
| 282 | mc_make_sid_override_cfg(VIW), |
| 283 | mc_make_sid_override_cfg(UFSHCR), |
| 284 | mc_make_sid_override_cfg(NVENCSWR), |
| 285 | mc_make_sid_override_cfg(AFIW), |
| 286 | smmu_make_gnsr0_nsec_cfg(CR0), |
| 287 | smmu_make_gnsr0_sec_cfg(IDR0), |
| 288 | smmu_make_gnsr0_sec_cfg(IDR1), |
| 289 | smmu_make_gnsr0_sec_cfg(IDR2), |
| 290 | smmu_make_gnsr0_nsec_cfg(GFSR), |
| 291 | smmu_make_gnsr0_nsec_cfg(GFSYNR0), |
| 292 | smmu_make_gnsr0_nsec_cfg(GFSYNR1), |
| 293 | smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), |
| 294 | smmu_make_gnsr0_nsec_cfg(PIDR2), |
| 295 | smmu_make_smrg_group(0), |
| 296 | smmu_make_smrg_group(1), |
| 297 | smmu_make_smrg_group(2), |
| 298 | smmu_make_smrg_group(3), |
| 299 | smmu_make_smrg_group(4), |
| 300 | smmu_make_smrg_group(5), |
| 301 | smmu_make_smrg_group(6), |
| 302 | smmu_make_smrg_group(7), |
| 303 | smmu_make_smrg_group(8), |
| 304 | smmu_make_smrg_group(9), |
| 305 | smmu_make_smrg_group(10), |
| 306 | smmu_make_smrg_group(11), |
| 307 | smmu_make_smrg_group(12), |
| 308 | smmu_make_smrg_group(13), |
| 309 | smmu_make_smrg_group(14), |
| 310 | smmu_make_smrg_group(15), |
| 311 | smmu_make_smrg_group(16), |
| 312 | smmu_make_smrg_group(17), |
| 313 | smmu_make_smrg_group(18), |
| 314 | smmu_make_smrg_group(19), |
| 315 | smmu_make_smrg_group(20), |
| 316 | smmu_make_smrg_group(21), |
| 317 | smmu_make_smrg_group(22), |
| 318 | smmu_make_smrg_group(23), |
| 319 | smmu_make_smrg_group(24), |
| 320 | smmu_make_smrg_group(25), |
| 321 | smmu_make_smrg_group(26), |
| 322 | smmu_make_smrg_group(27), |
| 323 | smmu_make_smrg_group(28), |
| 324 | smmu_make_smrg_group(29), |
| 325 | smmu_make_smrg_group(30), |
| 326 | smmu_make_smrg_group(31), |
| 327 | smmu_make_smrg_group(32), |
| 328 | smmu_make_smrg_group(33), |
| 329 | smmu_make_smrg_group(34), |
| 330 | smmu_make_smrg_group(35), |
| 331 | smmu_make_smrg_group(36), |
| 332 | smmu_make_smrg_group(37), |
| 333 | smmu_make_smrg_group(38), |
| 334 | smmu_make_smrg_group(39), |
| 335 | smmu_make_smrg_group(40), |
| 336 | smmu_make_smrg_group(41), |
| 337 | smmu_make_smrg_group(42), |
| 338 | smmu_make_smrg_group(43), |
| 339 | smmu_make_smrg_group(44), |
| 340 | smmu_make_smrg_group(45), |
| 341 | smmu_make_smrg_group(46), |
| 342 | smmu_make_smrg_group(47), |
| 343 | smmu_make_smrg_group(48), |
| 344 | smmu_make_smrg_group(49), |
| 345 | smmu_make_smrg_group(50), |
| 346 | smmu_make_smrg_group(51), |
| 347 | smmu_make_smrg_group(52), |
| 348 | smmu_make_smrg_group(53), |
| 349 | smmu_make_smrg_group(54), |
| 350 | smmu_make_smrg_group(55), |
| 351 | smmu_make_smrg_group(56), |
| 352 | smmu_make_smrg_group(57), |
| 353 | smmu_make_smrg_group(58), |
| 354 | smmu_make_smrg_group(59), |
| 355 | smmu_make_smrg_group(60), |
| 356 | smmu_make_smrg_group(61), |
| 357 | smmu_make_smrg_group(62), |
| 358 | smmu_make_smrg_group(63), |
| 359 | smmu_make_cb_group(0), |
| 360 | smmu_make_cb_group(1), |
| 361 | smmu_make_cb_group(2), |
| 362 | smmu_make_cb_group(3), |
| 363 | smmu_make_cb_group(4), |
| 364 | smmu_make_cb_group(5), |
| 365 | smmu_make_cb_group(6), |
| 366 | smmu_make_cb_group(7), |
| 367 | smmu_make_cb_group(8), |
| 368 | smmu_make_cb_group(9), |
| 369 | smmu_make_cb_group(10), |
| 370 | smmu_make_cb_group(11), |
| 371 | smmu_make_cb_group(12), |
| 372 | smmu_make_cb_group(13), |
| 373 | smmu_make_cb_group(14), |
| 374 | smmu_make_cb_group(15), |
| 375 | smmu_make_cb_group(16), |
| 376 | smmu_make_cb_group(17), |
| 377 | smmu_make_cb_group(18), |
| 378 | smmu_make_cb_group(19), |
| 379 | smmu_make_cb_group(20), |
| 380 | smmu_make_cb_group(21), |
| 381 | smmu_make_cb_group(22), |
| 382 | smmu_make_cb_group(23), |
| 383 | smmu_make_cb_group(24), |
| 384 | smmu_make_cb_group(25), |
| 385 | smmu_make_cb_group(26), |
| 386 | smmu_make_cb_group(27), |
| 387 | smmu_make_cb_group(28), |
| 388 | smmu_make_cb_group(29), |
| 389 | smmu_make_cb_group(30), |
| 390 | smmu_make_cb_group(31), |
| 391 | smmu_make_cb_group(32), |
| 392 | smmu_make_cb_group(33), |
| 393 | smmu_make_cb_group(34), |
| 394 | smmu_make_cb_group(35), |
| 395 | smmu_make_cb_group(36), |
| 396 | smmu_make_cb_group(37), |
| 397 | smmu_make_cb_group(38), |
| 398 | smmu_make_cb_group(39), |
| 399 | smmu_make_cb_group(40), |
| 400 | smmu_make_cb_group(41), |
| 401 | smmu_make_cb_group(42), |
| 402 | smmu_make_cb_group(43), |
| 403 | smmu_make_cb_group(44), |
| 404 | smmu_make_cb_group(45), |
| 405 | smmu_make_cb_group(46), |
| 406 | smmu_make_cb_group(47), |
| 407 | smmu_make_cb_group(48), |
| 408 | smmu_make_cb_group(49), |
| 409 | smmu_make_cb_group(50), |
| 410 | smmu_make_cb_group(51), |
| 411 | smmu_make_cb_group(52), |
| 412 | smmu_make_cb_group(53), |
| 413 | smmu_make_cb_group(54), |
| 414 | smmu_make_cb_group(55), |
| 415 | smmu_make_cb_group(56), |
| 416 | smmu_make_cb_group(57), |
| 417 | smmu_make_cb_group(58), |
| 418 | smmu_make_cb_group(59), |
| 419 | smmu_make_cb_group(60), |
| 420 | smmu_make_cb_group(61), |
| 421 | smmu_make_cb_group(62), |
| 422 | smmu_make_cb_group(63), |
| 423 | smmu_bypass_cfg, /* TBU settings */ |
| 424 | _END_OF_TABLE_, |
| 425 | }; |
| 426 | |
| 427 | /* |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 428 | * Save SMMU settings before "System Suspend" to TZDRAM |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 429 | */ |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 430 | void tegra_smmu_save_context(uint64_t smmu_ctx_addr) |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 431 | { |
| 432 | uint32_t i; |
| 433 | #if DEBUG |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 434 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 435 | uint64_t tzdram_base = params_from_bl2->tzdram_base; |
| 436 | uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 437 | uint32_t reg_id1, pgshift, cb_size; |
| 438 | |
| 439 | /* sanity check SMMU settings c*/ |
| 440 | reg_id1 = mmio_read_32((TEGRA_SMMU_BASE + SMMU_GNSR0_IDR1)); |
| 441 | pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12; |
| 442 | cb_size = (2 << pgshift) * \ |
| 443 | (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1)); |
| 444 | |
| 445 | assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE))); |
| 446 | #endif |
| 447 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 448 | assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end)); |
| 449 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 450 | /* index of _END_OF_TABLE_ */ |
| 451 | smmu_ctx_regs[0].val = ARRAY_SIZE(smmu_ctx_regs) - 1; |
| 452 | |
| 453 | /* save SMMU register values */ |
| 454 | for (i = 1; i < ARRAY_SIZE(smmu_ctx_regs) - 1; i++) |
| 455 | smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg); |
| 456 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 457 | /* Save SMMU config settings */ |
| 458 | memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs, |
| 459 | sizeof(smmu_ctx_regs)); |
| 460 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 461 | /* save the SMMU table address */ |
| 462 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 463 | (uint32_t)smmu_ctx_addr); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 464 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 465 | (uint32_t)(smmu_ctx_addr >> 32)); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 466 | } |
| 467 | |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 468 | #define SMMU_NUM_CONTEXTS 64 |
| 469 | #define SMMU_CONTEXT_BANK_MAX_IDX 64 |
| 470 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 471 | /* |
| 472 | * Init SMMU during boot or "System Suspend" exit |
| 473 | */ |
| 474 | void tegra_smmu_init(void) |
| 475 | { |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 476 | uint32_t val, i, ctx_base; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 477 | |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 478 | /* Program the SMMU pagesize and reset CACHE_LOCK bit */ |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 479 | val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR); |
| 480 | val |= SMMU_GSR0_PGSIZE_64K; |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 481 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 482 | tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val); |
| 483 | |
| 484 | /* reset CACHE LOCK bit for NS Aux. Config. Register */ |
| 485 | val = tegra_smmu_read_32(SMMU_GNSR_ACR); |
| 486 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 487 | tegra_smmu_write_32(SMMU_GNSR_ACR, val); |
| 488 | |
| 489 | /* disable TCU prefetch for all contexts */ |
| 490 | ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) + SMMU_CBn_ACTLR; |
| 491 | for (i = 0; i < SMMU_CONTEXT_BANK_MAX_IDX; i++) { |
| 492 | val = tegra_smmu_read_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i)); |
| 493 | val &= ~SMMU_CBn_ACTLR_CPRE_BIT; |
| 494 | tegra_smmu_write_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i), val); |
| 495 | } |
| 496 | |
| 497 | /* set CACHE LOCK bit for NS Aux. Config. Register */ |
| 498 | val = tegra_smmu_read_32(SMMU_GNSR_ACR); |
| 499 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 500 | tegra_smmu_write_32(SMMU_GNSR_ACR, val); |
| 501 | |
| 502 | /* set CACHE LOCK bit for S Aux. Config. Register */ |
| 503 | val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR); |
| 504 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 505 | tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val); |
| 506 | } |