| Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | #ifndef ARM_PAS_DEF_H |
| 7 | #define ARM_PAS_DEF_H |
| 8 | |
| 9 | #include <plat/arm/common/arm_def.h> |
| 10 | |
| 11 | /***************************************************************************** |
| 12 | * PAS regions used to initialize the Granule Protection Table (GPT) |
| 13 | ****************************************************************************/ |
| 14 | |
| 15 | /* |
| 16 | * The PA space is initially mapped in the GPT as follows: |
| 17 | * |
| 18 | * ============================================================================ |
| 19 | * Base Addr| Size |L? GPT|PAS |Content |Comment |
| 20 | * ============================================================================ |
| 21 | * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping |
| 22 | * | | | |TSRAM (EL3 data) | |
| 23 | * | | | |IO (incl.UARTs & GIC) | |
| 24 | * ---------------------------------------------------------------------------- |
| 25 | * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping |
| 26 | * ---------------------------------------------------------------------------- |
| 27 | * 2GB | 1GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip |
| 28 | * ---------------------------------------------------------------------------- |
| 29 | * 3GB |1GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip |
| 30 | * ---------------------------------------------------------------------------- |
| 31 | * 4GB-64MB |64MB-32MB | | | | |
| 32 | * | -4MB |L1 GPT|SECURE|DRAM TZC |Use T.Descrip |
| 33 | * ---------------------------------------------------------------------------- |
| 34 | * 4GB-32MB | | | | | |
| 35 | * -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip |
| 36 | * ---------------------------------------------------------------------------- |
| 37 | * 4GB-3MB | | | | | |
| 38 | * -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip |
| 39 | * ---------------------------------------------------------------------------- |
| 40 | * 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping |
| 41 | * ============================================================================ |
| 42 | * |
| 43 | * - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section. |
| 44 | * - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area). |
| 45 | * - The first 1GB region has GPI_ANY and, therefore, is not protected by |
| 46 | * the GPT. |
| 47 | * - The DRAM TZC area is split into three regions: the L1 GPT region and |
| 48 | * 3MB of region below that are defined as GPI_ROOT, 32MB Realm region |
| 49 | * below that is defined as GPI_REALM and the rest of it is defined as |
| 50 | * GPI_SECURE. |
| 51 | */ |
| 52 | |
| 53 | /* TODO: This might not be the best way to map the PAS */ |
| 54 | |
| 55 | /* Device memory 0 to 2GB */ |
| 56 | #define ARM_PAS_1_BASE (U(0)) |
| 57 | #define ARM_PAS_1_SIZE ((ULL(1)<<31)) /* 2GB */ |
| 58 | |
| 59 | /* NS memory 2GB to (end - 64MB) */ |
| 60 | #define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) |
| 61 | #define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) |
| 62 | |
| 63 | /* Secure TZC region */ |
| 64 | #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) |
| 65 | #define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) |
| 66 | |
| 67 | #define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \ |
| 68 | ARM_PAS_1_SIZE, \ |
| 69 | GPI_ANY) |
| 70 | #define ARM_PAS_KERNEL MAP_GPT_REGION_TBL(ARM_PAS_2_BASE, \ |
| 71 | ARM_PAS_2_SIZE, \ |
| 72 | GPI_NS) |
| 73 | |
| 74 | #define ARM_PAS_TZC MAP_GPT_REGION_TBL(ARM_PAS_3_BASE, \ |
| 75 | ARM_PAS_3_SIZE, \ |
| 76 | GPI_SECURE) |
| 77 | |
| 78 | #define ARM_PAS_REALM MAP_GPT_REGION_TBL(ARM_REALM_BASE, \ |
| 79 | ARM_REALM_SIZE, \ |
| 80 | GPI_REALM) |
| 81 | |
| 82 | #define ARM_PAS_EL3_DRAM MAP_GPT_REGION_TBL(ARM_EL3_TZC_DRAM1_BASE, \ |
| 83 | ARM_EL3_TZC_DRAM1_SIZE, \ |
| 84 | GPI_ROOT) |
| 85 | |
| 86 | #define ARM_PAS_GPTS MAP_GPT_REGION_TBL(ARM_L1_GPT_ADDR_BASE, \ |
| 87 | ARM_L1_GPT_SIZE, \ |
| 88 | GPI_ROOT) |
| 89 | |
| Zelalem Aweke | 5085abd | 2021-07-13 17:19:54 -0500 | [diff] [blame] | 90 | /* GPT Configuration options */ |
| 91 | #define PLATFORM_PGS GPCCR_PGS_4K |
| 92 | #define PLATFORM_PPS GPCCR_PPS_4GB |
| 93 | #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS |
| 94 | |
| Zelalem Aweke | c43c563 | 2021-07-12 23:41:05 -0500 | [diff] [blame] | 95 | #endif /* ARM_PAS_DEF_H */ |