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git01.mediatek.com / filogic / atf / ce56e4654af6ca7a89e5ba7d4af5084b0234ffac / . / drivers / staging / renesas / rcar / qos / D3 / qos_init_d3.c
blob: b115d633b561b952d3d7d296ead7b8b94deac00a [file] [log] [blame]
Marek Vasut6f39e3c2018-06-14 06:26:45 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h>
8#include <common/debug.h>
9#include "qos_init_d3.h"
10
11
12#define RCAR_QOS_VERSION "rev.0.05"
13
14#define RCAR_QOS_NONE (3U)
15#define RCAR_QOS_TYPE_DEFAULT (0U)
16
17#define RCAR_DRAM_SPLIT_LINEAR (0U)
18#define RCAR_DRAM_SPLIT_4CH (1U)
19#define RCAR_DRAM_SPLIT_2CH (2U)
20#define RCAR_DRAM_SPLIT_AUTO (3U)
21
22#define RST_BASE (0xE6160000U)
23#define RST_MODEMR (RST_BASE + 0x0060U)
24
25#define DBSC_BASE (0xE6790000U)
26#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
27#define DBSC_AXARB (DBSC_BASE + 0x0800U)
28#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
29#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
30#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
31#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
32#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
33#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
34#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
35#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
36#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
37#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
38#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
39#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
40#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
41#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
42#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
43#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
44#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
45#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
46#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
47#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
48#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
49#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
50#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
51#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
52#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
53#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
54#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
55#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
56#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
57#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
58#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
59#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
60#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
61#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
62#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
63#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
64#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
65#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
66#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
67#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
68#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
69#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
70#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
71#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
72#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
73#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
74#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
75#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
76#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
77#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
78#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
79#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
80#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
81#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
82#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
83#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
84#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
85#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
86#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
87#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
88#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
89#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
90#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
91#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
92#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
93#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
94#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
95#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
96#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
97#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
98#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
99#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
100#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
101#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
102#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
103
104#define AXI_BASE (0xE6784000U)
105#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
106#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
107
108#define MSTAT_BASE (0xE67E0000U)
109#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
110#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
111#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
112#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
113#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
114#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
115#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
116
117#define RALLOC_BASE (0xE67F0000U)
118#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
119#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
120#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
121#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
122#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
123#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
124#define RALLOC_EC (RALLOC_BASE + 0x003CU)
125#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
126#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
127#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
128#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
129#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U)
130#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
131#define RALLOC_TICKDUPL (RALLOC_BASE + 0x0088U)
132
133#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
134
135static inline void io_write_32(uintptr_t addr, uint32_t value)
136{
137 *(volatile uint32_t*)addr = value;
138}
139
140static inline void io_write_64(uintptr_t addr, uint64_t value)
141{
142 *(volatile uint64_t*)addr = value;
143}
144
145typedef struct {
146 uintptr_t addr;
147 uint64_t value;
148} mstat_slot_t;
149
150
151#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
152static const mstat_slot_t mstat_fix[] = {
153 {0x0000U, 0x0000000000000000U},
154 {0x0008U, 0x0000000000000000U},
155 {0x0010U, 0x0000000000000000U},
156 {0x0018U, 0x0000000000000000U},
157 {0x0020U, 0x0000000000000000U},
158 {0x0028U, 0x0000000000000000U},
159 {0x0030U, 0x001004340000FFFFU},
160 {0x0038U, 0x001004140000FFFFU},
161 {0x0040U, 0x0000000000000000U},
162 {0x0048U, 0x0000000000000000U},
163 {0x0050U, 0x0000000000000000U},
164 {0x0058U, 0x00140B030000FFFFU},
165 {0x0060U, 0x001408610000FFFFU},
166 {0x0068U, 0x0000000000000000U},
167 {0x0070U, 0x0000000000000000U},
168 {0x0078U, 0x0000000000000000U},
169 {0x0080U, 0x0000000000000000U},
170 {0x0088U, 0x001410620000FFFFU},
171 {0x0090U, 0x0000000000000000U},
172 {0x0098U, 0x0000000000000000U},
173 {0x00A0U, 0x000C041C0000FFFFU},
174 {0x00A8U, 0x000C04090000FFFFU},
175 {0x00B0U, 0x000C04110000FFFFU},
176 {0x00B8U, 0x0000000000000000U},
177 {0x00C0U, 0x000C041C0000FFFFU},
178 {0x00C8U, 0x000C04090000FFFFU},
179 {0x00D0U, 0x000C04110000FFFFU},
180 {0x00D8U, 0x0000000000000000U},
181 {0x00E0U, 0x0000000000000000U},
182 {0x00E8U, 0x0000000000000000U},
183 {0x00F0U, 0x001018570000FFFFU},
184 {0x00F8U, 0x0000000000000000U},
185 {0x0100U, 0x0000000000000000U},
186 {0x0108U, 0x0000000000000000U},
187 {0x0110U, 0x001008570000FFFFU},
188 {0x0118U, 0x0000000000000000U},
189 {0x0120U, 0x0000000000000000U},
190 {0x0128U, 0x0000000000000000U},
191 {0x0130U, 0x0000000000000000U},
192 {0x0138U, 0x0000000000000000U},
193 {0x0140U, 0x0000000000000000U},
194 {0x0148U, 0x0000000000000000U},
195 {0x0150U, 0x001008520000FFFFU},
196 {0x0158U, 0x0000000000000000U},
197 {0x0160U, 0x0000000000000000U},
198 {0x0168U, 0x0000000000000000U},
199 {0x0170U, 0x0000000000000000U},
200 {0x0178U, 0x0000000000000000U},
201 {0x0180U, 0x0000000000000000U},
202 {0x0188U, 0x0000000000000000U},
203 {0x0190U, 0x00100CA30000FFFFU},
204 {0x0198U, 0x0000000000000000U},
205 {0x01A0U, 0x0000000000000000U},
206 {0x01A8U, 0x0000000000000000U},
207 {0x01B0U, 0x0000000000000000U},
208 {0x01B8U, 0x0000000000000000U},
209 {0x01C0U, 0x0000000000000000U},
210 {0x01C8U, 0x0000000000000000U},
211 {0x01D0U, 0x0000000000000000U},
212 {0x01D8U, 0x0000000000000000U},
213 {0x01E0U, 0x0000000000000000U},
214 {0x01E8U, 0x000C04020000FFFFU},
215 {0x01F0U, 0x0000000000000000U},
216 {0x01F8U, 0x0000000000000000U},
217 {0x0200U, 0x0000000000000000U},
218 {0x0208U, 0x000C04090000FFFFU},
219 {0x0210U, 0x0000000000000000U},
220 {0x0218U, 0x0000000000000000U},
221 {0x0220U, 0x0000000000000000U},
222 {0x0228U, 0x0000000000000000U},
223 {0x0230U, 0x0000000000000000U},
224 {0x0238U, 0x0000000000000000U},
225 {0x0240U, 0x0000000000000000U},
226 {0x0248U, 0x0000000000000000U},
227 {0x0250U, 0x0000000000000000U},
228 {0x0258U, 0x0000000000000000U},
229 {0x0260U, 0x0000000000000000U},
230 {0x0268U, 0x001410040000FFFFU},
231 {0x0270U, 0x001404020000FFFFU},
232 {0x0278U, 0x0000000000000000U},
233 {0x0280U, 0x0000000000000000U},
234 {0x0288U, 0x0000000000000000U},
235 {0x0290U, 0x001410040000FFFFU},
236 {0x0298U, 0x001404020000FFFFU},
237 {0x02A0U, 0x000C04050000FFFFU},
238 {0x02A8U, 0x000C04050000FFFFU},
239 {0x02B0U, 0x0000000000000000U},
240 {0x02B8U, 0x0000000000000000U},
241 {0x02C0U, 0x0000000000000000U},
242 {0x02C8U, 0x0000000000000000U},
243 {0x02D0U, 0x000C04050000FFFFU},
244 {0x02D8U, 0x000C04050000FFFFU},
245 {0x02E0U, 0x0000000000000000U},
246 {0x02E8U, 0x0000000000000000U},
247 {0x02F0U, 0x0000000000000000U},
248 {0x02F8U, 0x0000000000000000U},
249 {0x0300U, 0x0000000000000000U},
250 {0x0308U, 0x0000000000000000U},
251 {0x0310U, 0x0000000000000000U},
252 {0x0318U, 0x0000000000000000U},
253 {0x0320U, 0x0000000000000000U},
254 {0x0328U, 0x0000000000000000U},
255 {0x0330U, 0x0000000000000000U},
256 {0x0338U, 0x0000000000000000U},
257 {0x0340U, 0x0000000000000000U},
258 {0x0348U, 0x0000000000000000U},
259 {0x0350U, 0x0000000000000000U},
260 {0x0358U, 0x0000000000000000U},
261 {0x0360U, 0x0000000000000000U},
262 {0x0368U, 0x0000000000000000U},
263 {0x0370U, 0x000C04020000FFFFU},
264 {0x0378U, 0x000C04020000FFFFU},
265 {0x0380U, 0x000C04090000FFFFU},
266 {0x0388U, 0x000C04090000FFFFU},
267 {0x0390U, 0x0000000000000000U},
268};
269
270static const mstat_slot_t mstat_be[] = {
271 {0x0000U, 0x0000000000000000U},
272 {0x0008U, 0x0000000000000000U},
273 {0x0010U, 0x0000000000000000U},
274 {0x0018U, 0x0000000000000000U},
275 {0x0020U, 0x0000000000000000U},
276 {0x0028U, 0x0000000000000000U},
277 {0x0030U, 0x0000000000000000U},
278 {0x0038U, 0x0000000000000000U},
279 {0x0040U, 0x0000000000000000U},
280 {0x0048U, 0x0000000000000000U},
281 {0x0050U, 0x0000000000000000U},
282 {0x0058U, 0x0000000000000000U},
283 {0x0060U, 0x0000000000000000U},
284 {0x0068U, 0x0000000000000000U},
285 {0x0070U, 0x0000000000000000U},
286 {0x0078U, 0x0000000000000000U},
287 {0x0080U, 0x0000000000000000U},
288 {0x0088U, 0x0000000000000000U},
289 {0x0090U, 0x0000000000000000U},
290 {0x0098U, 0x0000000000000000U},
291 {0x00A0U, 0x0000000000000000U},
292 {0x00A8U, 0x0000000000000000U},
293 {0x00B0U, 0x0000000000000000U},
294 {0x00B8U, 0x0000000000000000U},
295 {0x00C0U, 0x0000000000000000U},
296 {0x00C8U, 0x0000000000000000U},
297 {0x00D0U, 0x0000000000000000U},
298 {0x00D8U, 0x0000000000000000U},
299 {0x00E0U, 0x0000000000000000U},
300 {0x00E8U, 0x0000000000000000U},
301 {0x00F0U, 0x0000000000000000U},
302 {0x00F8U, 0x0000000000000000U},
303 {0x0100U, 0x0000000000000000U},
304 {0x0108U, 0x0000000000000000U},
305 {0x0110U, 0x0000000000000000U},
306 {0x0118U, 0x0000000000000000U},
307 {0x0120U, 0x0000000000000000U},
308 {0x0128U, 0x0000000000000000U},
309 {0x0130U, 0x0000000000000000U},
310 {0x0138U, 0x0000000000000000U},
311 {0x0140U, 0x0000000000000000U},
312 {0x0148U, 0x0000000000000000U},
313 {0x0150U, 0x0000000000000000U},
314 {0x0158U, 0x0000000000000000U},
315 {0x0160U, 0x0000000000000000U},
316 {0x0168U, 0x0000000000000000U},
317 {0x0170U, 0x0000000000000000U},
318 {0x0178U, 0x0000000000000000U},
319 {0x0180U, 0x0000000000000000U},
320 {0x0188U, 0x0000000000000000U},
321 {0x0190U, 0x0000000000000000U},
322 {0x0198U, 0x0000000000000000U},
323 {0x01A0U, 0x0000000000000000U},
324 {0x01A8U, 0x0000000000000000U},
325 {0x01B0U, 0x0000000000000000U},
326 {0x01B8U, 0x0000000000000000U},
327 {0x01C0U, 0x00110090060FA001U},
328 {0x01C8U, 0x00110090060FA001U},
329 {0x01D0U, 0x0000000000000000U},
330 {0x01D8U, 0x0000000000000000U},
331 {0x01E0U, 0x0000000000000000U},
332 {0x01E8U, 0x0000000000000000U},
333 {0x01F0U, 0x0011001006004401U},
334 {0x01F8U, 0x0000000000000000U},
335 {0x0200U, 0x0000000000000000U},
336 {0x0208U, 0x0000000000000000U},
337 {0x0210U, 0x0011001006004401U},
338 {0x0218U, 0x0011001006009801U},
339 {0x0220U, 0x0011001006009801U},
340 {0x0228U, 0x0000000000000000U},
341 {0x0230U, 0x0011001006009801U},
342 {0x0238U, 0x0011001006009801U},
343 {0x0240U, 0x0000000000000000U},
344 {0x0248U, 0x0000000000000000U},
345 {0x0250U, 0x0000000000000000U},
346 {0x0258U, 0x0000000000000000U},
347 {0x0260U, 0x0000000000000000U},
348 {0x0268U, 0x0000000000000000U},
349 {0x0270U, 0x0000000000000000U},
350 {0x0278U, 0x0000000000000000U},
351 {0x0280U, 0x0000000000000000U},
352 {0x0288U, 0x0000000000000000U},
353 {0x0290U, 0x0000000000000000U},
354 {0x0298U, 0x0000000000000000U},
355 {0x02A0U, 0x0000000000000000U},
356 {0x02A8U, 0x0000000000000000U},
357 {0x02B0U, 0x0000000000000000U},
358 {0x02B8U, 0x0011001006003401U},
359 {0x02C0U, 0x0000000000000000U},
360 {0x02C8U, 0x0000000000000000U},
361 {0x02D0U, 0x0000000000000000U},
362 {0x02D8U, 0x0000000000000000U},
363 {0x02E0U, 0x0000000000000000U},
364 {0x02E8U, 0x0011001006003401U},
365 {0x02F0U, 0x00110090060FA001U},
366 {0x02F8U, 0x00110090060FA001U},
367 {0x0300U, 0x0000000000000000U},
368 {0x0308U, 0x0000000000000000U},
369 {0x0310U, 0x0000000000000000U},
370 {0x0318U, 0x0012001006003401U},
371 {0x0320U, 0x0000000000000000U},
372 {0x0328U, 0x0000000000000000U},
373 {0x0330U, 0x0000000000000000U},
374 {0x0338U, 0x0000000000000000U},
375 {0x0340U, 0x0000000000000000U},
376 {0x0348U, 0x0000000000000000U},
377 {0x0350U, 0x0000000000000000U},
378 {0x0358U, 0x00120090060FA001U},
379 {0x0360U, 0x00120090060FA001U},
380 {0x0368U, 0x0012001006003401U},
381 {0x0370U, 0x0000000000000000U},
382 {0x0378U, 0x0000000000000000U},
383 {0x0380U, 0x0000000000000000U},
384 {0x0388U, 0x0000000000000000U},
385 {0x0390U, 0x0012001006003401U},
386};
387#endif
388
389static void dbsc_setting(void)
390{
391 uint32_t md=0;
392
393 /* BUFCAM settings */
394 //DBSC_DBCAM0CNF0 not set
395 io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
396 io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
397 io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
398 //DBSC_DBSCHCNT1 not set
399 io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
400 io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
401
402 md = (*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 19;
403
404 switch (md) {
405 case 0x0: //MD19=0 : DDR3L-1600, 4GByte(1GByte x4)
406 /* DDR1600 */
407 io_write_32(DBSC_SCFCTST2, 0x012F1123);
408 break;
409 default: //MD19=1 : DDR3L-1856, 4GByte(1GByte x4)
410 /* DDR1856 */
411 io_write_32(DBSC_SCFCTST2, 0x012F1123);
412 break;
413 }
414
415 /* QoS Settings */
416 io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
417 io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
418 io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
419 io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
420 //DBSC_DBSCHQOS_1_0 not set
421 //DBSC_DBSCHQOS_1_1 not set
422 //DBSC_DBSCHQOS_1_2 not set
423 //DBSC_DBSCHQOS_1_3 not set
424 //DBSC_DBSCHQOS_2_0 not set
425 //DBSC_DBSCHQOS_2_1 not set
426 //DBSC_DBSCHQOS_2_2 not set
427 //DBSC_DBSCHQOS_2_3 not set
428 //DBSC_DBSCHQOS_3_0 not set
429 //DBSC_DBSCHQOS_3_1 not set
430 //DBSC_DBSCHQOS_3_2 not set
431 //DBSC_DBSCHQOS_3_3 not set
432 io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
433 io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
434 io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
435 io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
436 //DBSC_DBSCHQOS_5_0 not set
437 //DBSC_DBSCHQOS_5_1 not set
438 //DBSC_DBSCHQOS_5_2 not set
439 //DBSC_DBSCHQOS_5_3 not set
440 //DBSC_DBSCHQOS_6_0 not set
441 //DBSC_DBSCHQOS_6_1 not set
442 //DBSC_DBSCHQOS_6_2 not set
443 //DBSC_DBSCHQOS_6_3 not set
444 //DBSC_DBSCHQOS_7_0 not set
445 //DBSC_DBSCHQOS_7_1 not set
446 //DBSC_DBSCHQOS_7_2 not set
447 //DBSC_DBSCHQOS_7_3 not set
448 //DBSC_DBSCHQOS_8_0 not set
449 //DBSC_DBSCHQOS_8_1 not set
450 //DBSC_DBSCHQOS_8_2 not set
451 //DBSC_DBSCHQOS_8_3 not set
452 io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
453 io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
454 io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
455 io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
456 //DBSC_DBSCHQOS_10_0 not set
457 //DBSC_DBSCHQOS_10_1 not set
458 //DBSC_DBSCHQOS_10_2 not set
459 //DBSC_DBSCHQOS_10_3 not set
460 //DBSC_DBSCHQOS_11_0 not set
461 //DBSC_DBSCHQOS_11_1 not set
462 //DBSC_DBSCHQOS_11_2 not set
463 //DBSC_DBSCHQOS_11_3 not set
464 //DBSC_DBSCHQOS_12_0 not set
465 //DBSC_DBSCHQOS_12_1 not set
466 //DBSC_DBSCHQOS_12_2 not set
467 //DBSC_DBSCHQOS_12_3 not set
468 io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
469 io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
470 io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
471 io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
472 io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
473 io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
474 io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
475 io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
476 io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
477 io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
478 io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
479 io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
480}
481
482void qos_init_d3(void)
483{
484 io_write_32(DBSC_DBSYSCNT0, 0x00001234);
485
486 dbsc_setting();
487
488 /* DRAM Split Address mapping */
489#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
490 ERROR("DRAM Split 4ch not supported.(D3)");
491 panic();
492#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
493 ERROR("DRAM Split 2ch not supported.(D3)");
494 panic();
495#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
496 ERROR("DRAM Split Auto not supported.(D3)");
497 panic();
498#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
499/* NOTICE("BL2: DRAM Split is OFF\n"); */
500 /* Split setting(DDR 1ch) */
501 io_write_32(AXI_ADSPLCR0, 0x00000000U);
502 io_write_32(AXI_ADSPLCR3, 0x00000000U);
503#else
504 ERROR("DRAM split is an invalid value.(D3)");
505 panic();
506#endif
507
508#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
509#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
510 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
511#endif
512
513 /* Resource Alloc setting */
514 io_write_32(RALLOC_RAS, 0x00000020U);
515 io_write_32(RALLOC_FIXTH, 0x000F0005U);
516 io_write_32(RALLOC_RAEN, 0x00000001U);
517 io_write_32(RALLOC_REGGD, 0x00000000U);
518 io_write_64(RALLOC_DANN, 0x0404020002020201U);
519 io_write_32(RALLOC_DANT, 0x00100804U);
520 io_write_32(RALLOC_EC, 0x00000000U);
521 io_write_64(RALLOC_EMS, 0x0000000000000000U);
522 io_write_32(RALLOC_FSS, 0x0000000AU);
523 io_write_32(RALLOC_INSFC, 0xC7840001U);
524 io_write_32(RALLOC_BERR, 0x00000000U);
525 io_write_32(RALLOC_EARLYR, 0x00000000U);
526 io_write_32(RALLOC_RACNT0, 0x00010003U);
527 io_write_32(RALLOC_TICKDUPL, 0x00000000U);
528
529 /* GPU setting */
530 io_write_32(0xFD812030U, 0x00000000U);
531
532 /* MSTAT setting */
533 io_write_32(MSTAT_SL_INIT, 0x030500ACU);
534 io_write_32(MSTAT_REF_ARS, 0x00780000U);
535
536 /* MSTAT SRAM setting */
537 {
538 uint32_t i;
539
540 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
541 io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
542 mstat_fix[i].value);
543 io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
544 mstat_fix[i].value);
545 }
546 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
547 io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
548 mstat_be[i].value);
549 io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
550 mstat_be[i].value);
551 }
552 }
553
554 /* 3DG bus Leaf setting */
555 io_write_32(0xFD820808U, 0x00001234U);
556 io_write_32(0xFD820800U, 0x00000000U);
557 io_write_32(0xFD821800U, 0x00000000U);
558 io_write_32(0xFD822800U, 0x00000000U);
559 io_write_32(0xFD823800U, 0x00000000U);
560
561 /* RT bus Leaf setting */
562 io_write_32(0xF1300800U, 0x00000003U);
563 io_write_32(0xF1340800U, 0x00000003U);
564 io_write_32(0xFFC50800U, 0x00000000U);
565 io_write_32(0xFFC51800U, 0x00000000U);
566
567 /* Resource Alloc start */
568 io_write_32(RALLOC_RAEN, 0x00000001U);
569
570 /* MSTAT start */
571 io_write_32(MSTAT_STATQC, 0x00000001U);
572#else
573 NOTICE("BL2: QoS is None\n");
574
575 /* Resource Alloc setting */
576 io_write_32(RALLOC_EC, 0x00000000U);
577 /* Resource Alloc start */
578 io_write_32(RALLOC_RAEN, 0x00000001U);
579#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
580 io_write_32(DBSC_DBSYSCNT0, 0x00000000);
581}