blob: 30a2420a046eec4226f0d57db432384a97e26bf3 [file] [log] [blame]
Tejas Patel354fe572018-12-14 00:55:37 -08001/*
2 * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/* Versal IPI management enums and defines */
8
9#ifndef PLAT_IPI_H
10#define PLAT_IPI_H
11
12#include <ipi.h>
13#include <stdint.h>
14
15/*********************************************************************
16 * IPI agent IDs macros
17 ********************************************************************/
18#define IPI_ID_PMC 1U
19#define IPI_ID_APU 2U
20#define IPI_ID_RPU0 3U
21#define IPI_ID_RPU1 4U
22#define IPI_ID_3 5U
23#define IPI_ID_4 6U
24#define IPI_ID_5 7U
25
26/*********************************************************************
27 * IPI message buffers
28 ********************************************************************/
29#define IPI_BUFFER_BASEADDR 0xFF3F0000U
30
31#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
32#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U)
33
Rajan Vaja1885bf12021-04-20 02:53:01 -070034#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
Tejas Patel354fe572018-12-14 00:55:37 -080035#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U
36
Tejas Patel354fe572018-12-14 00:55:37 -080037#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE
38
39#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET
40#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET
41
42#define IPI_BUFFER_MAX_WORDS 8
43
44#define IPI_BUFFER_REQ_OFFSET 0x0U
45#define IPI_BUFFER_RESP_OFFSET 0x20U
46
47/*********************************************************************
48 * Platform specific IPI API declarations
49 ********************************************************************/
50
51/* Configure IPI table for versal */
52void versal_ipi_config_table_init(void);
53
Michal Simekd62c8dd2023-04-25 12:46:03 +020054/* IPI registers and bitfields */
55#define PMC_REG_BASE U(0xFF320000)
56#define PMC_IPI_TRIG_BIT (1U << 1U)
57#define IPI0_REG_BASE U(0xFF330000)
58#define IPI0_TRIG_BIT (1U << 2U)
59#define IPI1_REG_BASE U(0xFF340000)
60#define IPI1_TRIG_BIT (1U << 3U)
61#define IPI2_REG_BASE U(0xFF350000)
62#define IPI2_TRIG_BIT (1U << 4U)
63#define IPI3_REG_BASE U(0xFF360000)
64#define IPI3_TRIG_BIT (1U << 5U)
65#define IPI4_REG_BASE U(0xFF370000)
66#define IPI4_TRIG_BIT (1U << 5U)
67#define IPI5_REG_BASE U(0xFF380000)
68#define IPI5_TRIG_BIT (1U << 6U)
69
Tejas Patel354fe572018-12-14 00:55:37 -080070#endif /* PLAT_IPI_H */