Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 1 | /* |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, ARM Limited. All rights reserved. |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 3 | * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <arch.h> |
| 9 | #include <asm_macros.S> |
| 10 | #include <common/bl_common.h> |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 11 | #include <cortex_a78_ae.h> |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 12 | #include <cpu_macros.S> |
| 13 | #include <plat_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 14 | #include "wa_cve_2022_23960_bhb_vector.S" |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 15 | |
| 16 | /* Hardware handled coherency */ |
| 17 | #if HW_ASSISTED_COHERENCY == 0 |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 18 | #error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 19 | #endif |
| 20 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 21 | #if WORKAROUND_CVE_2022_23960 |
| 22 | wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae |
| 23 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 24 | |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 25 | /* -------------------------------------------------- |
Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 26 | * Errata Workaround for A78 AE Erratum 1941500. |
| 27 | * This applies to revisions r0p0 and r0p1 of A78 AE. |
| 28 | * Inputs: |
| 29 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 30 | * Shall clobber: x0-x17 |
| 31 | * -------------------------------------------------- |
| 32 | */ |
| 33 | func errata_a78_ae_1941500_wa |
| 34 | /* Compare x0 against revisions r0p0 - r0p1 */ |
| 35 | mov x17, x30 |
| 36 | bl check_errata_1941500 |
| 37 | cbz x0, 1f |
| 38 | |
| 39 | /* Set bit 8 in ECTLR_EL1 */ |
| 40 | mrs x0, CORTEX_A78_AE_CPUECTLR_EL1 |
| 41 | bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 |
| 42 | msr CORTEX_A78_AE_CPUECTLR_EL1, x0 |
| 43 | isb |
| 44 | 1: |
| 45 | ret x17 |
| 46 | endfunc errata_a78_ae_1941500_wa |
| 47 | |
| 48 | func check_errata_1941500 |
| 49 | /* Applies to revisions r0p0 and r0p1. */ |
| 50 | mov x1, #CPU_REV(0, 0) |
| 51 | mov x2, #CPU_REV(0, 1) |
| 52 | b cpu_rev_var_range |
| 53 | endfunc check_errata_1941500 |
| 54 | |
| 55 | /* -------------------------------------------------- |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 56 | * Errata Workaround for A78 AE Erratum 1951502. |
| 57 | * This applies to revisions r0p0 and r0p1 of A78 AE. |
| 58 | * Inputs: |
| 59 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 60 | * Shall clobber: x0-x17 |
| 61 | * -------------------------------------------------- |
| 62 | */ |
| 63 | func errata_a78_ae_1951502_wa |
| 64 | /* Compare x0 against revisions r0p0 - r0p1 */ |
| 65 | mov x17, x30 |
| 66 | bl check_errata_1951502 |
| 67 | cbz x0, 1f |
| 68 | |
| 69 | msr S3_6_c15_c8_0, xzr |
| 70 | ldr x0, =0x10E3900002 |
| 71 | msr S3_6_c15_c8_2, x0 |
| 72 | ldr x0, =0x10FFF00083 |
| 73 | msr S3_6_c15_c8_3, x0 |
| 74 | ldr x0, =0x2001003FF |
| 75 | msr S3_6_c15_c8_1, x0 |
| 76 | |
| 77 | mov x0, #1 |
| 78 | msr S3_6_c15_c8_0, x0 |
| 79 | ldr x0, =0x10E3800082 |
| 80 | msr S3_6_c15_c8_2, x0 |
| 81 | ldr x0, =0x10FFF00083 |
| 82 | msr S3_6_c15_c8_3, x0 |
| 83 | ldr x0, =0x2001003FF |
| 84 | msr S3_6_c15_c8_1, x0 |
| 85 | |
| 86 | mov x0, #2 |
| 87 | msr S3_6_c15_c8_0, x0 |
| 88 | ldr x0, =0x10E3800200 |
| 89 | msr S3_6_c15_c8_2, x0 |
| 90 | ldr x0, =0x10FFF003E0 |
| 91 | msr S3_6_c15_c8_3, x0 |
| 92 | ldr x0, =0x2001003FF |
| 93 | msr S3_6_c15_c8_1, x0 |
| 94 | |
| 95 | isb |
| 96 | 1: |
| 97 | ret x17 |
| 98 | endfunc errata_a78_ae_1951502_wa |
| 99 | |
| 100 | func check_errata_1951502 |
| 101 | /* Applies to revisions r0p0 and r0p1. */ |
| 102 | mov x1, #CPU_REV(0, 0) |
| 103 | mov x2, #CPU_REV(0, 1) |
| 104 | b cpu_rev_var_range |
| 105 | endfunc check_errata_1951502 |
| 106 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 107 | func check_errata_cve_2022_23960 |
| 108 | #if WORKAROUND_CVE_2022_23960 |
| 109 | mov x0, #ERRATA_APPLIES |
| 110 | #else |
| 111 | mov x0, #ERRATA_MISSING |
| 112 | #endif |
| 113 | ret |
| 114 | endfunc check_errata_cve_2022_23960 |
| 115 | |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 116 | /* ------------------------------------------------- |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 117 | * The CPU Ops reset function for Cortex-A78-AE |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 118 | * ------------------------------------------------- |
| 119 | */ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 120 | func cortex_a78_ae_reset_func |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 121 | mov x19, x30 |
| 122 | bl cpu_get_rev_var |
| 123 | mov x18, x0 |
| 124 | |
Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 125 | #if ERRATA_A78_AE_1941500 |
| 126 | mov x0, x18 |
| 127 | bl errata_a78_ae_1941500_wa |
| 128 | #endif |
| 129 | |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 130 | #if ERRATA_A78_AE_1951502 |
| 131 | mov x0, x18 |
| 132 | bl errata_a78_ae_1951502_wa |
| 133 | #endif |
| 134 | |
| 135 | #if ENABLE_AMU |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 136 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 137 | mrs x0, actlr_el3 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 138 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 139 | msr actlr_el3, x0 |
| 140 | |
| 141 | /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ |
| 142 | mrs x0, actlr_el2 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 143 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 144 | msr actlr_el2, x0 |
| 145 | |
| 146 | /* Enable group0 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 147 | mov x0, #CORTEX_A78_AMU_GROUP0_MASK |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 148 | msr CPUAMCNTENSET0_EL0, x0 |
| 149 | |
| 150 | /* Enable group1 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 151 | mov x0, #CORTEX_A78_AMU_GROUP1_MASK |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 152 | msr CPUAMCNTENSET1_EL0, x0 |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 153 | #endif |
| 154 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 155 | #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 |
| 156 | /* |
| 157 | * The Cortex-A78AE generic vectors are overridden to apply errata |
| 158 | * mitigation on exception entry from lower ELs. |
| 159 | */ |
| 160 | adr x0, wa_cve_vbar_cortex_a78_ae |
| 161 | msr vbar_el3, x0 |
| 162 | #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 163 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 164 | isb |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 165 | ret x19 |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 166 | endfunc cortex_a78_ae_reset_func |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 167 | |
| 168 | /* ------------------------------------------------------- |
| 169 | * HW will do the cache maintenance while powering down |
| 170 | * ------------------------------------------------------- |
| 171 | */ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 172 | func cortex_a78_ae_core_pwr_dwn |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 173 | /* ------------------------------------------------------- |
| 174 | * Enable CPU power down bit in power control register |
| 175 | * ------------------------------------------------------- |
| 176 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 177 | mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 |
| 178 | orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
| 179 | msr CORTEX_A78_CPUPWRCTLR_EL1, x0 |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 180 | isb |
| 181 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 182 | endfunc cortex_a78_ae_core_pwr_dwn |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 183 | |
| 184 | /* |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 185 | * Errata printing function for cortex_a78_ae. Must follow AAPCS. |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 186 | */ |
| 187 | #if REPORT_ERRATA |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 188 | func cortex_a78_ae_errata_report |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 189 | stp x8, x30, [sp, #-16]! |
| 190 | |
| 191 | bl cpu_get_rev_var |
| 192 | mov x8, x0 |
| 193 | |
| 194 | /* |
| 195 | * Report all errata. The revision-variant information is passed to |
| 196 | * checking functions of each errata. |
| 197 | */ |
Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 198 | report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500 |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 199 | report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 200 | report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960 |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 201 | |
| 202 | ldp x8, x30, [sp], #16 |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 203 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 204 | endfunc cortex_a78_ae_errata_report |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 205 | #endif |
| 206 | |
| 207 | /* ------------------------------------------------------- |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 208 | * This function provides cortex_a78_ae specific |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 209 | * register information for crash reporting. |
| 210 | * It needs to return with x6 pointing to |
| 211 | * a list of register names in ascii and |
| 212 | * x8 - x15 having values of registers to be |
| 213 | * reported. |
| 214 | * ------------------------------------------------------- |
| 215 | */ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 216 | .section .rodata.cortex_a78_ae_regs, "aS" |
| 217 | cortex_a78_ae_regs: /* The ascii list of register names to be reported */ |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 218 | .asciz "cpuectlr_el1", "" |
| 219 | |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 220 | func cortex_a78_ae_cpu_reg_dump |
| 221 | adr x6, cortex_a78_ae_regs |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 222 | mrs x8, CORTEX_A78_CPUECTLR_EL1 |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 223 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 224 | endfunc cortex_a78_ae_cpu_reg_dump |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 225 | |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 226 | declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ |
Varun Wadekar | a3110ad | 2021-07-27 00:39:40 -0700 | [diff] [blame] | 227 | cortex_a78_ae_reset_func, \ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 228 | cortex_a78_ae_core_pwr_dwn |