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git01.mediatek.com / filogic / atf / d9453fdc815ff2edd959989ca30d9189bd3d85b6 / . / plat / renesas / rcar / bl2_secure_setting.c
blob: 35c658c0dcdae9a008c1432f70443099d8ec4c18 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include "axi_registers.h"
8#include "lifec_registers.h"
9#include "micro_delay.h"
10#include "mmio.h"
11#include "utils_def.h"
12
13static void lifec_security_setting(void);
14static void axi_security_setting(void);
15
16static const struct {
17 uint32_t reg;
18 uint32_t val;
19} lifec[] = {
20 /** LIFEC0 (SECURITY) settings */
21 /* Security attribute setting for master ports */
22 /* Bit 0: ARM realtime core (Cortex-R7) master port */
23 /* 0: Non-Secure */
24 {
25 SEC_SRC, 0x0000001EU},
26 /** Security attribute setting for slave ports 0 to 15 */
27 /* {SEC_SEL0, 0xFFFFFFFFU}, */
28 /* {SEC_SEL1, 0xFFFFFFFFU}, */
29 /* {SEC_SEL2, 0xFFFFFFFFU}, */
30 /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports */
31 /* 0: registers accessed from secure resource only */
32 /* Bit 9: DBSC4 register access slave ports. */
33 /* 0: registers accessed from secure resource only. */
34#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
35 {
36 SEC_SEL3, 0xFFF7FDFFU},
37#else
38 {
39 SEC_SEL3, 0xFFFFFFFFU},
40#endif
41 /* {SEC_SEL4, 0xFFFFFFFFU}, */
42 /* Bit 6: Boot ROM slave ports. */
43 /* 0: registers accessed from secure resource only */
44 {
45 SEC_SEL5, 0xFFFFFFBFU},
46 /* Bit13: SCEG PKA (secure APB) slave ports */
47 /* 0: registers accessed from secure resource only */
48 /* 1: Reserved[R-Car E3] */
49 /* Bit12: SCEG PKA (public APB) slave ports */
50 /* 0: registers accessed from secure resource only */
51 /* 1: Reserved[R-Car E3] */
52 /* Bit10: SCEG Secure Core slave ports */
53 /* 0: registers accessed from secure resource only */
54#if RCAR_LSI == RCAR_E3
55 {
56 SEC_SEL6, 0xFFFFFBFFU},
57#else
58 {
59 SEC_SEL6, 0xFFFFCBFFU},
60#endif
61 /* {SEC_SEL7, 0xFFFFFFFFU}, */
62 /* {SEC_SEL8, 0xFFFFFFFFU}, */
63 /* {SEC_SEL9, 0xFFFFFFFFU}, */
64 /* {SEC_SEL10, 0xFFFFFFFFU}, */
65 /* {SEC_SEL11, 0xFFFFFFFFU}, */
66 /* {SEC_SEL12, 0xFFFFFFFFU}, */
67 /* Bit22: RPC slave ports. */
68 /* 0: registers accessed from secure resource only. */
69 /* {SEC_SEL13, 0xFFBFFFFFU},*/
70 /* Bit27: System Timer (SCMT) slave ports */
71 /* 0: registers accessed from secure resource only */
72 /* Bit26: System Watchdog Timer (SWDT) slave ports */
73 /* 0: registers accessed from secure resource only */
74 {
75 SEC_SEL14, 0xF3FFFFFFU},
76 /* Bit13: RST slave ports. */
77 /* 0: registers accessed from secure resource only */
78 /* Bit 7: Life Cycle 0 slave ports */
79 /* 0: registers accessed from secure resource only */
80 {
81 SEC_SEL15, 0xFFFFFF3FU},
82 /** Security group 0 attribute setting for master ports 0 */
83 /** Security group 1 attribute setting for master ports 0 */
84 /* {SEC_GRP0CR0, 0x00000000U}, */
85 /* {SEC_GRP1CR0, 0x00000000U}, */
86 /** Security group 0 attribute setting for master ports 1 */
87 /** Security group 1 attribute setting for master ports 1 */
88 /* {SEC_GRP0CR1, 0x00000000U}, */
89 /* {SEC_GRP1CR1, 0x00000000U}, */
90 /** Security group 0 attribute setting for master ports 2 */
91 /** Security group 1 attribute setting for master ports 2 */
92 /* Bit17: SCEG Secure Core master ports. */
93 /* SecurityGroup3 */
94 {
95 SEC_GRP0CR2, 0x00020000U}, {
96 SEC_GRP1CR2, 0x00020000U},
97 /** Security group 0 attribute setting for master ports 3 */
98 /** Security group 1 attribute setting for master ports 3 */
99 /* {SEC_GRP0CR3, 0x00000000U}, */
100 /* {SEC_GRP1CR3, 0x00000000U}, */
101 /** Security group 0 attribute setting for slave ports 0 */
102 /** Security group 1 attribute setting for slave ports 0 */
103 /* {SEC_GRP0COND0, 0x00000000U}, */
104 /* {SEC_GRP1COND0, 0x00000000U}, */
105 /** Security group 0 attribute setting for slave ports 1 */
106 /** Security group 1 attribute setting for slave ports 1 */
107 /* {SEC_GRP0COND1, 0x00000000U}, */
108 /* {SEC_GRP1COND1, 0x00000000U}, */
109 /** Security group 0 attribute setting for slave ports 2 */
110 /** Security group 1 attribute setting for slave ports 2 */
111 /* {SEC_GRP0COND2, 0x00000000U}, */
112 /* {SEC_GRP1COND2, 0x00000000U}, */
113 /** Security group 0 attribute setting for slave ports 3 */
114 /** Security group 1 attribute setting for slave ports 3 */
115 /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports. */
116 /* SecurityGroup3 */
117 /* Bit 9: DBSC4 register access slave ports. */
118 /* SecurityGroup3 */
119#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
120 {
121 SEC_GRP0COND3, 0x00080200U}, {
122 SEC_GRP1COND3, 0x00080200U},
123#else
124 {
125 SEC_GRP0COND3, 0x00000000U}, {
126 SEC_GRP1COND3, 0x00000000U},
127#endif
128 /** Security group 0 attribute setting for slave ports 4 */
129 /** Security group 1 attribute setting for slave ports 4 */
130 /* {SEC_GRP0COND4, 0x00000000U}, */
131 /* {SEC_GRP1COND4, 0x00000000U}, */
132 /** Security group 0 attribute setting for slave ports 5 */
133 /** Security group 1 attribute setting for slave ports 5 */
134 /* Bit 6: Boot ROM slave ports */
135 /* SecurityGroup3 */
136 {
137 SEC_GRP0COND5, 0x00000040U}, {
138 SEC_GRP1COND5, 0x00000040U},
139 /** Security group 0 attribute setting for slave ports 6 */
140 /** Security group 1 attribute setting for slave ports 6 */
141 /* Bit13: SCEG PKA (secure APB) slave ports */
142 /* SecurityGroup3 */
143 /* Reserved[R-Car E3] */
144 /* Bit12: SCEG PKA (public APB) slave ports */
145 /* SecurityGroup3 */
146 /* Reserved[R-Car E3] */
147 /* Bit10: SCEG Secure Core slave ports */
148 /* SecurityGroup3 */
149#if RCAR_LSI == RCAR_E3
150 {
151 SEC_GRP0COND6, 0x00000400U}, {
152 SEC_GRP1COND6, 0x00000400U},
153#else
154 {
155 SEC_GRP0COND6, 0x00003400U}, {
156 SEC_GRP1COND6, 0x00003400U},
157#endif
158 /** Security group 0 attribute setting for slave ports 7 */
159 /** Security group 1 attribute setting for slave ports 7 */
160 /* {SEC_GRP0COND7, 0x00000000U}, */
161 /* {SEC_GRP1COND7, 0x00000000U}, */
162 /** Security group 0 attribute setting for slave ports 8 */
163 /** Security group 1 attribute setting for slave ports 8 */
164 /* {SEC_GRP0COND8, 0x00000000U}, */
165 /* {SEC_GRP1COND8, 0x00000000U}, */
166 /** Security group 0 attribute setting for slave ports 9 */
167 /** Security group 1 attribute setting for slave ports 9 */
168 /* {SEC_GRP0COND9, 0x00000000U}, */
169 /* {SEC_GRP1COND9, 0x00000000U}, */
170 /** Security group 0 attribute setting for slave ports 10 */
171 /** Security group 1 attribute setting for slave ports 10 */
172 /* {SEC_GRP0COND10, 0x00000000U}, */
173 /* {SEC_GRP1COND10, 0x00000000U}, */
174 /** Security group 0 attribute setting for slave ports 11 */
175 /** Security group 1 attribute setting for slave ports 11 */
176 /* {SEC_GRP0COND11, 0x00000000U}, */
177 /* {SEC_GRP1COND11, 0x00000000U}, */
178 /** Security group 0 attribute setting for slave ports 12 */
179 /** Security group 1 attribute setting for slave ports 12 */
180 /* {SEC_GRP0COND12, 0x00000000U}, */
181 /* {SEC_GRP1COND12, 0x00000000U}, */
182 /** Security group 0 attribute setting for slave ports 13 */
183 /** Security group 1 attribute setting for slave ports 13 */
184 /* Bit22: RPC slave ports. */
185 /* SecurityGroup3 */
186 /* {SEC_GRP0COND13, 0x00400000U}, */
187 /* {SEC_GRP1COND13, 0x00400000U}, */
188 /** Security group 0 attribute setting for slave ports 14 */
189 /** Security group 1 attribute setting for slave ports 14 */
190 /* Bit26: System Timer (SCMT) slave ports */
191 /* SecurityGroup3 */
192 /* Bit27: System Watchdog Timer (SWDT) slave ports */
193 /* SecurityGroup3 */
194 {
195 SEC_GRP0COND14, 0x0C000000U}, {
196 SEC_GRP1COND14, 0x0C000000U},
197 /** Security group 0 attribute setting for slave ports 15 */
198 /** Security group 1 attribute setting for slave ports 15 */
199 /* Bit13: RST slave ports */
200 /* SecurityGroup3 */
201 /* Bit 7: Life Cycle 0 slave ports */
202 /* SecurityGroup3 */
203 /* Bit 6: TDBG slave ports */
204 /* SecurityGroup3 */
205 {
206 SEC_GRP0COND15, 0x000000C0U}, {
207 SEC_GRP1COND15, 0x000000C0U},
208 /** Security write protection attribute setting slave ports 0 */
209 /* {SEC_READONLY0, 0x00000000U}, */
210 /** Security write protection attribute setting slave ports 1 */
211 /* {SEC_READONLY1, 0x00000000U}, */
212 /** Security write protection attribute setting slave ports 2 */
213 /* {SEC_READONLY2, 0x00000000U}, */
214 /** Security write protection attribute setting slave ports 3 */
215 /* {SEC_READONLY3, 0x00000000U}, */
216 /** Security write protection attribute setting slave ports 4 */
217 /* {SEC_READONLY4, 0x00000000U}, */
218 /** Security write protection attribute setting slave ports 5 */
219 /* {SEC_READONLY5, 0x00000000U}, */
220 /** Security write protection attribute setting slave ports 6 */
221 /* {SEC_READONLY6, 0x00000000U}, */
222 /** Security write protection attribute setting slave ports 7 */
223 /* {SEC_READONLY7, 0x00000000U}, */
224 /** Security write protection attribute setting slave ports 8 */
225 /* {SEC_READONLY8, 0x00000000U}, */
226 /** Security write protection attribute setting slave ports 9 */
227 /* {SEC_READONLY9, 0x00000000U}, */
228 /** Security write protection attribute setting slave ports 10 */
229 /* {SEC_READONLY10, 0x00000000U}, */
230 /** Security write protection attribute setting slave ports 11 */
231 /* {SEC_READONLY11, 0x00000000U}, */
232 /** Security write protection attribute setting slave ports 12 */
233 /* {SEC_READONLY12, 0x00000000U}, */
234 /** Security write protection attribute setting slave ports 13 */
235 /* {SEC_READONLY13, 0x00000000U}, */
236 /** Security write protection attribute setting slave ports 14 */
237 /* {SEC_READONLY14, 0x00000000U}, */
238 /** Security write protection attribute setting slave ports 15 */
239 /* {SEC_READONLY15, 0x00000000U} */
240};
241
242/* AXI settings */
243static const struct {
244 uint32_t reg;
245 uint32_t val;
246} axi[] = {
247 /* DRAM protection */
248 /* AXI dram protected area division */
249 {
250 AXI_DPTDIVCR0, 0x0E0403F0U}, {
251 AXI_DPTDIVCR1, 0x0E0407E0U}, {
252 AXI_DPTDIVCR2, 0x0E080000U}, {
253 AXI_DPTDIVCR3, 0x0E080000U}, {
254 AXI_DPTDIVCR4, 0x0E080000U}, {
255 AXI_DPTDIVCR5, 0x0E080000U}, {
256 AXI_DPTDIVCR6, 0x0E080000U}, {
257 AXI_DPTDIVCR7, 0x0E080000U}, {
258 AXI_DPTDIVCR8, 0x0E080000U}, {
259 AXI_DPTDIVCR9, 0x0E080000U}, {
260 AXI_DPTDIVCR10, 0x0E080000U}, {
261 AXI_DPTDIVCR11, 0x0E080000U}, {
262 AXI_DPTDIVCR12, 0x0E080000U}, {
263 AXI_DPTDIVCR13, 0x0E080000U}, {
264 AXI_DPTDIVCR14, 0x0E080000U},
265 /* AXI dram protected area setting */
266 {
267 AXI_DPTCR0, 0x0E000000U}, {
268 AXI_DPTCR1, 0x0E000E0EU}, {
269 AXI_DPTCR2, 0x0E000000U}, {
270 AXI_DPTCR3, 0x0E000000U}, {
271 AXI_DPTCR4, 0x0E000000U}, {
272 AXI_DPTCR5, 0x0E000000U}, {
273 AXI_DPTCR6, 0x0E000000U}, {
274 AXI_DPTCR7, 0x0E000000U}, {
275 AXI_DPTCR8, 0x0E000000U}, {
276 AXI_DPTCR9, 0x0E000000U}, {
277 AXI_DPTCR10, 0x0E000000U}, {
278 AXI_DPTCR11, 0x0E000000U}, {
279 AXI_DPTCR12, 0x0E000000U}, {
280 AXI_DPTCR13, 0x0E000000U}, {
281 AXI_DPTCR14, 0x0E000000U}, {
282 AXI_DPTCR15, 0x0E000000U},
283 /* SRAM ptotection */
284 /* AXI sram protected area division */
285 {
286 AXI_SPTDIVCR0, 0x0E0E6304U}, {
287 AXI_SPTDIVCR1, 0x0E0E6360U}, {
288 AXI_SPTDIVCR2, 0x0E0E6360U}, {
289 AXI_SPTDIVCR3, 0x0E0E6360U}, {
290 AXI_SPTDIVCR4, 0x0E0E6360U}, {
291 AXI_SPTDIVCR5, 0x0E0E6360U}, {
292 AXI_SPTDIVCR6, 0x0E0E6360U}, {
293 AXI_SPTDIVCR7, 0x0E0E6360U}, {
294 AXI_SPTDIVCR8, 0x0E0E6360U}, {
295 AXI_SPTDIVCR9, 0x0E0E6360U}, {
296 AXI_SPTDIVCR10, 0x0E0E6360U}, {
297 AXI_SPTDIVCR11, 0x0E0E6360U}, {
298 AXI_SPTDIVCR12, 0x0E0E6360U}, {
299 AXI_SPTDIVCR13, 0x0E0E6360U}, {
300 AXI_SPTDIVCR14, 0x0E0E6360U},
301 /* AXI sram protected area setting */
302 {
303 AXI_SPTCR0, 0x0E000E0EU}, {
304 AXI_SPTCR1, 0x0E000000U}, {
305 AXI_SPTCR2, 0x0E000000U}, {
306 AXI_SPTCR3, 0x0E000000U}, {
307 AXI_SPTCR4, 0x0E000000U}, {
308 AXI_SPTCR5, 0x0E000000U}, {
309 AXI_SPTCR6, 0x0E000000U}, {
310 AXI_SPTCR7, 0x0E000000U}, {
311 AXI_SPTCR8, 0x0E000000U}, {
312 AXI_SPTCR9, 0x0E000000U}, {
313 AXI_SPTCR10, 0x0E000000U}, {
314 AXI_SPTCR11, 0x0E000000U}, {
315 AXI_SPTCR12, 0x0E000000U}, {
316 AXI_SPTCR13, 0x0E000000U}, {
317 AXI_SPTCR14, 0x0E000000U}, {
318 AXI_SPTCR15, 0x0E000000U}
319};
320
321static void lifec_security_setting(void)
322{
323 uint32_t i;
324
325 for (i = 0; i < ARRAY_SIZE(lifec); i++)
326 mmio_write_32(lifec[i].reg, lifec[i].val);
327}
328
329/* SRAM/DRAM protection setting */
330static void axi_security_setting(void)
331{
332 uint32_t i;
333
334 for (i = 0; i < ARRAY_SIZE(axi); i++)
335 mmio_write_32(axi[i].reg, axi[i].val);
336}
337
338void bl2_secure_setting(void)
339{
340 const uint32_t delay = 10;
341
342 lifec_security_setting();
343 axi_security_setting();
344 rcar_micro_delay(delay);
345
346 return;
347}