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git01.mediatek.com / filogic / atf / 4d93d1d5797cceb6ef0a70df861fd565553a3b27 / . / plat / imx / imx8ulp / imx8ulp_bl31_setup.c
blob: c25726351d04ec87d03b8273a7be86034b02c52f [file] [log] [blame]
Jacky Bai4d93d1d2020-07-02 14:39:58 +0800[diff] [blame^]1/*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <stdbool.h>
9
10#include <arch_helpers.h>
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <context.h>
14#include <drivers/console.h>
15#include <drivers/generic_delay_timer.h>
16#include <lib/el3_runtime/context_mgmt.h>
17#include <lib/mmio.h>
18#include <lib/xlat_tables/xlat_tables_v2.h>
19#include <plat/common/platform.h>
20#include <platform_def.h>
21
22#include <imx8_lpuart.h>
23#include <imx_plat_common.h>
24#include <plat_imx8.h>
25#include <upower_api.h>
26
27#define MAP_BL31_TOTAL \
28 MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE)
29#define MAP_BL31_RO \
30 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
31
32#define MAP_COHERENT_MEM \
33 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), \
34 MT_DEVICE | MT_RW | MT_SECURE)
35
36static const mmap_region_t imx_mmap[] = {
37 DEVICE0_MAP, DEVICE1_MAP, ELE_MAP,
38 SEC_SIM_MAP, SRAM0_MAP,
39 {0}
40};
41
42extern uint32_t upower_init(void);
43extern void imx8ulp_init_scmi_server(void);
44
45static entry_point_info_t bl32_image_ep_info;
46static entry_point_info_t bl33_image_ep_info;
47
48void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
49 u_register_t arg2, u_register_t arg3)
50{
51 static console_t console;
52
53
54 /* enable the GPIO D,E,F non-secure access by default */
55 mmio_write_32(IMX_PCC4_BASE + 0x78, 0xc0000000);
56 mmio_write_32(IMX_PCC4_BASE + 0x7c, 0xc0000000);
57 mmio_write_32(IMX_PCC5_BASE + 0x114, 0xc0000000);
58
59 mmio_write_32(IMX_GPIOE_BASE + 0x10, 0xffffffff);
60 mmio_write_32(IMX_GPIOE_BASE + 0x14, 0x3);
61 mmio_write_32(IMX_GPIOE_BASE + 0x18, 0xffffffff);
62 mmio_write_32(IMX_GPIOE_BASE + 0x1c, 0x3);
63
64 mmio_write_32(IMX_GPIOF_BASE + 0x10, 0xffffffff);
65 mmio_write_32(IMX_GPIOF_BASE + 0x14, 0x3);
66 mmio_write_32(IMX_GPIOF_BASE + 0x18, 0xffffffff);
67 mmio_write_32(IMX_GPIOF_BASE + 0x1c, 0x3);
68
69 mmio_write_32(IMX_GPIOD_BASE + 0x10, 0xffffffff);
70 mmio_write_32(IMX_GPIOD_BASE + 0x14, 0x3);
71 mmio_write_32(IMX_GPIOD_BASE + 0x18, 0xffffffff);
72 mmio_write_32(IMX_GPIOD_BASE + 0x1c, 0x3);
73
74 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
75 IMX_CONSOLE_BAUDRATE, &console);
76
77 /* This console is only used for boot stage */
78 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
79
80 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
81 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry();
82 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
83}
84
85void bl31_plat_arch_setup(void)
86{
87 const mmap_region_t bl_regions[] = {
88 MAP_BL31_TOTAL,
89 MAP_BL31_RO,
90#if USE_COHERENT_MEM
91 MAP_COHERENT_MEM,
92#endif
93 {0},
94 };
95
96 setup_page_tables(bl_regions, imx_mmap);
97 enable_mmu_el3(0);
98
99 /* TODO: Hack, refine this piece, scmi channel free */
100 mmio_write_32(SRAM0_BASE + 0x4, 1);
101}
102
103void bl31_platform_setup(void)
104{
105 /* select the arch timer source */
106 mmio_setbits_32(IMX_SIM1_BASE + 0x30, 0x8000000);
107
108 generic_delay_timer_init();
109
110 plat_gic_driver_init();
111 plat_gic_init();
112
113 imx8ulp_init_scmi_server();
114 upower_init();
115}
116
117entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
118{
119 if (type == NON_SECURE) {
120 return &bl33_image_ep_info;
121 } else {
122 return &bl32_image_ep_info;
123 }
124}
125
126unsigned int plat_get_syscnt_freq2(void)
127{
128 return COUNTER_FREQUENCY;
129}
130
131void bl31_plat_runtime_setup(void)
132{
133}