blob: 05461928d277f9a6887626c1c96daa4894fe1237 [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <platform_def.h>
10
11#include <plat/common/platform.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <drivers/arm/ccn.h>
15#include <plat/arm/common/plat_arm.h>
16#include <plat/common/platform.h>
17#include <drivers/arm/sbsa.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020018
19#if SPM_MM
Usama Arifbec5afd2020-04-17 16:13:39 +010020#include <services/spm_mm_partition.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020021#endif
Usama Arifbec5afd2020-04-17 16:13:39 +010022
23/*
24 * Table of regions for different BL stages to map using the MMU.
25 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
26 * arm_configure_mmu_elx() will give the available subset of that.
27 */
28#if IMAGE_BL1
29const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
31 TC0_FLASH0_RO,
32 TC0_MAP_DEVICE,
33 {0}
34};
35#endif
36#if IMAGE_BL2
37const mmap_region_t plat_arm_mmap[] = {
38 ARM_MAP_SHARED_RAM,
39 TC0_FLASH0_RO,
40 TC0_MAP_DEVICE,
41 ARM_MAP_NS_DRAM1,
42#if ARM_BL31_IN_DRAM
43 ARM_MAP_BL31_SEC_DRAM,
44#endif
45#if SPM_MM
46 ARM_SP_IMAGE_MMAP,
47#endif
48#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
49 ARM_MAP_BL1_RW,
50#endif
51 {0}
52};
53#endif
54#if IMAGE_BL31
55const mmap_region_t plat_arm_mmap[] = {
56 ARM_MAP_SHARED_RAM,
57 V2M_MAP_IOFPGA,
58 TC0_MAP_DEVICE,
59#if SPM_MM
60 ARM_SPM_BUF_EL3_MMAP,
61#endif
62 {0}
63};
64
65#if SPM_MM && defined(IMAGE_BL31)
66const mmap_region_t plat_arm_secure_partition_mmap[] = {
67 PLAT_ARM_SECURE_MAP_DEVICE,
68 ARM_SP_IMAGE_MMAP,
69 ARM_SP_IMAGE_NS_BUF_MMAP,
70 ARM_SP_CPER_BUF_MMAP,
71 ARM_SP_IMAGE_RW_MMAP,
72 ARM_SPM_BUF_EL0_MMAP,
73 {0}
74};
75#endif /* SPM_MM && defined(IMAGE_BL31) */
76#endif
77
78ARM_CASSERT_MMAP
79
80#if SPM_MM && defined(IMAGE_BL31)
81/*
82 * Boot information passed to a secure partition during initialisation. Linear
83 * indices in MP information will be filled at runtime.
84 */
85static spm_mm_mp_info_t sp_mp_info[] = {
86 [0] = {0x81000000, 0},
87 [1] = {0x81000100, 0},
88 [2] = {0x81000200, 0},
89 [3] = {0x81000300, 0},
90 [4] = {0x81010000, 0},
91 [5] = {0x81010100, 0},
92 [6] = {0x81010200, 0},
93 [7] = {0x81010300, 0},
94};
95
96const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
97 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
98 .h.version = VERSION_1,
99 .h.size = sizeof(spm_mm_boot_info_t),
100 .h.attr = 0,
101 .sp_mem_base = ARM_SP_IMAGE_BASE,
102 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
103 .sp_image_base = ARM_SP_IMAGE_BASE,
104 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
105 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
106 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
107 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
108 .sp_image_size = ARM_SP_IMAGE_SIZE,
109 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
110 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
111 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
112 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
113 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
114 .num_cpus = PLATFORM_CORE_COUNT,
115 .mp_info = &sp_mp_info[0],
116};
117
118const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
119{
120 return plat_arm_secure_partition_mmap;
121}
122
123const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
124 void *cookie)
125{
126 return &plat_arm_secure_partition_boot_info;
127}
128#endif /* SPM_MM && defined(IMAGE_BL31) */
129
130#if TRUSTED_BOARD_BOOT
131int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
132{
133 assert(heap_addr != NULL);
134 assert(heap_size != NULL);
135
136 return arm_get_mbedtls_heap(heap_addr, heap_size);
137}
138#endif
139
140void plat_arm_secure_wdt_start(void)
141{
142 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
143}
144
145void plat_arm_secure_wdt_stop(void)
146{
147 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
148}