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developer550bf5e2016-07-11 16:05:23 +08001/*
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
developer550bf5e2016-07-11 16:05:23 +08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
developer550bf5e2016-07-11 16:05:23 +08005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
developer550bf5e2016-07-11 16:05:23 +080011
12#define PLAT_PRIMARY_CPU 0x0
13
14/* Special value used to verify platform parameters from BL2 to BL3-1 */
15#define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
16
17#define IO_PHYS (0x10000000)
18#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
19#define MCUCFG_BASE (IO_PHYS + 0x200000)
20#define PERI_BASE (IO_PHYS + 0x1000000)
21
22
23#define GPIO_BASE (IO_PHYS + 0x370000)
24#define SPM_BASE (IO_PHYS + 0x6000)
25#define RGU_BASE (MCUCFG_BASE + 0x11000)
26#define PMIC_WRAP_BASE (IO_PHYS + 0x10000)
27
28#define TRNG_base (MCUCFG_BASE + 0x230000)
29#define MT_GIC_BASE (0x10220000)
30#define MCU_SYS_SIZE (0x700000)
31#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)
32
33/* Aggregate of all devices in the first GB */
34#define MTK_DEV_RNG0_BASE IO_PHYS
35#define MTK_DEV_RNG0_SIZE 0x400000
36#define MTK_DEV_RNG1_BASE (PERI_BASE)
37#define MTK_DEV_RNG1_SIZE 0x4000000
38
39/*******************************************************************************
40 * UART related constants
41 ******************************************************************************/
42#define UART0_BASE (PERI_BASE + 0x2000)
43
44#define UART_BAUDRATE (921600)
45#define UART_CLOCK (26000000)
46
47/*******************************************************************************
48 * System counter frequency related constants
49 ******************************************************************************/
50#define SYS_COUNTER_FREQ_IN_TICKS 13000000
51#define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS/1000000)
52
53/*******************************************************************************
54 * GIC-400 & interrupt handling related constants
55 ******************************************************************************/
56
57/* Base MTK_platform compatible GIC memory map */
58#define BASE_GICD_BASE (MT_GIC_BASE+0x1000)
59#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000)
60#define BASE_GICR_BASE (MT_GIC_BASE + 0x200000)
61#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
62#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
63
64#define INT_POL_CTL0 0x10200620
65#define GIC_PRIVATE_SIGNALS (32)
66
67/*******************************************************************************
68 * CCI-400 related constants
69 ******************************************************************************/
70#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
71#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
72
73/*******************************************************************************
74 * WDT Registers
75 ******************************************************************************/
76#define MTK_WDT_BASE (RGU_BASE)
77#define MTK_WDT_SIZE (0x1000)
78#define MTK_WDT_MODE (MTK_WDT_BASE+0x0000)
79#define MTK_WDT_LENGTH (MTK_WDT_BASE+0x0004)
80#define MTK_WDT_RESTART (MTK_WDT_BASE+0x0008)
81#define MTK_WDT_STATUS (MTK_WDT_BASE+0x000C)
82#define MTK_WDT_INTERVAL (MTK_WDT_BASE+0x0010)
83#define MTK_WDT_SWRST (MTK_WDT_BASE+0x0014)
84#define MTK_WDT_SWSYSRST (MTK_WDT_BASE+0x0018)
85#define MTK_WDT_NONRST_REG (MTK_WDT_BASE+0x0020)
86#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE+0x0024)
87#define MTK_WDT_REQ_MODE (MTK_WDT_BASE+0x0030)
88#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE+0x0034)
89#define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE+0x0040)
90
91/*WDT_STATUS*/
92#define MTK_WDT_STATUS_HWWDT_RST (0x80000000)
93#define MTK_WDT_STATUS_SWWDT_RST (0x40000000)
94#define MTK_WDT_STATUS_IRQWDT_RST (0x20000000)
95#define MTK_WDT_STATUS_DEBUGWDT_RST (0x00080000)
96#define MTK_WDT_STATUS_SPMWDT_RST (0x0002)
97#define MTK_WDT_STATUS_SPM_THERMAL_RST (0x0001)
98#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1<<18)
99#define MTK_WDT_STATUS_SECURITY_RST (1<<28)
100
101#define MTK_WDT_MODE_DUAL_MODE 0x0040
102#define MTK_WDT_MODE_IRQ 0x0008
103#define MTK_WDT_MODE_KEY 0x22000000
104#define MTK_WDT_MODE_EXTEN 0x0004
105#define MTK_WDT_SWRST_KEY 0x1209
106#define MTK_WDT_RESTART_KEY (0x1971)
107
108/* FIQ platform related define */
109#define MT_IRQ_SEC_SGI_0 8
110#define MT_IRQ_SEC_SGI_1 9
111#define MT_IRQ_SEC_SGI_2 10
112#define MT_IRQ_SEC_SGI_3 11
113#define MT_IRQ_SEC_SGI_4 12
114#define MT_IRQ_SEC_SGI_5 13
115#define MT_IRQ_SEC_SGI_6 14
116#define MT_IRQ_SEC_SGI_7 15
117
118#define FIQ_SMP_CALL_SGI MT_IRQ_SEC_SGI_5
119
developer550bf5e2016-07-11 16:05:23 +0800120/*******************************************************************************
121 * Platform binary types for linking
122 ******************************************************************************/
123#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
124#define PLATFORM_LINKER_ARCH aarch64
125
126/*******************************************************************************
127 * Generic platform constants
128 ******************************************************************************/
129
130/* Size of cacheable stacks */
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100131#if defined(IMAGE_BL1)
developer550bf5e2016-07-11 16:05:23 +0800132#define PLATFORM_STACK_SIZE 0x440
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900133#elif defined(IMAGE_BL2)
developer550bf5e2016-07-11 16:05:23 +0800134#define PLATFORM_STACK_SIZE 0x400
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900135#elif defined(IMAGE_BL31)
developer550bf5e2016-07-11 16:05:23 +0800136#define PLATFORM_STACK_SIZE 0x800
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900137#elif defined(IMAGE_BL32)
developer550bf5e2016-07-11 16:05:23 +0800138#define PLATFORM_STACK_SIZE 0x440
139#endif
140
141#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100142#define PLAT_MAX_PWR_LVL U(2) /* MPIDR_AFFLVL2 */
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100143
144#define PLAT_MAX_RET_STATE U(1)
145#define PLAT_MAX_OFF_STATE U(2)
developer550bf5e2016-07-11 16:05:23 +0800146
147#define PLATFORM_CACHE_LINE_SIZE 64
148#define PLATFORM_SYSTEM_COUNT 1
149#define PLATFORM_CLUSTER_COUNT 2
150#define PLATFORM_CLUSTER0_CORE_COUNT 4
151#define PLATFORM_CLUSTER1_CORE_COUNT 4
152#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
153 PLATFORM_CLUSTER0_CORE_COUNT)
154#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
155#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
156 PLATFORM_CLUSTER_COUNT + \
157 PLATFORM_CORE_COUNT)
158
159/*******************************************************************************
160 * Platform memory map related constants
161 ******************************************************************************/
162/* ATF Argument */
163#define ATF_ARG_SIZE (0x800)
164
165/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */
166#define TZRAM_BASE (0x110000)
167#if DEBUG
168#define TZRAM_SIZE (0x1C400)
169#else
170#define TZRAM_SIZE (0x1C400)
171#endif
172#define TZRAM2_BASE 0x00100000
173#define TZRAM2_SIZE 0xDC00
174#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE)
175
176#define RAM_CONSOLE_BASE 0x0012D000
177#define RAM_CONSOLE_SIZE 0x00001000
178/*******************************************************************************
179 * BL31 specific defines.
180 ******************************************************************************/
181/*
182 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
183 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
184 * little space for growth.
185 */
186#define BL31_BASE (TZRAM_BASE + 0x1000)
187#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
188#define BSS1_STACK_LIMIT (TZRAM_BASE + TZRAM_SIZE)
189#define BL31_TZRAM_SIZE (TZRAM_SIZE - ATF_ARG_SIZE)
190
191/*******************************************************************************
192 * Platform specific page table and MMU setup constants
193 ******************************************************************************/
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100194#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
195#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
developer550bf5e2016-07-11 16:05:23 +0800196#define MAX_XLAT_TABLES 7
197#define MAX_MMAP_REGIONS 16
198
199
200/*******************************************************************************
201 * CCI-400 related constants
202 ******************************************************************************/
203#define CCI400_BASE 0x10390000
204#define CCI400_SL_IFACE_CLUSTER0 4
205#define CCI400_SL_IFACE_CLUSTER1 3
206#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
207 CCI400_SL_IFACE_CLUSTER1 : \
208 CCI400_SL_IFACE_CLUSTER0)
209#define CCI_SEC_ACCESS_OFFSET (0x8)
210
211
212/*******************************************************************************
213 * Declarations and constants to access the mailboxes safely. Each mailbox is
214 * aligned on the biggest cache line size in the platform. This is known only
215 * to the platform as it might have a combination of integrated and external
216 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
217 * line at any cache level. They could belong to different cpus/clusters &
218 * get written while being protected by different locks causing corruption of
219 * a valid mailbox address.
220 ******************************************************************************/
221#define CACHE_WRITEBACK_SHIFT 6
222#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
223
224#define BL32_BASE (0x0)
225
226/*
227 * Load address of BL3-3 for this platform port
228 */
229#define LK_SIZE_LIMIT (0x100000)
230#define PLAT_MTK_NS_IMAGE_OFFSET (0x41E00000)
231/* 16KB */
232#define ATF_AEE_BUFFER_SIZE (0x4000)
233#define PAGE_SIZE_2MB_MASK (PAGE_SIZE_2MB - 1)
234#define IS_PAGE_2MB_ALIGNED(addr) (((addr) & PAGE_SIZE_2MB_MASK) == 0)
235#define PAGE_SIZE_2MB (1 << PAGE_SIZE_2MB_SHIFT)
236#define PAGE_SIZE_2MB_SHIFT TWO_MB_SHIFT
237
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100238#endif /* PLATFORM_DEF_H */