| Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef N1SDP_DEF_H |
| 8 | #define N1SDP_DEF_H |
| 9 | |
| 10 | /* Non-secure SRAM MMU mapping */ |
| 11 | #define N1SDP_NS_SRAM_BASE (0x06000000) |
| 12 | #define N1SDP_NS_SRAM_SIZE (0x00010000) |
| 13 | #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ |
| 14 | N1SDP_NS_SRAM_BASE, \ |
| 15 | N1SDP_NS_SRAM_SIZE, \ |
| 16 | MT_DEVICE | MT_RW | MT_SECURE) |
| 17 | |
| 18 | /* SDS memory information defines */ |
| 19 | #define N1SDP_SDS_MEM_INFO_STRUCT_ID 8 |
| 20 | #define N1SDP_SDS_MEM_INFO_OFFSET 0 |
| 21 | #define N1SDP_SDS_MEM_INFO_SIZE 4 |
| 22 | |
| 23 | /* SDS BL33 image information defines */ |
| 24 | #define N1SDP_SDS_BL33_INFO_STRUCT_ID 9 |
| 25 | #define N1SDP_SDS_BL33_INFO_OFFSET 0 |
| 26 | #define N1SDP_SDS_BL33_INFO_SIZE 12 |
| 27 | |
| 28 | /* DMC ERR0CTLR0 registers */ |
| 29 | #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 |
| 30 | #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 |
| 31 | |
| 32 | /* DMC ECC enable bit in ERR0CTLR0 register */ |
| 33 | #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 |
| 34 | |
| 35 | /* Base address of non-secure SRAM where DDR memory size will be filled */ |
| 36 | #define N1SDP_DDR_MEM_INFO_BASE 0x06008000 |
| 37 | |
| 38 | #endif /* N1SDP_DEF_H */ |