Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 1 | /* |
Pritesh Raithatha | 45ea689 | 2017-12-18 23:00:05 -0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Varun Wadekar | 128f46a | 2019-10-24 16:06:12 -0700 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <common/bl_common.h> |
| 9 | #include <mce.h> |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 10 | #include <memctrl_v2.h> |
Varun Wadekar | 128f46a | 2019-10-24 16:06:12 -0700 | [diff] [blame] | 11 | #include <tegra_mc_def.h> |
| 12 | #include <tegra_platform.h> |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 13 | |
| 14 | /******************************************************************************* |
| 15 | * Array to hold stream_id override config register offsets |
| 16 | ******************************************************************************/ |
| 17 | const static uint32_t tegra194_streamid_override_regs[] = { |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 18 | MC_STREAMID_OVERRIDE_CFG_PTCR, |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 19 | MC_STREAMID_OVERRIDE_CFG_HDAR, |
| 20 | MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, |
| 21 | MC_STREAMID_OVERRIDE_CFG_NVENCSRD, |
| 22 | MC_STREAMID_OVERRIDE_CFG_SATAR, |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 23 | MC_STREAMID_OVERRIDE_CFG_MPCORER, |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 24 | MC_STREAMID_OVERRIDE_CFG_NVENCSWR, |
| 25 | MC_STREAMID_OVERRIDE_CFG_HDAW, |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 26 | MC_STREAMID_OVERRIDE_CFG_MPCOREW, |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 27 | MC_STREAMID_OVERRIDE_CFG_SATAW, |
| 28 | MC_STREAMID_OVERRIDE_CFG_ISPRA, |
| 29 | MC_STREAMID_OVERRIDE_CFG_ISPFALR, |
| 30 | MC_STREAMID_OVERRIDE_CFG_ISPWA, |
| 31 | MC_STREAMID_OVERRIDE_CFG_ISPWB, |
| 32 | MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, |
| 33 | MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, |
| 34 | MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, |
| 35 | MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, |
| 36 | MC_STREAMID_OVERRIDE_CFG_TSECSRD, |
| 37 | MC_STREAMID_OVERRIDE_CFG_TSECSWR, |
| 38 | MC_STREAMID_OVERRIDE_CFG_SDMMCRA, |
| 39 | MC_STREAMID_OVERRIDE_CFG_SDMMCR, |
| 40 | MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, |
| 41 | MC_STREAMID_OVERRIDE_CFG_SDMMCWA, |
| 42 | MC_STREAMID_OVERRIDE_CFG_SDMMCW, |
| 43 | MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, |
| 44 | MC_STREAMID_OVERRIDE_CFG_VICSRD, |
| 45 | MC_STREAMID_OVERRIDE_CFG_VICSWR, |
| 46 | MC_STREAMID_OVERRIDE_CFG_VIW, |
| 47 | MC_STREAMID_OVERRIDE_CFG_NVDECSRD, |
| 48 | MC_STREAMID_OVERRIDE_CFG_NVDECSWR, |
| 49 | MC_STREAMID_OVERRIDE_CFG_APER, |
| 50 | MC_STREAMID_OVERRIDE_CFG_APEW, |
| 51 | MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, |
| 52 | MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, |
| 53 | MC_STREAMID_OVERRIDE_CFG_SESRD, |
| 54 | MC_STREAMID_OVERRIDE_CFG_SESWR, |
| 55 | MC_STREAMID_OVERRIDE_CFG_AXIAPR, |
| 56 | MC_STREAMID_OVERRIDE_CFG_AXIAPW, |
| 57 | MC_STREAMID_OVERRIDE_CFG_ETRR, |
| 58 | MC_STREAMID_OVERRIDE_CFG_ETRW, |
| 59 | MC_STREAMID_OVERRIDE_CFG_TSECSRDB, |
| 60 | MC_STREAMID_OVERRIDE_CFG_TSECSWRB, |
| 61 | MC_STREAMID_OVERRIDE_CFG_AXISR, |
| 62 | MC_STREAMID_OVERRIDE_CFG_AXISW, |
| 63 | MC_STREAMID_OVERRIDE_CFG_EQOSR, |
| 64 | MC_STREAMID_OVERRIDE_CFG_EQOSW, |
| 65 | MC_STREAMID_OVERRIDE_CFG_UFSHCR, |
| 66 | MC_STREAMID_OVERRIDE_CFG_UFSHCW, |
| 67 | MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, |
| 68 | MC_STREAMID_OVERRIDE_CFG_BPMPR, |
| 69 | MC_STREAMID_OVERRIDE_CFG_BPMPW, |
| 70 | MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, |
| 71 | MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, |
| 72 | MC_STREAMID_OVERRIDE_CFG_AONR, |
| 73 | MC_STREAMID_OVERRIDE_CFG_AONW, |
| 74 | MC_STREAMID_OVERRIDE_CFG_AONDMAR, |
| 75 | MC_STREAMID_OVERRIDE_CFG_AONDMAW, |
| 76 | MC_STREAMID_OVERRIDE_CFG_SCER, |
| 77 | MC_STREAMID_OVERRIDE_CFG_SCEW, |
| 78 | MC_STREAMID_OVERRIDE_CFG_SCEDMAR, |
| 79 | MC_STREAMID_OVERRIDE_CFG_SCEDMAW, |
| 80 | MC_STREAMID_OVERRIDE_CFG_APEDMAR, |
| 81 | MC_STREAMID_OVERRIDE_CFG_APEDMAW, |
| 82 | MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, |
| 83 | MC_STREAMID_OVERRIDE_CFG_VICSRD1, |
| 84 | MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, |
| 85 | MC_STREAMID_OVERRIDE_CFG_VIFALR, |
| 86 | MC_STREAMID_OVERRIDE_CFG_VIFALW, |
| 87 | MC_STREAMID_OVERRIDE_CFG_DLA0RDA, |
| 88 | MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, |
| 89 | MC_STREAMID_OVERRIDE_CFG_DLA0WRA, |
| 90 | MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, |
| 91 | MC_STREAMID_OVERRIDE_CFG_DLA1RDA, |
| 92 | MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, |
| 93 | MC_STREAMID_OVERRIDE_CFG_DLA1WRA, |
| 94 | MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, |
| 95 | MC_STREAMID_OVERRIDE_CFG_PVA0RDA, |
| 96 | MC_STREAMID_OVERRIDE_CFG_PVA0RDB, |
| 97 | MC_STREAMID_OVERRIDE_CFG_PVA0RDC, |
| 98 | MC_STREAMID_OVERRIDE_CFG_PVA0WRA, |
| 99 | MC_STREAMID_OVERRIDE_CFG_PVA0WRB, |
| 100 | MC_STREAMID_OVERRIDE_CFG_PVA0WRC, |
| 101 | MC_STREAMID_OVERRIDE_CFG_PVA1RDA, |
| 102 | MC_STREAMID_OVERRIDE_CFG_PVA1RDB, |
| 103 | MC_STREAMID_OVERRIDE_CFG_PVA1RDC, |
| 104 | MC_STREAMID_OVERRIDE_CFG_PVA1WRA, |
| 105 | MC_STREAMID_OVERRIDE_CFG_PVA1WRB, |
| 106 | MC_STREAMID_OVERRIDE_CFG_PVA1WRC, |
| 107 | MC_STREAMID_OVERRIDE_CFG_RCER, |
| 108 | MC_STREAMID_OVERRIDE_CFG_RCEW, |
| 109 | MC_STREAMID_OVERRIDE_CFG_RCEDMAR, |
| 110 | MC_STREAMID_OVERRIDE_CFG_RCEDMAW, |
| 111 | MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, |
| 112 | MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, |
| 113 | MC_STREAMID_OVERRIDE_CFG_PCIE0R, |
| 114 | MC_STREAMID_OVERRIDE_CFG_PCIE0W, |
| 115 | MC_STREAMID_OVERRIDE_CFG_PCIE1R, |
| 116 | MC_STREAMID_OVERRIDE_CFG_PCIE1W, |
| 117 | MC_STREAMID_OVERRIDE_CFG_PCIE2AR, |
| 118 | MC_STREAMID_OVERRIDE_CFG_PCIE2AW, |
| 119 | MC_STREAMID_OVERRIDE_CFG_PCIE3R, |
| 120 | MC_STREAMID_OVERRIDE_CFG_PCIE3W, |
| 121 | MC_STREAMID_OVERRIDE_CFG_PCIE4R, |
| 122 | MC_STREAMID_OVERRIDE_CFG_PCIE4W, |
| 123 | MC_STREAMID_OVERRIDE_CFG_PCIE5R, |
| 124 | MC_STREAMID_OVERRIDE_CFG_PCIE5W, |
| 125 | MC_STREAMID_OVERRIDE_CFG_ISPFALW, |
| 126 | MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, |
| 127 | MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, |
| 128 | MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, |
| 129 | MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, |
| 130 | MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, |
| 131 | MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, |
| 132 | MC_STREAMID_OVERRIDE_CFG_PCIE5R1, |
| 133 | MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, |
| 134 | MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, |
| 135 | MC_STREAMID_OVERRIDE_CFG_ISPRA1, |
Pritesh Raithatha | b1914ae | 2018-03-09 10:15:17 +0530 | [diff] [blame] | 136 | MC_STREAMID_OVERRIDE_CFG_PCIE0R1, |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 137 | MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD, |
| 138 | MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1, |
| 139 | MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR, |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 140 | MC_STREAMID_OVERRIDE_CFG_MIU0R, |
| 141 | MC_STREAMID_OVERRIDE_CFG_MIU0W, |
| 142 | MC_STREAMID_OVERRIDE_CFG_MIU1R, |
| 143 | MC_STREAMID_OVERRIDE_CFG_MIU1W, |
| 144 | MC_STREAMID_OVERRIDE_CFG_MIU2R, |
| 145 | MC_STREAMID_OVERRIDE_CFG_MIU2W, |
| 146 | MC_STREAMID_OVERRIDE_CFG_MIU3R, |
Pravin | f74639e | 2018-05-11 15:14:19 +0530 | [diff] [blame] | 147 | MC_STREAMID_OVERRIDE_CFG_MIU3W, |
| 148 | MC_STREAMID_OVERRIDE_CFG_MIU4R, |
| 149 | MC_STREAMID_OVERRIDE_CFG_MIU4W, |
| 150 | MC_STREAMID_OVERRIDE_CFG_MIU5R, |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 151 | MC_STREAMID_OVERRIDE_CFG_MIU5W, |
| 152 | MC_STREAMID_OVERRIDE_CFG_MIU6R, |
| 153 | MC_STREAMID_OVERRIDE_CFG_MIU6W, |
| 154 | MC_STREAMID_OVERRIDE_CFG_MIU7R, |
| 155 | MC_STREAMID_OVERRIDE_CFG_MIU7W |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | /******************************************************************************* |
| 159 | * Array to hold the security configs for stream IDs |
| 160 | ******************************************************************************/ |
| 161 | const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 162 | mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 163 | mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE), |
| 164 | mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 165 | mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 166 | mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE), |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 167 | mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 168 | mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 169 | mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE), |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 170 | mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 171 | mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE), |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 172 | mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 173 | mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 174 | mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 175 | mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE), |
Ajay Gupta | 8162109 | 2017-08-01 15:53:04 -0700 | [diff] [blame] | 176 | mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 177 | mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 178 | mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 179 | mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 180 | mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 181 | mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 182 | mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE), |
| 183 | mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE), |
| 184 | mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE), |
| 185 | mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE), |
| 186 | mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE), |
| 187 | mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE), |
| 188 | mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 189 | mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 190 | mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 191 | mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 192 | mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 193 | mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 194 | mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 195 | mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 196 | mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 197 | mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 198 | mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 199 | mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE), |
| 200 | mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE), |
| 201 | mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE), |
| 202 | mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE), |
| 203 | mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 204 | mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE), |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 205 | mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), |
| 206 | mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 207 | mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE), |
| 208 | mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE), |
| 209 | mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE), |
| 210 | mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE), |
| 211 | mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE), |
| 212 | mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 213 | mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 214 | mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 215 | mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 216 | mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 217 | mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 218 | mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 219 | mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 220 | mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 221 | mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 222 | mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 223 | mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 224 | mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 225 | mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 226 | mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE), |
| 227 | mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 228 | mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 229 | mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE), |
| 230 | mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 231 | mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 232 | mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 233 | mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 234 | mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 235 | mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 236 | mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 237 | mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 238 | mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 239 | mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 240 | mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 241 | mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 242 | mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 243 | mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 244 | mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 245 | mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 246 | mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 247 | mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 248 | mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 249 | mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 250 | mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 251 | mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 252 | mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 253 | mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 254 | mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 255 | mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 256 | mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 257 | mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE), |
| 258 | mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE), |
| 259 | mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE), |
| 260 | mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE), |
| 261 | mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE), |
| 262 | mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE), |
| 263 | mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE), |
| 264 | mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE), |
| 265 | mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE), |
| 266 | mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE), |
| 267 | mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE), |
| 268 | mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE), |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 269 | mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 270 | mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 271 | mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 272 | mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 273 | mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 274 | mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 275 | mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 276 | mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE), |
| 277 | mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 278 | mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 279 | mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 280 | mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE), |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 281 | mc_make_sec_cfg(NVDEC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 282 | mc_make_sec_cfg(NVDEC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE), |
| 283 | mc_make_sec_cfg(NVDEC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE), |
Pritesh Raithatha | 649eb24 | 2018-06-06 11:02:55 +0530 | [diff] [blame] | 284 | mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE), |
| 285 | mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE), |
| 286 | mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE), |
| 287 | mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE), |
| 288 | mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE), |
| 289 | mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE), |
| 290 | mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE), |
Pravin | f74639e | 2018-05-11 15:14:19 +0530 | [diff] [blame] | 291 | mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE), |
| 292 | mc_make_sec_cfg(MIU4R, NON_SECURE, OVERRIDE, DISABLE), |
| 293 | mc_make_sec_cfg(MIU4W, NON_SECURE, OVERRIDE, DISABLE), |
| 294 | mc_make_sec_cfg(MIU5R, NON_SECURE, OVERRIDE, DISABLE), |
Pritesh Raithatha | aa4e3f2 | 2018-08-23 11:47:23 +0530 | [diff] [blame] | 295 | mc_make_sec_cfg(MIU5W, NON_SECURE, OVERRIDE, DISABLE), |
| 296 | mc_make_sec_cfg(MIU6R, NON_SECURE, OVERRIDE, DISABLE), |
| 297 | mc_make_sec_cfg(MIU6W, NON_SECURE, OVERRIDE, DISABLE), |
| 298 | mc_make_sec_cfg(MIU7R, NON_SECURE, OVERRIDE, DISABLE), |
| 299 | mc_make_sec_cfg(MIU7W, NON_SECURE, OVERRIDE, DISABLE) |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 300 | }; |
| 301 | |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 302 | /******************************************************************************* |
| 303 | * Struct to hold the memory controller settings |
| 304 | ******************************************************************************/ |
| 305 | static tegra_mc_settings_t tegra194_mc_settings = { |
| 306 | .streamid_override_cfg = tegra194_streamid_override_regs, |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 307 | .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 308 | .streamid_security_cfg = tegra194_streamid_sec_cfgs, |
Stefan Kristiansson | 1be9a9e | 2018-04-24 16:02:17 +0300 | [diff] [blame] | 309 | .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs) |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 310 | }; |
| 311 | |
| 312 | /******************************************************************************* |
| 313 | * Handler to return the pointer to the memory controller's settings struct |
| 314 | ******************************************************************************/ |
| 315 | tegra_mc_settings_t *tegra_get_mc_settings(void) |
| 316 | { |
| 317 | return &tegra194_mc_settings; |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | /******************************************************************************* |
| 321 | * Handler to program the scratch registers with TZDRAM settings for the |
| 322 | * resume firmware |
| 323 | ******************************************************************************/ |
| 324 | void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) |
| 325 | { |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 326 | uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); |
| 327 | |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 328 | /* |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 329 | * Check TZDRAM carveout register access status. Setup TZDRAM fence |
| 330 | * only if access is enabled. |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 331 | */ |
Steven Kao | b2b4305 | 2017-11-30 11:53:29 +0800 | [diff] [blame] | 332 | if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == |
| 333 | SECURITY_CFG_WRITE_ACCESS_ENABLE) { |
Steven Kao | ee93ed1 | 2017-11-14 19:12:58 +0800 | [diff] [blame] | 334 | |
| 335 | /* |
| 336 | * Setup the Memory controller to allow only secure accesses to |
| 337 | * the TZDRAM carveout |
| 338 | */ |
| 339 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 340 | |
| 341 | tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); |
| 342 | tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); |
| 343 | tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); |
| 344 | |
| 345 | /* |
| 346 | * MCE propagates the security configuration values across the |
| 347 | * CCPLEX. |
| 348 | */ |
| 349 | (void)mce_update_gsc_tzdram(); |
| 350 | } |
| 351 | } |