Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 32 | #include <asm_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 33 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | .globl read_vbar_el1 |
| 35 | .globl read_vbar_el2 |
| 36 | .globl read_vbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | .globl write_vbar_el1 |
| 38 | .globl write_vbar_el2 |
| 39 | .globl write_vbar_el3 |
| 40 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 41 | .globl read_sctlr_el1 |
| 42 | .globl read_sctlr_el2 |
| 43 | .globl read_sctlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 44 | .globl write_sctlr_el1 |
| 45 | .globl write_sctlr_el2 |
| 46 | .globl write_sctlr_el3 |
| 47 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 48 | .globl read_actlr_el1 |
| 49 | .globl read_actlr_el2 |
| 50 | .globl read_actlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 51 | .globl write_actlr_el1 |
| 52 | .globl write_actlr_el2 |
| 53 | .globl write_actlr_el3 |
| 54 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 55 | .globl read_esr_el1 |
| 56 | .globl read_esr_el2 |
| 57 | .globl read_esr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 58 | .globl write_esr_el1 |
| 59 | .globl write_esr_el2 |
| 60 | .globl write_esr_el3 |
| 61 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 62 | .globl read_afsr0_el1 |
| 63 | .globl read_afsr0_el2 |
| 64 | .globl read_afsr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | .globl write_afsr0_el1 |
| 66 | .globl write_afsr0_el2 |
| 67 | .globl write_afsr0_el3 |
| 68 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 69 | .globl read_afsr1_el1 |
| 70 | .globl read_afsr1_el2 |
| 71 | .globl read_afsr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 72 | .globl write_afsr1_el1 |
| 73 | .globl write_afsr1_el2 |
| 74 | .globl write_afsr1_el3 |
| 75 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 76 | .globl read_far_el1 |
| 77 | .globl read_far_el2 |
| 78 | .globl read_far_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 79 | .globl write_far_el1 |
| 80 | .globl write_far_el2 |
| 81 | .globl write_far_el3 |
| 82 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | .globl read_mair_el1 |
| 84 | .globl read_mair_el2 |
| 85 | .globl read_mair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 86 | .globl write_mair_el1 |
| 87 | .globl write_mair_el2 |
| 88 | .globl write_mair_el3 |
| 89 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 90 | .globl read_amair_el1 |
| 91 | .globl read_amair_el2 |
| 92 | .globl read_amair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | .globl write_amair_el1 |
| 94 | .globl write_amair_el2 |
| 95 | .globl write_amair_el3 |
| 96 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 97 | .globl read_rvbar_el1 |
| 98 | .globl read_rvbar_el2 |
| 99 | .globl read_rvbar_el3 |
| 100 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 101 | .globl read_rmr_el1 |
| 102 | .globl read_rmr_el2 |
| 103 | .globl read_rmr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 104 | .globl write_rmr_el1 |
| 105 | .globl write_rmr_el2 |
| 106 | .globl write_rmr_el3 |
| 107 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 108 | .globl read_tcr_el1 |
| 109 | .globl read_tcr_el2 |
| 110 | .globl read_tcr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 111 | .globl write_tcr_el1 |
| 112 | .globl write_tcr_el2 |
| 113 | .globl write_tcr_el3 |
| 114 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | .globl read_cptr_el2 |
| 116 | .globl read_cptr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 117 | .globl write_cptr_el2 |
| 118 | .globl write_cptr_el3 |
| 119 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 120 | .globl read_ttbr0_el1 |
| 121 | .globl read_ttbr0_el2 |
| 122 | .globl read_ttbr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 123 | .globl write_ttbr0_el1 |
| 124 | .globl write_ttbr0_el2 |
| 125 | .globl write_ttbr0_el3 |
| 126 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | .globl read_ttbr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 128 | .globl write_ttbr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 129 | |
| 130 | .globl read_cpacr |
| 131 | .globl write_cpacr |
| 132 | |
| 133 | .globl read_cntfrq |
| 134 | .globl write_cntfrq |
| 135 | |
| 136 | .globl read_cpuectlr |
| 137 | .globl write_cpuectlr |
| 138 | |
| 139 | .globl read_cnthctl_el2 |
| 140 | .globl write_cnthctl_el2 |
| 141 | |
| 142 | .globl read_cntfrq_el0 |
| 143 | .globl write_cntfrq_el0 |
| 144 | |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 145 | .globl read_cntps_ctl_el1 |
| 146 | .globl write_cntps_ctl_el1 |
| 147 | |
| 148 | .globl read_cntps_cval_el1 |
| 149 | .globl write_cntps_cval_el1 |
| 150 | |
| 151 | .globl read_cntps_tval_el1 |
| 152 | .globl write_cntps_tval_el1 |
| 153 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | .globl read_scr |
| 155 | .globl write_scr |
| 156 | |
| 157 | .globl read_hcr |
| 158 | .globl write_hcr |
| 159 | |
| 160 | .globl read_midr |
| 161 | .globl read_mpidr |
| 162 | |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 163 | .globl read_cntpct_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 164 | .globl read_current_el |
| 165 | .globl read_id_pfr1_el1 |
| 166 | .globl read_id_aa64pfr0_el1 |
| 167 | |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 168 | .globl write_tpidr_el3 |
| 169 | .globl read_tpidr_el3 |
| 170 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 171 | #if SUPPORT_VFP |
| 172 | .globl enable_vfp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 173 | #endif |
| 174 | |
| 175 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 176 | func read_current_el |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 177 | mrs x0, CurrentEl |
| 178 | ret |
| 179 | |
| 180 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 181 | func read_id_pfr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 182 | mrs x0, id_pfr1_el1 |
| 183 | ret |
| 184 | |
| 185 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 186 | func read_id_aa64pfr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 187 | mrs x0, id_aa64pfr0_el1 |
| 188 | ret |
| 189 | |
| 190 | |
| 191 | /* ----------------------------------------------------- |
| 192 | * VBAR accessors |
| 193 | * ----------------------------------------------------- |
| 194 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 195 | func read_vbar_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 196 | mrs x0, vbar_el1 |
| 197 | ret |
| 198 | |
| 199 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 200 | func read_vbar_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 201 | mrs x0, vbar_el2 |
| 202 | ret |
| 203 | |
| 204 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 205 | func read_vbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 206 | mrs x0, vbar_el3 |
| 207 | ret |
| 208 | |
| 209 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 210 | func write_vbar_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 211 | msr vbar_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 212 | ret |
| 213 | |
| 214 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 215 | func write_vbar_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 216 | msr vbar_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | ret |
| 218 | |
| 219 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 220 | func write_vbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 221 | msr vbar_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | ret |
| 223 | |
| 224 | |
| 225 | /* ----------------------------------------------------- |
| 226 | * AFSR0 accessors |
| 227 | * ----------------------------------------------------- |
| 228 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 229 | func read_afsr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 230 | mrs x0, afsr0_el1 |
| 231 | ret |
| 232 | |
| 233 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 234 | func read_afsr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 235 | mrs x0, afsr0_el2 |
| 236 | ret |
| 237 | |
| 238 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 239 | func read_afsr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 240 | mrs x0, afsr0_el3 |
| 241 | ret |
| 242 | |
| 243 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 244 | func write_afsr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 245 | msr afsr0_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 246 | ret |
| 247 | |
| 248 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 249 | func write_afsr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 250 | msr afsr0_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 251 | ret |
| 252 | |
| 253 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 254 | func write_afsr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 255 | msr afsr0_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 256 | ret |
| 257 | |
| 258 | |
| 259 | /* ----------------------------------------------------- |
| 260 | * FAR accessors |
| 261 | * ----------------------------------------------------- |
| 262 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 263 | func read_far_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 264 | mrs x0, far_el1 |
| 265 | ret |
| 266 | |
| 267 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 268 | func read_far_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 269 | mrs x0, far_el2 |
| 270 | ret |
| 271 | |
| 272 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 273 | func read_far_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 274 | mrs x0, far_el3 |
| 275 | ret |
| 276 | |
| 277 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 278 | func write_far_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 279 | msr far_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 280 | ret |
| 281 | |
| 282 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 283 | func write_far_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 284 | msr far_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 285 | ret |
| 286 | |
| 287 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 288 | func write_far_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 289 | msr far_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 290 | ret |
| 291 | |
| 292 | |
| 293 | /* ----------------------------------------------------- |
| 294 | * MAIR accessors |
| 295 | * ----------------------------------------------------- |
| 296 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 297 | func read_mair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 298 | mrs x0, mair_el1 |
| 299 | ret |
| 300 | |
| 301 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 302 | func read_mair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 303 | mrs x0, mair_el2 |
| 304 | ret |
| 305 | |
| 306 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 307 | func read_mair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 308 | mrs x0, mair_el3 |
| 309 | ret |
| 310 | |
| 311 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 312 | func write_mair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 313 | msr mair_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 314 | ret |
| 315 | |
| 316 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 317 | func write_mair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 318 | msr mair_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 319 | ret |
| 320 | |
| 321 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 322 | func write_mair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 323 | msr mair_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 324 | ret |
| 325 | |
| 326 | |
| 327 | /* ----------------------------------------------------- |
| 328 | * AMAIR accessors |
| 329 | * ----------------------------------------------------- |
| 330 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 331 | func read_amair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 332 | mrs x0, amair_el1 |
| 333 | ret |
| 334 | |
| 335 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 336 | func read_amair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 337 | mrs x0, amair_el2 |
| 338 | ret |
| 339 | |
| 340 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 341 | func read_amair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 342 | mrs x0, amair_el3 |
| 343 | ret |
| 344 | |
| 345 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 346 | func write_amair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 347 | msr amair_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 348 | ret |
| 349 | |
| 350 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 351 | func write_amair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 352 | msr amair_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 353 | ret |
| 354 | |
| 355 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 356 | func write_amair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 357 | msr amair_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 358 | ret |
| 359 | |
| 360 | |
| 361 | /* ----------------------------------------------------- |
| 362 | * RVBAR accessors |
| 363 | * ----------------------------------------------------- |
| 364 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 365 | func read_rvbar_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 366 | mrs x0, rvbar_el1 |
| 367 | ret |
| 368 | |
| 369 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 370 | func read_rvbar_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 371 | mrs x0, rvbar_el2 |
| 372 | ret |
| 373 | |
| 374 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 375 | func read_rvbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 376 | mrs x0, rvbar_el3 |
| 377 | ret |
| 378 | |
| 379 | |
| 380 | /* ----------------------------------------------------- |
| 381 | * RMR accessors |
| 382 | * ----------------------------------------------------- |
| 383 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 384 | func read_rmr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 385 | mrs x0, rmr_el1 |
| 386 | ret |
| 387 | |
| 388 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 389 | func read_rmr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 390 | mrs x0, rmr_el2 |
| 391 | ret |
| 392 | |
| 393 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 394 | func read_rmr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 395 | mrs x0, rmr_el3 |
| 396 | ret |
| 397 | |
| 398 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 399 | func write_rmr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 400 | msr rmr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 401 | ret |
| 402 | |
| 403 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 404 | func write_rmr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 405 | msr rmr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 406 | ret |
| 407 | |
| 408 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 409 | func write_rmr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 410 | msr rmr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 411 | ret |
| 412 | |
| 413 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 414 | /* ----------------------------------------------------- |
| 415 | * AFSR1 accessors |
| 416 | * ----------------------------------------------------- |
| 417 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 418 | func read_afsr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 419 | mrs x0, afsr1_el1 |
| 420 | ret |
| 421 | |
| 422 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 423 | func read_afsr1_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 424 | mrs x0, afsr1_el2 |
| 425 | ret |
| 426 | |
| 427 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 428 | func read_afsr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 429 | mrs x0, afsr1_el3 |
| 430 | ret |
| 431 | |
| 432 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 433 | func write_afsr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 434 | msr afsr1_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 435 | ret |
| 436 | |
| 437 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 438 | func write_afsr1_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 439 | msr afsr1_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 440 | ret |
| 441 | |
| 442 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 443 | func write_afsr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 444 | msr afsr1_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 445 | ret |
| 446 | |
| 447 | |
| 448 | /* ----------------------------------------------------- |
| 449 | * SCTLR accessors |
| 450 | * ----------------------------------------------------- |
| 451 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 452 | func read_sctlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 453 | mrs x0, sctlr_el1 |
| 454 | ret |
| 455 | |
| 456 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 457 | func read_sctlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 458 | mrs x0, sctlr_el2 |
| 459 | ret |
| 460 | |
| 461 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 462 | func read_sctlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 463 | mrs x0, sctlr_el3 |
| 464 | ret |
| 465 | |
| 466 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 467 | func write_sctlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 468 | msr sctlr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 469 | ret |
| 470 | |
| 471 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 472 | func write_sctlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 473 | msr sctlr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 474 | ret |
| 475 | |
| 476 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 477 | func write_sctlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 478 | msr sctlr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 479 | ret |
| 480 | |
| 481 | |
| 482 | /* ----------------------------------------------------- |
| 483 | * ACTLR accessors |
| 484 | * ----------------------------------------------------- |
| 485 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 486 | func read_actlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 487 | mrs x0, actlr_el1 |
| 488 | ret |
| 489 | |
| 490 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 491 | func read_actlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 492 | mrs x0, actlr_el2 |
| 493 | ret |
| 494 | |
| 495 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 496 | func read_actlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 497 | mrs x0, actlr_el3 |
| 498 | ret |
| 499 | |
| 500 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 501 | func write_actlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 502 | msr actlr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 503 | ret |
| 504 | |
| 505 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 506 | func write_actlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 507 | msr actlr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 508 | ret |
| 509 | |
| 510 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 511 | func write_actlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 512 | msr actlr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 513 | ret |
| 514 | |
| 515 | |
| 516 | /* ----------------------------------------------------- |
| 517 | * ESR accessors |
| 518 | * ----------------------------------------------------- |
| 519 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 520 | func read_esr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 521 | mrs x0, esr_el1 |
| 522 | ret |
| 523 | |
| 524 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 525 | func read_esr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 526 | mrs x0, esr_el2 |
| 527 | ret |
| 528 | |
| 529 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 530 | func read_esr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 531 | mrs x0, esr_el3 |
| 532 | ret |
| 533 | |
| 534 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 535 | func write_esr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 536 | msr esr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 537 | ret |
| 538 | |
| 539 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 540 | func write_esr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 541 | msr esr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 542 | ret |
| 543 | |
| 544 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 545 | func write_esr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 546 | msr esr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 547 | ret |
| 548 | |
| 549 | |
| 550 | /* ----------------------------------------------------- |
| 551 | * TCR accessors |
| 552 | * ----------------------------------------------------- |
| 553 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 554 | func read_tcr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 555 | mrs x0, tcr_el1 |
| 556 | ret |
| 557 | |
| 558 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 559 | func read_tcr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 560 | mrs x0, tcr_el2 |
| 561 | ret |
| 562 | |
| 563 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 564 | func read_tcr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 565 | mrs x0, tcr_el3 |
| 566 | ret |
| 567 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 568 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 569 | func write_tcr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 570 | msr tcr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 571 | ret |
| 572 | |
| 573 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 574 | func write_tcr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 575 | msr tcr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 576 | ret |
| 577 | |
| 578 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 579 | func write_tcr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 580 | msr tcr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 581 | ret |
| 582 | |
| 583 | |
| 584 | /* ----------------------------------------------------- |
| 585 | * CPTR accessors |
| 586 | * ----------------------------------------------------- |
| 587 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 588 | func read_cptr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 589 | mrs x0, cptr_el2 |
| 590 | ret |
| 591 | |
| 592 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 593 | func read_cptr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 594 | mrs x0, cptr_el3 |
| 595 | ret |
| 596 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 597 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 598 | func write_cptr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 599 | msr cptr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 600 | ret |
| 601 | |
| 602 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 603 | func write_cptr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 604 | msr cptr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 605 | ret |
| 606 | |
| 607 | |
| 608 | /* ----------------------------------------------------- |
| 609 | * TTBR0 accessors |
| 610 | * ----------------------------------------------------- |
| 611 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 612 | func read_ttbr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 613 | mrs x0, ttbr0_el1 |
| 614 | ret |
| 615 | |
| 616 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 617 | func read_ttbr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 618 | mrs x0, ttbr0_el2 |
| 619 | ret |
| 620 | |
| 621 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 622 | func read_ttbr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 623 | mrs x0, ttbr0_el3 |
| 624 | ret |
| 625 | |
| 626 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 627 | func write_ttbr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 628 | msr ttbr0_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 629 | ret |
| 630 | |
| 631 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 632 | func write_ttbr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 633 | msr ttbr0_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 634 | ret |
| 635 | |
| 636 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 637 | func write_ttbr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 638 | msr ttbr0_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 639 | ret |
| 640 | |
| 641 | |
| 642 | /* ----------------------------------------------------- |
| 643 | * TTBR1 accessors |
| 644 | * ----------------------------------------------------- |
| 645 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 646 | func read_ttbr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 647 | mrs x0, ttbr1_el1 |
| 648 | ret |
| 649 | |
| 650 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 651 | func write_ttbr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 652 | msr ttbr1_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 653 | ret |
| 654 | |
| 655 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 656 | func read_hcr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 657 | mrs x0, hcr_el2 |
| 658 | ret |
| 659 | |
| 660 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 661 | func write_hcr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 662 | msr hcr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 663 | ret |
| 664 | |
| 665 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 666 | func read_cpacr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 667 | mrs x0, cpacr_el1 |
| 668 | ret |
| 669 | |
| 670 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 671 | func write_cpacr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 672 | msr cpacr_el1, x0 |
| 673 | ret |
| 674 | |
| 675 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 676 | func read_cntfrq_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 677 | mrs x0, cntfrq_el0 |
| 678 | ret |
| 679 | |
| 680 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 681 | func write_cntfrq_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 682 | msr cntfrq_el0, x0 |
| 683 | ret |
| 684 | |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 685 | func read_cntps_ctl_el1 |
| 686 | mrs x0, cntps_ctl_el1 |
| 687 | ret |
| 688 | |
| 689 | func write_cntps_ctl_el1 |
| 690 | msr cntps_ctl_el1, x0 |
| 691 | ret |
| 692 | |
| 693 | func read_cntps_cval_el1 |
| 694 | mrs x0, cntps_cval_el1 |
| 695 | ret |
| 696 | |
| 697 | func write_cntps_cval_el1 |
| 698 | msr cntps_cval_el1, x0 |
| 699 | ret |
| 700 | |
| 701 | func read_cntps_tval_el1 |
| 702 | mrs x0, cntps_tval_el1 |
| 703 | ret |
| 704 | |
| 705 | func write_cntps_tval_el1 |
| 706 | msr cntps_tval_el1, x0 |
| 707 | ret |
| 708 | |
| 709 | func read_cntpct_el0 |
| 710 | mrs x0, cntpct_el0 |
| 711 | ret |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 712 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 713 | func read_cpuectlr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 714 | mrs x0, CPUECTLR_EL1 |
| 715 | ret |
| 716 | |
| 717 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 718 | func write_cpuectlr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 719 | msr CPUECTLR_EL1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 720 | ret |
| 721 | |
| 722 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 723 | func read_cnthctl_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 724 | mrs x0, cnthctl_el2 |
| 725 | ret |
| 726 | |
| 727 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 728 | func write_cnthctl_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 729 | msr cnthctl_el2, x0 |
| 730 | ret |
| 731 | |
| 732 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 733 | func read_cntfrq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 734 | mrs x0, cntfrq_el0 |
| 735 | ret |
| 736 | |
| 737 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 738 | func write_cntfrq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 739 | msr cntfrq_el0, x0 |
| 740 | ret |
| 741 | |
| 742 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 743 | func write_scr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 744 | msr scr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 745 | ret |
| 746 | |
| 747 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 748 | func read_scr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 749 | mrs x0, scr_el3 |
| 750 | ret |
| 751 | |
| 752 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 753 | func read_midr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 754 | mrs x0, midr_el1 |
| 755 | ret |
| 756 | |
| 757 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 758 | func read_mpidr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 759 | mrs x0, mpidr_el1 |
| 760 | ret |
| 761 | |
Soby Mathew | 5e5c207 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 762 | func write_tpidr_el3 |
| 763 | msr tpidr_el3, x0 |
| 764 | ret |
| 765 | |
| 766 | func read_tpidr_el3 |
| 767 | mrs x0, tpidr_el3 |
| 768 | ret |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 769 | |
| 770 | #if SUPPORT_VFP |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 771 | func enable_vfp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 772 | mrs x0, cpacr_el1 |
| 773 | orr x0, x0, #CPACR_VFP_BITS |
| 774 | msr cpacr_el1, x0 |
| 775 | mrs x0, cptr_el3 |
| 776 | mov x1, #AARCH64_CPTR_TFP |
| 777 | bic x0, x0, x1 |
| 778 | msr cptr_el3, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 779 | isb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 780 | ret |
| 781 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 782 | #endif |