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David Wang805c2c72016-11-09 16:29:02 +00001/*
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +00002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
David Wang805c2c72016-11-09 16:29:02 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CORTEX_A55_H
8#define CORTEX_A55_H
David Wang805c2c72016-11-09 16:29:02 +00009
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000010#include <lib/utils_def.h>
11
David Wang805c2c72016-11-09 16:29:02 +000012/* Cortex-A55 MIDR for revision 0 */
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000013#define CORTEX_A55_MIDR U(0x410fd050)
David Wang805c2c72016-11-09 16:29:02 +000014
15/*******************************************************************************
16 * CPU Extended Control register specific definitions.
17 ******************************************************************************/
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000018#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
David Wang805c2c72016-11-09 16:29:02 +000019#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
20
Ambroise Vincent7927fa02019-02-21 16:20:43 +000021/*******************************************************************************
22 * CPU Auxiliary Control register specific definitions.
23 ******************************************************************************/
24#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0
25
26#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31)
27
David Wang805c2c72016-11-09 16:29:02 +000028/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000029#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
David Wang805c2c72016-11-09 16:29:02 +000030
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000031#endif /* CORTEX_A55_H */