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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Sona Mathew7fe03522022-11-18 18:05:38 -06002 * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef ARCH_H
8#define ARCH_H
Soby Mathewc6820d12016-05-09 17:49:55 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Isla Mitchell02c63072017-07-21 14:44:36 +010011
Soby Mathewc6820d12016-05-09 17:49:55 +010012/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(24)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
Sona Mathew7fe03522022-11-18 18:05:38 -060019#define MIDR_VAR_MASK U(0xf)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010020#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
Sona Mathew7fe03522022-11-18 18:05:38 -060022#define MIDR_REV_MASK U(0xf)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010023#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(4)
Soby Mathewc6820d12016-05-09 17:49:55 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010029#define MPIDR_MT_MASK (U(1) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
31#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010032#define MPIDR_AFFINITY_BITS U(8)
33#define MPIDR_AFFLVL_MASK U(0xff)
34#define MPIDR_AFFLVL_SHIFT U(3)
35#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000038#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010039#define MPIDR_AFFINITY_MASK U(0x00ffffff)
40#define MPIDR_AFFLVL0 U(0)
41#define MPIDR_AFFLVL1 U(1)
42#define MPIDR_AFFLVL2 U(2)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000043#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Soby Mathewc6820d12016-05-09 17:49:55 +010044
45#define MPIDR_AFFLVL0_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
47#define MPIDR_AFFLVL1_VAL(mpidr) \
48 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
49#define MPIDR_AFFLVL2_VAL(mpidr) \
50 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010051#define MPIDR_AFFLVL3_VAL(mpidr) U(0)
Soby Mathewc6820d12016-05-09 17:49:55 +010052
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000053#define MPIDR_AFF_ID(mpid, n) \
54 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
55
56#define MPID_MASK (MPIDR_MT_MASK |\
57 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
58 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
59 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
60
61/*
62 * An invalid MPID. This value can be used by functions that return an MPID to
63 * indicate an error.
64 */
65#define INVALID_MPID U(0xFFFFFFFF)
66
Soby Mathewc6820d12016-05-09 17:49:55 +010067/*
68 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
69 * add one while using this macro to define array sizes.
70 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010071#define MPIDR_MAX_AFFLVL U(2)
Soby Mathewc6820d12016-05-09 17:49:55 +010072
73/* Data Cache set/way op type defines */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010074#define DC_OP_ISW U(0x0)
75#define DC_OP_CISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000076#if ERRATA_A53_827319
77#define DC_OP_CSW DC_OP_CISW
78#else
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010079#define DC_OP_CSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000080#endif
Soby Mathewc6820d12016-05-09 17:49:55 +010081
82/*******************************************************************************
83 * Generic timer memory mapped registers & offsets
84 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010085#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +020086/* Counter Count Value Lower register */
87#define CNTCVL_OFF U(0x008)
88/* Counter Count Value Upper register */
89#define CNTCVU_OFF U(0x00C)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010090#define CNTFID_OFF U(0x020)
Soby Mathewc6820d12016-05-09 17:49:55 +010091
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010092#define CNTCR_EN (U(1) << 0)
93#define CNTCR_HDBG (U(1) << 1)
Soby Mathewc6820d12016-05-09 17:49:55 +010094#define CNTCR_FCREQ(x) ((x) << 8)
95
96/*******************************************************************************
97 * System register bit definitions
98 ******************************************************************************/
99/* CLIDR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100100#define LOUIS_SHIFT U(21)
101#define LOC_SHIFT U(24)
102#define CLIDR_FIELD_WIDTH U(3)
Soby Mathewc6820d12016-05-09 17:49:55 +0100103
104/* CSSELR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100105#define LEVEL_SHIFT U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100106
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000107/* ID_DFR0 definitions */
108#define ID_DFR0_PERFMON_SHIFT U(24)
109#define ID_DFR0_PERFMON_MASK U(0xf)
110#define ID_DFR0_PERFMON_PMUV3 U(3)
111#define ID_DFR0_PERFMON_PMUV3P5 U(6)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100112#define ID_DFR0_COPTRC_SHIFT U(12)
113#define ID_DFR0_COPTRC_MASK U(0xf)
114#define ID_DFR0_COPTRC_SUPPORTED U(1)
115#define ID_DFR0_COPTRC_LENGTH U(4)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100116#define ID_DFR0_TRACEFILT_SHIFT U(28)
117#define ID_DFR0_TRACEFILT_MASK U(0xf)
118#define ID_DFR0_TRACEFILT_SUPPORTED U(1)
119#define ID_DFR0_TRACEFILT_LENGTH U(4)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100120
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000121/* ID_DFR1_EL1 definitions */
122#define ID_DFR1_MTPMU_SHIFT U(0)
123#define ID_DFR1_MTPMU_MASK U(0xf)
124#define ID_DFR1_MTPMU_SUPPORTED U(1)
125
Andre Przywara54d57912023-05-23 13:56:55 +0100126/* ID_MMFR3 definitions */
127#define ID_MMFR3_PAN_SHIFT U(16)
128#define ID_MMFR3_PAN_MASK U(0xf)
129
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000130/* ID_MMFR4 definitions */
131#define ID_MMFR4_CNP_SHIFT U(12)
132#define ID_MMFR4_CNP_LENGTH U(4)
133#define ID_MMFR4_CNP_MASK U(0xf)
134
johpow0174b7e442021-12-01 13:18:30 -0600135#define ID_MMFR4_CCIDX_SHIFT U(24)
136#define ID_MMFR4_CCIDX_LENGTH U(4)
137#define ID_MMFR4_CCIDX_MASK U(0xf)
138
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000139/* ID_PFR0 definitions */
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100140#define ID_PFR0_AMU_SHIFT U(20)
141#define ID_PFR0_AMU_LENGTH U(4)
142#define ID_PFR0_AMU_MASK U(0xf)
johpow01fa59c6f2020-10-02 13:41:11 -0500143#define ID_PFR0_AMU_NOT_SUPPORTED U(0x0)
144#define ID_PFR0_AMU_V1 U(0x1)
145#define ID_PFR0_AMU_V1P1 U(0x2)
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100146
Sathees Balya0911df12018-12-06 13:33:24 +0000147#define ID_PFR0_DIT_SHIFT U(24)
148#define ID_PFR0_DIT_LENGTH U(4)
149#define ID_PFR0_DIT_MASK U(0xf)
150#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
151
Soby Mathewc6820d12016-05-09 17:49:55 +0100152/* ID_PFR1 definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100153#define ID_PFR1_VIRTEXT_SHIFT U(12)
154#define ID_PFR1_VIRTEXT_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100155#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
156 & ID_PFR1_VIRTEXT_MASK)
Antonio Nino Diazd29d21e2019-02-06 09:23:04 +0000157#define ID_PFR1_GENTIMER_SHIFT U(16)
158#define ID_PFR1_GENTIMER_MASK U(0xf)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100159#define ID_PFR1_GIC_SHIFT U(28)
160#define ID_PFR1_GIC_MASK U(0xf)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000161#define ID_PFR1_SEC_SHIFT U(4)
162#define ID_PFR1_SEC_MASK U(0xf)
163#define ID_PFR1_ELx_ENABLED U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100164
165/* SCTLR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100166#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
167 (U(1) << 3))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100168#if ARM_ARCH_MAJOR == 7
169#define SCTLR_RES1 SCTLR_RES1_DEF
170#else
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100171#define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100172#endif
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100173#define SCTLR_M_BIT (U(1) << 0)
174#define SCTLR_A_BIT (U(1) << 1)
175#define SCTLR_C_BIT (U(1) << 2)
176#define SCTLR_CP15BEN_BIT (U(1) << 5)
177#define SCTLR_ITD_BIT (U(1) << 7)
178#define SCTLR_Z_BIT (U(1) << 11)
179#define SCTLR_I_BIT (U(1) << 12)
180#define SCTLR_V_BIT (U(1) << 13)
181#define SCTLR_RR_BIT (U(1) << 14)
182#define SCTLR_NTWI_BIT (U(1) << 16)
183#define SCTLR_NTWE_BIT (U(1) << 18)
184#define SCTLR_WXN_BIT (U(1) << 19)
185#define SCTLR_UWXN_BIT (U(1) << 20)
186#define SCTLR_EE_BIT (U(1) << 25)
187#define SCTLR_TRE_BIT (U(1) << 28)
188#define SCTLR_AFE_BIT (U(1) << 29)
189#define SCTLR_TE_BIT (U(1) << 30)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000190#define SCTLR_DSSBS_BIT (U(1) << 31)
johpow0174b7e442021-12-01 13:18:30 -0600191#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
David Cunadofee86532017-04-13 22:38:29 +0100192 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
Soby Mathewc6820d12016-05-09 17:49:55 +0100193
dp-arm595d0d52017-02-08 11:51:50 +0000194/* SDCR definitions */
195#define SDCR_SPD(x) ((x) << 14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100196#define SDCR_SPD_LEGACY U(0x0)
197#define SDCR_SPD_DISABLE U(0x2)
198#define SDCR_SPD_ENABLE U(0x3)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000199#define SDCR_SCCD_BIT (U(1) << 23)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100200#define SDCR_TTRF_BIT (U(1) << 19)
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100201#define SDCR_SPME_BIT (U(1) << 17)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100202#define SDCR_RESET_VAL U(0x0)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000203#define SDCR_MTPME_BIT (U(1) << 28)
dp-arm595d0d52017-02-08 11:51:50 +0000204
Soby Mathewc6820d12016-05-09 17:49:55 +0100205/* HSCTLR definitions */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000206#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100207 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
208 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
209
210#define HSCTLR_M_BIT (U(1) << 0)
211#define HSCTLR_A_BIT (U(1) << 1)
212#define HSCTLR_C_BIT (U(1) << 2)
213#define HSCTLR_CP15BEN_BIT (U(1) << 5)
214#define HSCTLR_ITD_BIT (U(1) << 7)
215#define HSCTLR_SED_BIT (U(1) << 8)
216#define HSCTLR_I_BIT (U(1) << 12)
217#define HSCTLR_WXN_BIT (U(1) << 19)
218#define HSCTLR_EE_BIT (U(1) << 25)
219#define HSCTLR_TE_BIT (U(1) << 30)
Soby Mathewc6820d12016-05-09 17:49:55 +0100220
221/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100222#define CPACR_FPEN(x) ((x) << 20)
Jimmy Brissoned202072020-08-04 16:18:52 -0500223#define CPACR_FP_TRAP_PL0 UL(0x1)
224#define CPACR_FP_TRAP_ALL UL(0x2)
225#define CPACR_FP_TRAP_NONE UL(0x3)
Soby Mathewc6820d12016-05-09 17:49:55 +0100226
227/* SCR definitions */
Jimmy Brissoned202072020-08-04 16:18:52 -0500228#define SCR_TWE_BIT (UL(1) << 13)
229#define SCR_TWI_BIT (UL(1) << 12)
230#define SCR_SIF_BIT (UL(1) << 9)
231#define SCR_HCE_BIT (UL(1) << 8)
232#define SCR_SCD_BIT (UL(1) << 7)
233#define SCR_NET_BIT (UL(1) << 6)
234#define SCR_AW_BIT (UL(1) << 5)
235#define SCR_FW_BIT (UL(1) << 4)
236#define SCR_EA_BIT (UL(1) << 3)
237#define SCR_FIQ_BIT (UL(1) << 2)
238#define SCR_IRQ_BIT (UL(1) << 1)
239#define SCR_NS_BIT (UL(1) << 0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100240#define SCR_VALID_BIT_MASK U(0x33ff)
241#define SCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100242
243#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
244
245/* HCR definitions */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000246#define HCR_TGE_BIT (U(1) << 27)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100247#define HCR_AMO_BIT (U(1) << 5)
248#define HCR_IMO_BIT (U(1) << 4)
249#define HCR_FMO_BIT (U(1) << 3)
250#define HCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100251
252/* CNTHCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100253#define CNTHCTL_RESET_VAL U(0x0)
254#define PL1PCEN_BIT (U(1) << 1)
255#define PL1PCTEN_BIT (U(1) << 0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100256
257/* CNTKCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100258#define PL0PTEN_BIT (U(1) << 9)
259#define PL0VTEN_BIT (U(1) << 8)
260#define PL0PCTEN_BIT (U(1) << 0)
261#define PL0VCTEN_BIT (U(1) << 1)
262#define EVNTEN_BIT (U(1) << 2)
263#define EVNTDIR_BIT (U(1) << 3)
264#define EVNTI_SHIFT U(4)
265#define EVNTI_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100266
267/* HCPTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100268#define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
269#define TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100270#define TAM_SHIFT U(30)
271#define TAM_BIT (U(1) << TAM_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100272#define TTA_BIT (U(1) << 20)
Sandrine Bailleux6061c452018-07-13 10:04:12 +0200273#define TCP11_BIT (U(1) << 11)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100274#define TCP10_BIT (U(1) << 10)
David Cunadofee86532017-04-13 22:38:29 +0100275#define HCPTR_RESET_VAL HCPTR_RES1
276
Elyes Haouas2be03c02023-02-13 09:14:48 +0100277/* VTTBR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100278#define VTTBR_RESET_VAL ULL(0x0)
279#define VTTBR_VMID_MASK ULL(0xff)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100280#define VTTBR_VMID_SHIFT U(48)
281#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
282#define VTTBR_BADDR_SHIFT U(0)
David Cunadofee86532017-04-13 22:38:29 +0100283
284/* HDCR definitions */
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000285#define HDCR_MTPME_BIT (U(1) << 28)
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100286#define HDCR_HLP_BIT (U(1) << 26)
287#define HDCR_HPME_BIT (U(1) << 7)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100288#define HDCR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100289
290/* HSTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100291#define HSTR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100292
293/* CNTHP_CTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100294#define CNTHP_CTL_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100295
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000296/* NSACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100297#define NSASEDIS_BIT (U(1) << 15)
298#define NSTRCDIS_BIT (U(1) << 20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100299#define NSACR_CP11_BIT (U(1) << 11)
300#define NSACR_CP10_BIT (U(1) << 10)
301#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
David Cunadofee86532017-04-13 22:38:29 +0100302#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100303#define NSACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100304
305/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100306#define ASEDIS_BIT (U(1) << 31)
307#define TRCDIS_BIT (U(1) << 28)
308#define CPACR_CP11_SHIFT U(22)
309#define CPACR_CP10_SHIFT U(20)
310#define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
311 (U(0x3) << CPACR_CP10_SHIFT))
johpow0174b7e442021-12-01 13:18:30 -0600312#define CPACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100313
314/* FPEXC definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100315#define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
316#define FPEXC_EN_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100317#define FPEXC_RESET_VAL FPEXC_RES1
Soby Mathewc6820d12016-05-09 17:49:55 +0100318
319/* SPSR/CPSR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100320#define SPSR_FIQ_BIT (U(1) << 0)
321#define SPSR_IRQ_BIT (U(1) << 1)
322#define SPSR_ABT_BIT (U(1) << 2)
323#define SPSR_AIF_SHIFT U(6)
324#define SPSR_AIF_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100325
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100326#define SPSR_E_SHIFT U(9)
327#define SPSR_E_MASK U(0x1)
328#define SPSR_E_LITTLE U(0)
329#define SPSR_E_BIG U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100330
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100331#define SPSR_T_SHIFT U(5)
332#define SPSR_T_MASK U(0x1)
333#define SPSR_T_ARM U(0)
334#define SPSR_T_THUMB U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100335
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100336#define SPSR_MODE_SHIFT U(0)
337#define SPSR_MODE_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100338
John Tsichritzis55534172019-07-23 11:12:41 +0100339#define SPSR_SSBS_BIT BIT_32(23)
340
Soby Mathewc6820d12016-05-09 17:49:55 +0100341#define DISABLE_ALL_EXCEPTIONS \
342 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
343
Sathees Balya0911df12018-12-06 13:33:24 +0000344#define CPSR_DIT_BIT (U(1) << 21)
Soby Mathewc6820d12016-05-09 17:49:55 +0100345/*
346 * TTBCR definitions
347 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100348#define TTBCR_EAE_BIT (U(1) << 31)
Soby Mathewc6820d12016-05-09 17:49:55 +0100349
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100350#define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
351#define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
352#define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
Soby Mathewc6820d12016-05-09 17:49:55 +0100353
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100354#define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
355#define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
356#define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
357#define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
Soby Mathewc6820d12016-05-09 17:49:55 +0100358
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100359#define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
360#define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
361#define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
362#define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +0100363
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100364#define TTBCR_EPD1_BIT (U(1) << 23)
365#define TTBCR_A1_BIT (U(1) << 22)
Soby Mathewc6820d12016-05-09 17:49:55 +0100366
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100367#define TTBCR_T1SZ_SHIFT U(16)
368#define TTBCR_T1SZ_MASK U(0x7)
369#define TTBCR_TxSZ_MIN U(0)
370#define TTBCR_TxSZ_MAX U(7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100371
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100372#define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
373#define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
374#define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
Soby Mathewc6820d12016-05-09 17:49:55 +0100375
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100376#define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
377#define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
378#define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
379#define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
Soby Mathewc6820d12016-05-09 17:49:55 +0100380
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100381#define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
382#define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
383#define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
384#define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
Soby Mathewc6820d12016-05-09 17:49:55 +0100385
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100386#define TTBCR_EPD0_BIT (U(1) << 7)
387#define TTBCR_T0SZ_SHIFT U(0)
388#define TTBCR_T0SZ_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100389
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100390/*
391 * HTCR definitions
392 */
393#define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
394
395#define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
396#define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
397#define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
398
399#define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
400#define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
401#define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
402#define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
403
404#define HTCR_RGN0_INNER_NC (U(0x0) << 8)
405#define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
406#define HTCR_RGN0_INNER_WT (U(0x2) << 8)
407#define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
408
409#define HTCR_T0SZ_SHIFT U(0)
410#define HTCR_T0SZ_MASK U(0x7)
411
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100412#define MODE_RW_SHIFT U(0x4)
413#define MODE_RW_MASK U(0x1)
414#define MODE_RW_32 U(0x1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100415
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100416#define MODE32_SHIFT U(0)
417#define MODE32_MASK U(0x1f)
418#define MODE32_usr U(0x10)
419#define MODE32_fiq U(0x11)
420#define MODE32_irq U(0x12)
421#define MODE32_svc U(0x13)
422#define MODE32_mon U(0x16)
423#define MODE32_abt U(0x17)
424#define MODE32_hyp U(0x1a)
425#define MODE32_und U(0x1b)
426#define MODE32_sys U(0x1f)
Soby Mathewc6820d12016-05-09 17:49:55 +0100427
428#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
429
John Powella5c66362020-03-20 14:21:05 -0500430#define SPSR_MODE32(mode, isa, endian, aif) \
431( \
432 ( \
433 (MODE_RW_32 << MODE_RW_SHIFT) | \
434 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
435 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
436 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
437 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \
438 ) & \
439 (~(SPSR_SSBS_BIT)) \
440)
Soby Mathewc6820d12016-05-09 17:49:55 +0100441
442/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100443 * TTBR definitions
444 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100445#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100446
447/*
Soby Mathewc6820d12016-05-09 17:49:55 +0100448 * CTR definitions
449 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100450#define CTR_CWG_SHIFT U(24)
451#define CTR_CWG_MASK U(0xf)
452#define CTR_ERG_SHIFT U(20)
453#define CTR_ERG_MASK U(0xf)
454#define CTR_DMINLINE_SHIFT U(16)
455#define CTR_DMINLINE_WIDTH U(4)
456#define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
457#define CTR_L1IP_SHIFT U(14)
458#define CTR_L1IP_MASK U(0x3)
459#define CTR_IMINLINE_SHIFT U(0)
460#define CTR_IMINLINE_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100461
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100462#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Soby Mathewc6820d12016-05-09 17:49:55 +0100463
David Cunado5f55e282016-10-31 17:37:34 +0000464/* PMCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100465#define PMCR_N_SHIFT U(11)
466#define PMCR_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000467#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100468#define PMCR_LP_BIT (U(1) << 7)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100469#define PMCR_LC_BIT (U(1) << 6)
470#define PMCR_DP_BIT (U(1) << 5)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000471#define PMCR_X_BIT (U(1) << 4)
472#define PMCR_C_BIT (U(1) << 2)
473#define PMCR_P_BIT (U(1) << 1)
474#define PMCR_E_BIT (U(1) << 0)
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100475#define PMCR_RESET_VAL U(0x0)
David Cunado5f55e282016-10-31 17:37:34 +0000476
Soby Mathewc6820d12016-05-09 17:49:55 +0100477/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000478 * Definitions of register offsets, fields and macros for CPU system
479 * instructions.
480 ******************************************************************************/
481
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100482#define TLBI_ADDR_SHIFT U(0)
483#define TLBI_ADDR_MASK U(0xFFFFF000)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000484#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
485
486/*******************************************************************************
Soby Mathewc6820d12016-05-09 17:49:55 +0100487 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
488 * system level implementation of the Generic Timer.
489 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100490#define CNTCTLBASE_CNTFRQ U(0x0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100491#define CNTNSAR U(0x4)
Soby Mathewc6820d12016-05-09 17:49:55 +0100492#define CNTNSAR_NS_SHIFT(x) (x)
493
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100494#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
495#define CNTACR_RPCT_SHIFT U(0x0)
496#define CNTACR_RVCT_SHIFT U(0x1)
497#define CNTACR_RFRQ_SHIFT U(0x2)
498#define CNTACR_RVOFF_SHIFT U(0x3)
499#define CNTACR_RWVT_SHIFT U(0x4)
500#define CNTACR_RWPT_SHIFT U(0x5)
Soby Mathewc6820d12016-05-09 17:49:55 +0100501
Soby Mathew2d9f7952018-06-11 16:21:30 +0100502/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000503 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100504 * system level implementation of the Generic Timer.
505 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000506/* Physical Count register. */
507#define CNTPCT_LO U(0x0)
508/* Counter Frequency register. */
509#define CNTBASEN_CNTFRQ U(0x10)
510/* Physical Timer CompareValue register. */
511#define CNTP_CVAL_LO U(0x20)
512/* Physical Timer Control register. */
513#define CNTP_CTL U(0x2c)
514
515/* Physical timer control register bit fields shifts and masks */
johpow0174b7e442021-12-01 13:18:30 -0600516#define CNTP_CTL_ENABLE_SHIFT 0
517#define CNTP_CTL_IMASK_SHIFT 1
518#define CNTP_CTL_ISTATUS_SHIFT 2
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000519
johpow0174b7e442021-12-01 13:18:30 -0600520#define CNTP_CTL_ENABLE_MASK U(1)
521#define CNTP_CTL_IMASK_MASK U(1)
522#define CNTP_CTL_ISTATUS_MASK U(1)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100523
Soby Mathewc6820d12016-05-09 17:49:55 +0100524/* MAIR macros */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000525#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
526#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
Soby Mathewc6820d12016-05-09 17:49:55 +0100527
528/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
529#define SCR p15, 0, c1, c1, 0
530#define SCTLR p15, 0, c1, c0, 0
Etienne Carriere70a004b2017-11-05 22:56:03 +0100531#define ACTLR p15, 0, c1, c0, 1
dp-arm595d0d52017-02-08 11:51:50 +0000532#define SDCR p15, 0, c1, c3, 1
Soby Mathewc6820d12016-05-09 17:49:55 +0100533#define MPIDR p15, 0, c0, c0, 5
534#define MIDR p15, 0, c0, c0, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000535#define HVBAR p15, 4, c12, c0, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100536#define VBAR p15, 0, c12, c0, 0
537#define MVBAR p15, 0, c12, c0, 1
538#define NSACR p15, 0, c1, c1, 2
539#define CPACR p15, 0, c1, c0, 2
540#define DCCIMVAC p15, 0, c7, c14, 1
541#define DCCMVAC p15, 0, c7, c10, 1
542#define DCIMVAC p15, 0, c7, c6, 1
543#define DCCISW p15, 0, c7, c14, 2
544#define DCCSW p15, 0, c7, c10, 2
545#define DCISW p15, 0, c7, c6, 2
546#define CTR p15, 0, c0, c0, 1
547#define CNTFRQ p15, 0, c14, c0, 0
Andre Przywara54d57912023-05-23 13:56:55 +0100548#define ID_MMFR3 p15, 0, c0, c1, 7
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000549#define ID_MMFR4 p15, 0, c0, c2, 6
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100550#define ID_DFR0 p15, 0, c0, c1, 2
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000551#define ID_DFR1 p15, 0, c0, c3, 5
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100552#define ID_PFR0 p15, 0, c0, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100553#define ID_PFR1 p15, 0, c0, c1, 1
554#define MAIR0 p15, 0, c10, c2, 0
555#define MAIR1 p15, 0, c10, c2, 1
556#define TTBCR p15, 0, c2, c0, 2
557#define TTBR0 p15, 0, c2, c0, 0
558#define TTBR1 p15, 0, c2, c0, 1
559#define TLBIALL p15, 0, c8, c7, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000560#define TLBIALLH p15, 4, c8, c7, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100561#define TLBIALLIS p15, 0, c8, c3, 0
562#define TLBIMVA p15, 0, c8, c7, 1
563#define TLBIMVAA p15, 0, c8, c7, 3
Antonio Nino Diazac998032017-02-27 17:23:54 +0000564#define TLBIMVAAIS p15, 0, c8, c3, 3
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100565#define TLBIMVAHIS p15, 4, c8, c3, 1
Antonio Nino Diazac998032017-02-27 17:23:54 +0000566#define BPIALLIS p15, 0, c7, c1, 6
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000567#define BPIALL p15, 0, c7, c5, 6
568#define ICIALLU p15, 0, c7, c5, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100569#define HSCTLR p15, 4, c1, c0, 0
570#define HCR p15, 4, c1, c1, 0
571#define HCPTR p15, 4, c1, c1, 2
David Cunadofee86532017-04-13 22:38:29 +0100572#define HSTR p15, 4, c1, c1, 3
Soby Mathewc6820d12016-05-09 17:49:55 +0100573#define CNTHCTL p15, 4, c14, c1, 0
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000574#define CNTKCTL p15, 0, c14, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100575#define VPIDR p15, 4, c0, c0, 0
576#define VMPIDR p15, 4, c0, c0, 5
577#define ISR p15, 0, c12, c1, 0
578#define CLIDR p15, 1, c0, c0, 1
579#define CSSELR p15, 2, c0, c0, 0
580#define CCSIDR p15, 1, c0, c0, 0
johpow0174b7e442021-12-01 13:18:30 -0600581#define CCSIDR2 p15, 1, c0, c0, 2
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100582#define HTCR p15, 4, c2, c0, 2
583#define HMAIR0 p15, 4, c10, c2, 0
Douglas Raillard77414632018-08-21 12:54:45 +0100584#define ATS1CPR p15, 0, c7, c8, 0
585#define ATS1HR p15, 4, c7, c8, 0
Yatharth Kochara9f776c2016-11-10 16:17:51 +0000586#define DBGOSDLR p14, 0, c1, c3, 4
Soby Mathewc6820d12016-05-09 17:49:55 +0100587
David Cunado5f55e282016-10-31 17:37:34 +0000588/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
589#define HDCR p15, 4, c1, c1, 1
David Cunado5f55e282016-10-31 17:37:34 +0000590#define PMCR p15, 0, c9, c12, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000591#define CNTHP_TVAL p15, 4, c14, c2, 0
David Cunadoc14b08e2016-11-25 00:21:59 +0000592#define CNTHP_CTL p15, 4, c14, c2, 1
David Cunado5f55e282016-10-31 17:37:34 +0000593
Etienne Carriere70a004b2017-11-05 22:56:03 +0100594/* AArch32 coproc registers for 32bit MMU descriptor support */
595#define PRRR p15, 0, c10, c2, 0
596#define NMRR p15, 0, c10, c2, 1
597#define DACR p15, 0, c3, c0, 0
598
Soby Mathewc6820d12016-05-09 17:49:55 +0100599/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
600#define ICC_IAR1 p15, 0, c12, c12, 0
601#define ICC_IAR0 p15, 0, c12, c8, 0
602#define ICC_EOIR1 p15, 0, c12, c12, 1
603#define ICC_EOIR0 p15, 0, c12, c8, 1
604#define ICC_HPPIR1 p15, 0, c12, c12, 2
605#define ICC_HPPIR0 p15, 0, c12, c8, 2
606#define ICC_BPR1 p15, 0, c12, c12, 3
607#define ICC_BPR0 p15, 0, c12, c8, 3
608#define ICC_DIR p15, 0, c12, c11, 1
609#define ICC_PMR p15, 0, c4, c6, 0
610#define ICC_RPR p15, 0, c12, c11, 3
611#define ICC_CTLR p15, 0, c12, c12, 4
612#define ICC_MCTLR p15, 6, c12, c12, 4
613#define ICC_SRE p15, 0, c12, c12, 5
614#define ICC_HSRE p15, 4, c12, c9, 5
615#define ICC_MSRE p15, 6, c12, c12, 5
616#define ICC_IGRPEN0 p15, 0, c12, c12, 6
617#define ICC_IGRPEN1 p15, 0, c12, c12, 7
618#define ICC_MGRPEN1 p15, 6, c12, c12, 7
619
620/* 64 bit system register defines The format is: coproc, opt1, CRm */
621#define TTBR0_64 p15, 0, c2
622#define TTBR1_64 p15, 1, c2
623#define CNTVOFF_64 p15, 4, c14
624#define VTTBR_64 p15, 6, c2
625#define CNTPCT_64 p15, 0, c14
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100626#define HTTBR_64 p15, 4, c2
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000627#define CNTHP_CVAL_64 p15, 6, c14
Douglas Raillard77414632018-08-21 12:54:45 +0100628#define PAR_64 p15, 0, c7
Soby Mathewc6820d12016-05-09 17:49:55 +0100629
630/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
631#define ICC_SGI1R_EL1_64 p15, 0, c12
632#define ICC_ASGI1R_EL1_64 p15, 1, c12
633#define ICC_SGI0R_EL1_64 p15, 2, c12
634
Yann Gautier69508e92019-05-21 18:59:18 +0200635/* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */
636#define DFSR p15, 0, c5, c0, 0
637#define IFSR p15, 0, c5, c0, 1
638#define DFAR p15, 0, c6, c0, 0
639#define IFAR p15, 0, c6, c0, 2
640
Isla Mitchell02c63072017-07-21 14:44:36 +0100641/*******************************************************************************
642 * Definitions of MAIR encodings for device and normal memory
643 ******************************************************************************/
644/*
645 * MAIR encodings for device memory attributes.
646 */
647#define MAIR_DEV_nGnRnE U(0x0)
648#define MAIR_DEV_nGnRE U(0x4)
649#define MAIR_DEV_nGRE U(0x8)
650#define MAIR_DEV_GRE U(0xc)
651
652/*
653 * MAIR encodings for normal memory attributes.
654 *
655 * Cache Policy
656 * WT: Write Through
657 * WB: Write Back
658 * NC: Non-Cacheable
659 *
660 * Transient Hint
661 * NTR: Non-Transient
662 * TR: Transient
663 *
664 * Allocation Policy
665 * RA: Read Allocate
666 * WA: Write Allocate
667 * RWA: Read and Write Allocate
668 * NA: No Allocation
669 */
670#define MAIR_NORM_WT_TR_WA U(0x1)
671#define MAIR_NORM_WT_TR_RA U(0x2)
672#define MAIR_NORM_WT_TR_RWA U(0x3)
673#define MAIR_NORM_NC U(0x4)
674#define MAIR_NORM_WB_TR_WA U(0x5)
675#define MAIR_NORM_WB_TR_RA U(0x6)
676#define MAIR_NORM_WB_TR_RWA U(0x7)
677#define MAIR_NORM_WT_NTR_NA U(0x8)
678#define MAIR_NORM_WT_NTR_WA U(0x9)
679#define MAIR_NORM_WT_NTR_RA U(0xa)
680#define MAIR_NORM_WT_NTR_RWA U(0xb)
681#define MAIR_NORM_WB_NTR_NA U(0xc)
682#define MAIR_NORM_WB_NTR_WA U(0xd)
683#define MAIR_NORM_WB_NTR_RA U(0xe)
684#define MAIR_NORM_WB_NTR_RWA U(0xf)
685
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100686#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100687
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100688#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
689 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100690
Douglas Raillard77414632018-08-21 12:54:45 +0100691/* PAR fields */
692#define PAR_F_SHIFT U(0)
693#define PAR_F_MASK ULL(0x1)
694#define PAR_ADDR_SHIFT U(12)
Yann Gautier812c3252018-09-20 15:48:52 +0200695#define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
Douglas Raillard77414632018-08-21 12:54:45 +0100696
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100697/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -0500698 * Definitions for system register interface to AMU for FEAT_AMUv1
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100699 ******************************************************************************/
700#define AMCR p15, 0, c13, c2, 0
701#define AMCFGR p15, 0, c13, c2, 1
702#define AMCGCR p15, 0, c13, c2, 2
703#define AMUSERENR p15, 0, c13, c2, 3
704#define AMCNTENCLR0 p15, 0, c13, c2, 4
705#define AMCNTENSET0 p15, 0, c13, c2, 5
706#define AMCNTENCLR1 p15, 0, c13, c3, 0
Joel Hutton0dcdd8d2017-12-21 15:21:20 +0000707#define AMCNTENSET1 p15, 0, c13, c3, 1
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100708
709/* Activity Monitor Group 0 Event Counter Registers */
710#define AMEVCNTR00 p15, 0, c0
711#define AMEVCNTR01 p15, 1, c0
712#define AMEVCNTR02 p15, 2, c0
713#define AMEVCNTR03 p15, 3, c0
714
715/* Activity Monitor Group 0 Event Type Registers */
716#define AMEVTYPER00 p15, 0, c13, c6, 0
717#define AMEVTYPER01 p15, 0, c13, c6, 1
718#define AMEVTYPER02 p15, 0, c13, c6, 2
719#define AMEVTYPER03 p15, 0, c13, c6, 3
720
Joel Hutton2691bc62017-12-12 15:47:55 +0000721/* Activity Monitor Group 1 Event Counter Registers */
722#define AMEVCNTR10 p15, 0, c4
723#define AMEVCNTR11 p15, 1, c4
724#define AMEVCNTR12 p15, 2, c4
725#define AMEVCNTR13 p15, 3, c4
726#define AMEVCNTR14 p15, 4, c4
727#define AMEVCNTR15 p15, 5, c4
728#define AMEVCNTR16 p15, 6, c4
729#define AMEVCNTR17 p15, 7, c4
730#define AMEVCNTR18 p15, 0, c5
731#define AMEVCNTR19 p15, 1, c5
732#define AMEVCNTR1A p15, 2, c5
733#define AMEVCNTR1B p15, 3, c5
734#define AMEVCNTR1C p15, 4, c5
735#define AMEVCNTR1D p15, 5, c5
736#define AMEVCNTR1E p15, 6, c5
737#define AMEVCNTR1F p15, 7, c5
738
739/* Activity Monitor Group 1 Event Type Registers */
740#define AMEVTYPER10 p15, 0, c13, c14, 0
741#define AMEVTYPER11 p15, 0, c13, c14, 1
742#define AMEVTYPER12 p15, 0, c13, c14, 2
743#define AMEVTYPER13 p15, 0, c13, c14, 3
744#define AMEVTYPER14 p15, 0, c13, c14, 4
745#define AMEVTYPER15 p15, 0, c13, c14, 5
746#define AMEVTYPER16 p15, 0, c13, c14, 6
747#define AMEVTYPER17 p15, 0, c13, c14, 7
748#define AMEVTYPER18 p15, 0, c13, c15, 0
749#define AMEVTYPER19 p15, 0, c13, c15, 1
750#define AMEVTYPER1A p15, 0, c13, c15, 2
751#define AMEVTYPER1B p15, 0, c13, c15, 3
752#define AMEVTYPER1C p15, 0, c13, c15, 4
753#define AMEVTYPER1D p15, 0, c13, c15, 5
754#define AMEVTYPER1E p15, 0, c13, c15, 6
755#define AMEVTYPER1F p15, 0, c13, c15, 7
756
Chris Kaya5fde282021-05-26 11:58:23 +0100757/* AMCNTENSET0 definitions */
758#define AMCNTENSET0_Pn_SHIFT U(0)
759#define AMCNTENSET0_Pn_MASK U(0xffff)
760
761/* AMCNTENSET1 definitions */
762#define AMCNTENSET1_Pn_SHIFT U(0)
763#define AMCNTENSET1_Pn_MASK U(0xffff)
764
765/* AMCNTENCLR0 definitions */
766#define AMCNTENCLR0_Pn_SHIFT U(0)
767#define AMCNTENCLR0_Pn_MASK U(0xffff)
768
769/* AMCNTENCLR1 definitions */
770#define AMCNTENCLR1_Pn_SHIFT U(0)
771#define AMCNTENCLR1_Pn_MASK U(0xffff)
772
johpow01fa59c6f2020-10-02 13:41:11 -0500773/* AMCR definitions */
Chris Kaya5fde282021-05-26 11:58:23 +0100774#define AMCR_CG1RZ_SHIFT U(17)
775#define AMCR_CG1RZ_BIT (ULL(1) << AMCR_CG1RZ_SHIFT)
johpow01fa59c6f2020-10-02 13:41:11 -0500776
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100777/* AMCFGR definitions */
778#define AMCFGR_NCG_SHIFT U(28)
779#define AMCFGR_NCG_MASK U(0xf)
780#define AMCFGR_N_SHIFT U(0)
781#define AMCFGR_N_MASK U(0xff)
782
783/* AMCGCR definitions */
Chris Kaya40141d2021-05-25 12:33:18 +0100784#define AMCGCR_CG0NC_SHIFT U(0)
785#define AMCGCR_CG0NC_MASK U(0xff)
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100786#define AMCGCR_CG1NC_SHIFT U(8)
787#define AMCGCR_CG1NC_MASK U(0xff)
788
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500789/*******************************************************************************
790 * Definitions for DynamicIQ Shared Unit registers
791 ******************************************************************************/
792#define CLUSTERPWRDN p15, 0, c15, c3, 6
793
794/* CLUSTERPWRDN register definitions */
795#define DSU_CLUSTER_PWR_OFF 0
796#define DSU_CLUSTER_PWR_ON 1
797#define DSU_CLUSTER_PWR_MASK U(1)
798
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000799#endif /* ARCH_H */