| developer | 6d207b4 | 2022-07-07 19:30:22 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #define PLAT_PRIMARY_CPU (0x0) |
| 11 | |
| 12 | #define MT_GIC_BASE (0x0C000000) |
| 13 | #define MCUCFG_BASE (0x0C530000) |
| 14 | #define IO_PHYS (0x10000000) |
| 15 | |
| 16 | /* Aggregate of all devices for MMU mapping */ |
| 17 | #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) |
| 18 | #define MTK_DEV_RNG0_SIZE (0x600000) |
| 19 | #define MTK_DEV_RNG1_BASE (IO_PHYS) |
| 20 | #define MTK_DEV_RNG1_SIZE (0x10000000) |
| 21 | |
| 22 | /******************************************************************************* |
| 23 | * UART related constants |
| 24 | ******************************************************************************/ |
| 25 | #define UART0_BASE (IO_PHYS + 0x01002000) |
| 26 | #define UART_BAUDRATE (115200) |
| 27 | |
| 28 | /******************************************************************************* |
| 29 | * System counter frequency related constants |
| 30 | ******************************************************************************/ |
| 31 | #define SYS_COUNTER_FREQ_IN_HZ (13000000) |
| 32 | #define SYS_COUNTER_FREQ_IN_MHZ (13) |
| 33 | |
| 34 | /******************************************************************************* |
| 35 | * Platform binary types for linking |
| 36 | ******************************************************************************/ |
| 37 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 38 | #define PLATFORM_LINKER_ARCH aarch64 |
| 39 | |
| 40 | /******************************************************************************* |
| 41 | * Generic platform constants |
| 42 | ******************************************************************************/ |
| 43 | #define PLATFORM_STACK_SIZE (0x800) |
| 44 | |
| 45 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
| 46 | |
| 47 | #define PLAT_MAX_PWR_LVL U(3) |
| 48 | #define PLAT_MAX_RET_STATE U(1) |
| 49 | #define PLAT_MAX_OFF_STATE U(9) |
| 50 | |
| 51 | #define PLATFORM_SYSTEM_COUNT U(1) |
| 52 | #define PLATFORM_MCUSYS_COUNT U(1) |
| 53 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 54 | #define PLATFORM_CLUSTER0_CORE_COUNT U(8) |
| 55 | #define PLATFORM_CLUSTER1_CORE_COUNT U(0) |
| 56 | |
| 57 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) |
| 58 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) |
| 59 | |
| 60 | #define SOC_CHIP_ID U(0x8188) |
| 61 | |
| 62 | /******************************************************************************* |
| 63 | * Platform memory map related constants |
| 64 | ******************************************************************************/ |
| 65 | #define TZRAM_BASE (0x54600000) |
| 66 | #define TZRAM_SIZE (0x00030000) |
| 67 | |
| 68 | /******************************************************************************* |
| 69 | * BL31 specific defines. |
| 70 | ******************************************************************************/ |
| 71 | /* |
| 72 | * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if |
| 73 | * present). BL31_BASE is calculated using the current BL3-1 debug size plus a |
| 74 | * little space for growth. |
| 75 | */ |
| 76 | #define BL31_BASE (TZRAM_BASE + 0x1000) |
| 77 | #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) |
| 78 | |
| 79 | /******************************************************************************* |
| 80 | * Platform specific page table and MMU setup constants |
| 81 | ******************************************************************************/ |
| 82 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 83 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 84 | #define MAX_XLAT_TABLES (16) |
| 85 | #define MAX_MMAP_REGIONS (16) |
| 86 | |
| 87 | /******************************************************************************* |
| 88 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 89 | * aligned on the biggest cache line size in the platform. This is known only |
| 90 | * to the platform as it might have a combination of integrated and external |
| 91 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 92 | * line at any cache level. They could belong to different cpus/clusters & |
| 93 | * get written while being protected by different locks causing corruption of |
| 94 | * a valid mailbox address. |
| 95 | ******************************************************************************/ |
| 96 | #define CACHE_WRITEBACK_SHIFT (6) |
| 97 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 98 | |
| 99 | #endif /* PLATFORM_DEF_H */ |