| Haojian Zhuang | 3846f14 | 2017-05-24 08:49:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __HISI_IPC_H__ |
| 8 | #define __HISI_IPC_H__ |
| 9 | |
| 10 | #define HISI_IPC_CORE_ACPU 0x0 |
| 11 | |
| 12 | #define HISI_IPC_MCU_INT_SRC_ACPU0_PD 10 |
| 13 | #define HISI_IPC_MCU_INT_SRC_ACPU1_PD 11 |
| 14 | #define HISI_IPC_MCU_INT_SRC_ACPU2_PD 12 |
| 15 | #define HISI_IPC_MCU_INT_SRC_ACPU3_PD 13 |
| 16 | #define HISI_IPC_MCU_INT_SRC_ACPU_PD 16 |
| 17 | #define HISI_IPC_MCU_INT_SRC_ACPU4_PD 26 |
| 18 | #define HISI_IPC_MCU_INT_SRC_ACPU5_PD 27 |
| 19 | #define HISI_IPC_MCU_INT_SRC_ACPU6_PD 28 |
| 20 | #define HISI_IPC_MCU_INT_SRC_ACPU7_PD 29 |
| 21 | |
| 22 | #define HISI_IPC_SEM_CPUIDLE 27 |
| 23 | #define HISI_IPC_INT_SRC_NUM 32 |
| 24 | |
| 25 | #define HISI_IPC_PM_ON 0 |
| 26 | #define HISI_IPC_PM_OFF 1 |
| 27 | |
| 28 | #define HISI_IPC_OK (0) |
| 29 | #define HISI_IPC_ERROR (-1) |
| 30 | |
| 31 | #define HISI_IPC_BASE_ADDR (0xF7510000) |
| 32 | #define HISI_IPC_CPU_RAW_INT_ADDR (0xF7510420) |
| 33 | #define HISI_IPC_ACPU_CTRL(i) (0xF7510800 + (i << 3)) |
| 34 | |
| 35 | void hisi_ipc_spin_lock(unsigned int signal); |
| 36 | void hisi_ipc_spin_unlock(unsigned int signal); |
| 37 | void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster); |
| 38 | void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster); |
| 39 | void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster); |
| 40 | void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster); |
| 41 | void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster); |
| 42 | void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster); |
| 43 | void hisi_ipc_psci_system_off(void); |
| 44 | int hisi_ipc_init(void); |
| 45 | |
| 46 | #endif /* __HISI_IPC_H__ */ |