blob: 29b9d34419c66674304daf70d7eef0de0013a458 [file] [log] [blame]
Yann Gautierbb836ee2018-07-16 17:55:07 +02001/*
2 * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __STM32MP1_I2C_H
8#define __STM32MP1_I2C_H
9
10#include <stdint.h>
11#include <utils_def.h>
12
13/* Bit definition for I2C_CR1 register */
14#define I2C_CR1_PE BIT(0)
15#define I2C_CR1_TXIE BIT(1)
16#define I2C_CR1_RXIE BIT(2)
17#define I2C_CR1_ADDRIE BIT(3)
18#define I2C_CR1_NACKIE BIT(4)
19#define I2C_CR1_STOPIE BIT(5)
20#define I2C_CR1_TCIE BIT(6)
21#define I2C_CR1_ERRIE BIT(7)
22#define I2C_CR1_DNF GENMASK(11, 8)
23#define I2C_CR1_ANFOFF BIT(12)
24#define I2C_CR1_SWRST BIT(13)
25#define I2C_CR1_TXDMAEN BIT(14)
26#define I2C_CR1_RXDMAEN BIT(15)
27#define I2C_CR1_SBC BIT(16)
28#define I2C_CR1_NOSTRETCH BIT(17)
29#define I2C_CR1_WUPEN BIT(18)
30#define I2C_CR1_GCEN BIT(19)
31#define I2C_CR1_SMBHEN BIT(22)
32#define I2C_CR1_SMBDEN BIT(21)
33#define I2C_CR1_ALERTEN BIT(22)
34#define I2C_CR1_PECEN BIT(23)
35
36/* Bit definition for I2C_CR2 register */
37#define I2C_CR2_SADD GENMASK(9, 0)
38#define I2C_CR2_RD_WRN BIT(10)
39#define I2C_CR2_RD_WRN_OFFSET 10U
40#define I2C_CR2_ADD10 BIT(11)
41#define I2C_CR2_HEAD10R BIT(12)
42#define I2C_CR2_START BIT(13)
43#define I2C_CR2_STOP BIT(14)
44#define I2C_CR2_NACK BIT(15)
45#define I2C_CR2_NBYTES GENMASK(23, 16)
46#define I2C_CR2_NBYTES_OFFSET 16U
47#define I2C_CR2_RELOAD BIT(24)
48#define I2C_CR2_AUTOEND BIT(25)
49#define I2C_CR2_PECBYTE BIT(26)
50
51/* Bit definition for I2C_OAR1 register */
52#define I2C_OAR1_OA1 GENMASK(9, 0)
53#define I2C_OAR1_OA1MODE BIT(10)
54#define I2C_OAR1_OA1EN BIT(15)
55
56/* Bit definition for I2C_OAR2 register */
57#define I2C_OAR2_OA2 GENMASK(7, 1)
58#define I2C_OAR2_OA2MSK GENMASK(10, 8)
59#define I2C_OAR2_OA2NOMASK 0
60#define I2C_OAR2_OA2MASK01 BIT(8)
61#define I2C_OAR2_OA2MASK02 BIT(9)
62#define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
63#define I2C_OAR2_OA2MASK04 BIT(10)
64#define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
65#define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
66#define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
67#define I2C_OAR2_OA2EN BIT(15)
68
69/* Bit definition for I2C_TIMINGR register */
70#define I2C_TIMINGR_SCLL GENMASK(7, 0)
71#define I2C_TIMINGR_SCLH GENMASK(15, 8)
72#define I2C_TIMINGR_SDADEL GENMASK(19, 16)
73#define I2C_TIMINGR_SCLDEL GENMASK(23, 20)
74#define I2C_TIMINGR_PRESC GENMASK(31, 28)
75
76/* Bit definition for I2C_TIMEOUTR register */
77#define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0)
78#define I2C_TIMEOUTR_TIDLE BIT(12)
79#define I2C_TIMEOUTR_TIMOUTEN BIT(15)
80#define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16)
81#define I2C_TIMEOUTR_TEXTEN BIT(31)
82
83/* Bit definition for I2C_ISR register */
84#define I2C_ISR_TXE BIT(0)
85#define I2C_ISR_TXIS BIT(1)
86#define I2C_ISR_RXNE BIT(2)
87#define I2C_ISR_ADDR BIT(3)
88#define I2C_ISR_NACKF BIT(4)
89#define I2C_ISR_STOPF BIT(5)
90#define I2C_ISR_TC BIT(6)
91#define I2C_ISR_TCR BIT(7)
92#define I2C_ISR_BERR BIT(8)
93#define I2C_ISR_ARLO BIT(9)
94#define I2C_ISR_OVR BIT(10)
95#define I2C_ISR_PECERR BIT(11)
96#define I2C_ISR_TIMEOUT BIT(12)
97#define I2C_ISR_ALERT BIT(13)
98#define I2C_ISR_BUSY BIT(15)
99#define I2C_ISR_DIR BIT(16)
100#define I2C_ISR_ADDCODE GENMASK(23, 17)
101
102/* Bit definition for I2C_ICR register */
103#define I2C_ICR_ADDRCF BIT(3)
104#define I2C_ICR_NACKCF BIT(4)
105#define I2C_ICR_STOPCF BIT(5)
106#define I2C_ICR_BERRCF BIT(8)
107#define I2C_ICR_ARLOCF BIT(9)
108#define I2C_ICR_OVRCF BIT(10)
109#define I2C_ICR_PECCF BIT(11)
110#define I2C_ICR_TIMOUTCF BIT(12)
111#define I2C_ICR_ALERTCF BIT(13)
112
113struct stm32_i2c_init_s {
114 uint32_t timing; /* Specifies the I2C_TIMINGR_register value
115 * This parameter is calculated by referring
116 * to I2C initialization section in Reference
117 * manual.
118 */
119
120 uint32_t own_address1; /* Specifies the first device own address.
121 * This parameter can be a 7-bit or 10-bit
122 * address.
123 */
124
125 uint32_t addressing_mode; /* Specifies if 7-bit or 10-bit addressing
126 * mode is selected.
127 * This parameter can be a value of @ref
128 * I2C_ADDRESSING_MODE.
129 */
130
131 uint32_t dual_address_mode; /* Specifies if dual addressing mode is
132 * selected.
133 * This parameter can be a value of @ref
134 * I2C_DUAL_ADDRESSING_MODE.
135 */
136
137 uint32_t own_address2; /* Specifies the second device own address
138 * if dual addressing mode is selected.
139 * This parameter can be a 7-bit address.
140 */
141
142 uint32_t own_address2_masks; /* Specifies the acknowledge mask address
143 * second device own address if dual
144 * addressing mode is selected.
145 * This parameter can be a value of @ref
146 * I2C_OWN_ADDRESS2_MASKS.
147 */
148
149 uint32_t general_call_mode; /* Specifies if general call mode is
150 * selected.
151 * This parameter can be a value of @ref
152 * I2C_GENERAL_CALL_ADDRESSING_MODE.
153 */
154
155 uint32_t no_stretch_mode; /* Specifies if nostretch mode is
156 * selected.
157 * This parameter can be a value of @ref
158 * I2C_NOSTRETCH_MODE.
159 */
160
161};
162
163enum i2c_state_e {
164 I2C_STATE_RESET = 0x00U, /* Peripheral is not yet
165 * initialized.
166 */
167 I2C_STATE_READY = 0x20U, /* Peripheral Initialized
168 * and ready for use.
169 */
170 I2C_STATE_BUSY = 0x24U, /* An internal process is
171 * ongoing.
172 */
173 I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission process
174 * is ongoing.
175 */
176 I2C_STATE_BUSY_RX = 0x22U, /* Data Reception process
177 * is ongoing.
178 */
179 I2C_STATE_LISTEN = 0x28U, /* Address Listen Mode is
180 * ongoing.
181 */
182 I2C_STATE_BUSY_TX_LISTEN = 0x29U, /* Address Listen Mode
183 * and Data Transmission
184 * process is ongoing.
185 */
186 I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /* Address Listen Mode
187 * and Data Reception
188 * process is ongoing.
189 */
190 I2C_STATE_ABORT = 0x60U, /* Abort user request ongoing. */
191 I2C_STATE_TIMEOUT = 0xA0U, /* Timeout state. */
192 I2C_STATE_ERROR = 0xE0U /* Error. */
193
194};
195
196enum i2c_mode_e {
197 I2C_MODE_NONE = 0x00U, /* No I2C communication on going. */
198 I2C_MODE_MASTER = 0x10U, /* I2C communication is in Master Mode. */
199 I2C_MODE_SLAVE = 0x20U, /* I2C communication is in Slave Mode. */
200 I2C_MODE_MEM = 0x40U /* I2C communication is in Memory Mode. */
201
202};
203
204#define I2C_ERROR_NONE 0x00000000U /* No error */
205#define I2C_ERROR_BERR 0x00000001U /* BERR error */
206#define I2C_ERROR_ARLO 0x00000002U /* ARLO error */
207#define I2C_ERROR_AF 0x00000004U /* ACKF error */
208#define I2C_ERROR_OVR 0x00000008U /* OVR error */
209#define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */
210#define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */
211#define I2C_ERROR_SIZE 0x00000040U /* Size Management error */
212
213struct i2c_handle_s {
214 uint32_t i2c_base_addr; /* Registers base address */
215
216 struct stm32_i2c_init_s i2c_init; /* Communication parameters */
217
218 uint8_t *p_buff; /* Pointer to transfer buffer */
219
220 uint16_t xfer_size; /* Transfer size */
221
222 uint16_t xfer_count; /* Transfer counter */
223
224 uint32_t prev_state; /* Communication previous
225 * state
226 */
227
228 uint8_t lock; /* Locking object */
229
230 enum i2c_state_e i2c_state; /* Communication state */
231
232 enum i2c_mode_e i2c_mode; /* Communication mode */
233
234 uint32_t i2c_err; /* Error code */
235};
236
237#define I2C_ADDRESSINGMODE_7BIT 0x00000001U
238#define I2C_ADDRESSINGMODE_10BIT 0x00000002U
239
240#define I2C_DUALADDRESS_DISABLE 0x00000000U
241#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
242
243#define I2C_GENERALCALL_DISABLE 0x00000000U
244#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
245
246#define I2C_NOSTRETCH_DISABLE 0x00000000U
247#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
248
249#define I2C_MEMADD_SIZE_8BIT 0x00000001U
250#define I2C_MEMADD_SIZE_16BIT 0x00000002U
251
252#define I2C_RELOAD_MODE I2C_CR2_RELOAD
253#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
254#define I2C_SOFTEND_MODE 0x00000000U
255
256#define I2C_NO_STARTSTOP 0x00000000U
257#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
258#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
259 I2C_CR2_RD_WRN)
260#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
261
262#define I2C_FLAG_TXE I2C_ISR_TXE
263#define I2C_FLAG_TXIS I2C_ISR_TXIS
264#define I2C_FLAG_RXNE I2C_ISR_RXNE
265#define I2C_FLAG_ADDR I2C_ISR_ADDR
266#define I2C_FLAG_AF I2C_ISR_NACKF
267#define I2C_FLAG_STOPF I2C_ISR_STOPF
268#define I2C_FLAG_TC I2C_ISR_TC
269#define I2C_FLAG_TCR I2C_ISR_TCR
270#define I2C_FLAG_BERR I2C_ISR_BERR
271#define I2C_FLAG_ARLO I2C_ISR_ARLO
272#define I2C_FLAG_OVR I2C_ISR_OVR
273#define I2C_FLAG_PECERR I2C_ISR_PECERR
274#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
275#define I2C_FLAG_ALERT I2C_ISR_ALERT
276#define I2C_FLAG_BUSY I2C_ISR_BUSY
277#define I2C_FLAG_DIR I2C_ISR_DIR
278
279#define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
280 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
281 I2C_CR2_RD_WRN)
282
283#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
284#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
285
286int stm32_i2c_init(struct i2c_handle_s *hi2c);
287
288int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
289 uint16_t mem_addr, uint16_t mem_add_size,
290 uint8_t *p_data, uint16_t size, uint32_t timeout);
291int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
292 uint16_t mem_addr, uint16_t mem_add_size,
293 uint8_t *p_data, uint16_t size, uint32_t timeout);
294int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
295 uint32_t trials, uint32_t timeout);
296
297int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c,
298 uint32_t analog_filter);
299
300#endif /* __STM32MP1_I2C_H */