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git01.mediatek.com / filogic / atf / 96f16311ecf9a909a66f7d5ac8a771cadd01b312 / . / include / lib / cpus / aarch64 / cortex_a73.h
blob: 77ea205c24613431d60e391e1ea0af293b21fb64 [file] [log] [blame]
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef CORTEX_A73_H
8#define CORTEX_A73_H
Yatharth Kochar63af6872016-02-09 12:00:03 +0000[diff] [blame]9
10/* Cortex-A73 midr for revision 0 */
11#define CORTEX_A73_MIDR 0x410FD090
12
13/*******************************************************************************
14 * CPU Extended Control register specific definitions.
15 ******************************************************************************/
16#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
17
18#define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6)
19
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]20/*******************************************************************************
21 * L2 Memory Error Syndrome register specific definitions.
22 ******************************************************************************/
23#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
24
Dimitris Papastamose6625ec2018-04-05 14:38:26 +0100[diff] [blame]25/*******************************************************************************
26 * CPU implementation defined register specific definitions.
27 ******************************************************************************/
28#define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0
29
30#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (1 << 3)
31
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]32#endif /* CORTEX_A73_H */