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Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000032#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +000033#include <bakery_lock.h>
34#include <css_def.h>
35#include <mmio.h>
36#include <plat_arm.h>
37#include "css_mhu.h"
38
39/* SCP MHU secure channel registers */
40#define SCP_INTR_S_STAT 0x200
41#define SCP_INTR_S_SET 0x208
42#define SCP_INTR_S_CLEAR 0x210
43
44/* CPU MHU secure channel registers */
45#define CPU_INTR_S_STAT 0x300
46#define CPU_INTR_S_SET 0x308
47#define CPU_INTR_S_CLEAR 0x310
48
49ARM_INSTANTIATE_LOCK
50
51/* Weak definition may be overridden in specific CSS based platform */
52#pragma weak plat_arm_pwrc_setup
53
54
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000055/*
56 * Slot 31 is reserved because the MHU hardware uses this register bit to
57 * indicate a non-secure access attempt. The total number of available slots is
58 * therefore 31 [30:0].
59 */
60#define MHU_MAX_SLOT_ID 30
61
62void mhu_secure_message_start(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000063{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000064 assert(slot_id <= MHU_MAX_SLOT_ID);
65
Dan Handley9df48042015-03-19 18:58:55 +000066 arm_lock_get();
67
68 /* Make sure any previous command has finished */
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000069 while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id))
Dan Handley9df48042015-03-19 18:58:55 +000070 ;
71}
72
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000073void mhu_secure_message_send(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000074{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000075 assert(slot_id <= MHU_MAX_SLOT_ID);
76 assert(!(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id)));
77
78 /* Send command to SCP */
79 mmio_write_32(MHU_BASE + CPU_INTR_S_SET, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +000080}
81
82uint32_t mhu_secure_message_wait(void)
83{
84 /* Wait for response from SCP */
85 uint32_t response;
86 while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT)))
87 ;
88
89 return response;
90}
91
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000092void mhu_secure_message_end(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000093{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000094 assert(slot_id <= MHU_MAX_SLOT_ID);
95
Dan Handley9df48042015-03-19 18:58:55 +000096 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000097 * Clear any response we got by writing one in the relevant slot bit to
98 * the CLEAR register
Dan Handley9df48042015-03-19 18:58:55 +000099 */
Sandrine Bailleux04b66d82015-03-18 14:52:53 +0000100 mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +0000101
102 arm_lock_release();
103}
104
105void mhu_secure_init(void)
106{
107 arm_lock_init();
108
109 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +0000110 * The STAT register resets to zero. Ensure it is in the expected state,
111 * as a stale or garbage value would make us think it's a message we've
112 * already sent.
Dan Handley9df48042015-03-19 18:58:55 +0000113 */
Sandrine Bailleux04b66d82015-03-18 14:52:53 +0000114 assert(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) == 0);
Dan Handley9df48042015-03-19 18:58:55 +0000115}
116
117void plat_arm_pwrc_setup(void)
118{
119 mhu_secure_init();
120}