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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -07002 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef VERSAL_DEF_H
8#define VERSAL_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <plat/common/common_def.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053011
12/* List all consoles */
13#define VERSAL_CONSOLE_ID_pl011 1
14#define VERSAL_CONSOLE_ID_pl011_0 1
15#define VERSAL_CONSOLE_ID_pl011_1 2
16#define VERSAL_CONSOLE_ID_dcc 3
17
18#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
19
20/* List all supported platforms */
21#define VERSAL_PLATFORM_ID_versal_virt 1
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053022#define VERSAL_PLATFORM_ID_silicon 4
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053023
24#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
25
26/* Firmware Image Package */
27#define VERSAL_PRIMARY_CPU 0
28
29/*******************************************************************************
30 * memory map related constants
31 ******************************************************************************/
32#define DEVICE0_BASE 0xFF000000
33#define DEVICE0_SIZE 0x00E00000
34#define DEVICE1_BASE 0xF9000000
35#define DEVICE1_SIZE 0x00800000
36
37/* CRL */
38#define VERSAL_CRL 0xFF5E0000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053039#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C)
40#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348)
41
42#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053043
44/* IOU SCNTRS */
45#define VERSAL_IOU_SCNTRS 0xFF140000
46#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0)
47#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20)
48
49#define VERSAL_IOU_SCNTRS_CONTROL_EN 1
50
51/*******************************************************************************
52 * IRQ constants
53 ******************************************************************************/
54#define VERSAL_IRQ_SEC_PHY_TIMER 29
55
56/*******************************************************************************
Tejas Patel54d13192019-02-27 18:44:55 +053057 * CCI-400 related constants
58 ******************************************************************************/
59#define PLAT_ARM_CCI_BASE 0xFD000000
60#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
61#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
62
63/*******************************************************************************
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053064 * UART related constants
65 ******************************************************************************/
66#define VERSAL_UART0_BASE 0xFF000000
67#define VERSAL_UART1_BASE 0xFF010000
68
69#if VERSAL_CONSOLE_IS(pl011)
70# define VERSAL_UART_BASE VERSAL_UART0_BASE
71#elif VERSAL_CONSOLE_IS(pl011_1)
72# define VERSAL_UART_BASE VERSAL_UART1_BASE
73#else
74# error "invalid VERSAL_CONSOLE"
75#endif
76
77#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
78#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
79#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
80
81/*******************************************************************************
82 * Platform related constants
83 ******************************************************************************/
84#if VERSAL_PLATFORM_IS(versal_virt)
85# define PLATFORM_NAME "Versal Virt"
86# define VERSAL_UART_CLOCK 25000000
87# define VERSAL_UART_BAUDRATE 115200
Siva Durga Prasad Paladugu10161e52019-04-27 11:23:20 +053088# define VERSAL_CPU_CLOCK 2720000
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053089#elif VERSAL_PLATFORM_IS(silicon)
90# define PLATFORM_NAME "Versal Silicon"
91# define VERSAL_UART_CLOCK 100000000
92# define VERSAL_UART_BAUDRATE 115200
93# define VERSAL_CPU_CLOCK 100000000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053094#endif
95
96/* Access control register defines */
97#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
98#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
99
100/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
101#define CRF_BASE 0xFD1A0000
102#define CRF_SIZE 0x00600000
103
104/* CRF registers and bitfields */
105#define CRF_RST_APU (CRF_BASE + 0X00000300)
106
107#define CRF_RST_APU_ACPU_RESET (1 << 0)
108#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
109
Tejas Patel54d13192019-02-27 18:44:55 +0530110#define FPD_MAINCCI_BASE 0xFD000000
111#define FPD_MAINCCI_SIZE 0x00100000
112
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530113/* APU registers and bitfields */
114#define FPD_APU_BASE 0xFD5C0000
115#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20)
116#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40)
117#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44)
118#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90)
119
120#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8
Tejas Patelfe0e10a2019-12-08 23:29:44 -0800121#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
122#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530123
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700124/* PMC registers and bitfields */
125#define PMC_GLOBAL_BASE 0xF1110000
126#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40)
127
Tejas Patel354fe572018-12-14 00:55:37 -0800128/* IPI registers and bitfields */
129#define IPI0_REG_BASE 0xFF330000
130#define IPI0_TRIG_BIT (1 << 2)
131#define PMC_IPI_TRIG_BIT (1 << 1)
132#define IPI1_REG_BASE 0xFF340000
133#define IPI1_TRIG_BIT (1 << 3)
134#define IPI2_REG_BASE 0xFF350000
135#define IPI2_TRIG_BIT (1 << 4)
136#define IPI3_REG_BASE 0xFF360000
137#define IPI3_TRIG_BIT (1 << 5)
138#define IPI4_REG_BASE 0xFF370000
139#define IPI4_TRIG_BIT (1 << 5)
140#define IPI5_REG_BASE 0xFF380000
141#define IPI5_TRIG_BIT (1 << 6)
142
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530143#endif /* VERSAL_DEF_H */